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authorMukul Joshi2022-03-02 21:40:38 -0500
committerAlex Deucher2023-06-09 09:43:09 -0400
commita8027fcd08f9127d38edeb59600ecb76c56a121a (patch)
tree1313c2d7e0fa18908341606bbb84f80e8585c668 /include
parenta805889a15315f7fa78c1c4bb2f1875c7c43f919 (diff)
drm/amdgpu: Fix CP_HYP_XCP_CTL register programming in CPX mode
Currently, in CPX mode, the CP_HYP_XCP_CTL register is programmed incorrectly with the number of XCCs in the partition. As a result, HIQ doesn't work in CPX mode. Fix this by programming the correct number of XCCs in a partition, which is 1, in CPX mode. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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