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authorDimitris Papavasiliou2019-01-26 15:23:45 +0200
committerMark Brown2019-01-28 12:34:14 +0000
commit51b033c2608147efe3a5368bfa64837e772d8c55 (patch)
tree6a2a8b724c77dc449e7dc7f40c3e2c0d7fc7fa37 /include
parentccc8d6c7b6d2f521a4b10c7f6d027f46c7a686bf (diff)
ASoC: pcm512x: Fix clocking calculations when not using the PLL
The rationale behind the current calculation is somewhat obscure [1] and can yield slightly wrong dividers in certain cases, which the machine drivers for some boards (like the HiFiBerry DAC+ Pro) seemingly try to circumvent, by updating the rate fraction so as to suit this calculation. The updated calculation should correctly yield the smallest bit clock rate that would fit the frame. [1] http://mailman.alsa-project.org/pipermail/alsa-devel/2019-January/144219.html Signed-off-by: Dimitris Papavasiliou <dpapavas@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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