aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorDhaval Shah2017-12-21 10:33:06 -0800
committerMichal Simek2018-01-08 13:42:47 +0100
commitcee8113a295acfc4cd25728d7c3d44e6bc3bbff9 (patch)
tree9f5bf6d034f9120fb26e46593fbab85dbf4cc8d0 /include
parentb7511552f920c8c273912353a8c8bf65e8f84fdc (diff)
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
Xilinx ZYNQMP logicoreIP Init driver is based on the new LogiCoreIP design created. This driver provides the processing system and programmable logic isolation. Set the frequency based on the clock information get from the logicoreIP register set. Signed-off-by: Dhaval Shah <dshah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions