diff options
| author | Bjorn Helgaas | 2019-11-28 08:54:32 -0600 |
|---|---|---|
| committer | Bjorn Helgaas | 2019-11-28 08:54:32 -0600 |
| commit | e87eb585d31fadb5e9e549a1de4b2da60a79bfc9 (patch) | |
| tree | c52a36975d14b8042d31ea5663c24a49d8138d21 /include | |
| parent | 2df08822a643558402b7c58528b8478e31e40ad7 (diff) | |
| parent | 3d581b11e34a92350983e5d3ecf469b5c677e295 (diff) | |
Merge branch 'pci/misc'
- Add NumaChip SPDX header (Krzysztof Wilczynski)
- Replace EXTRA_CFLAGS with ccflags-y (Krzysztof Wilczynski)
- Remove unused includes (Krzysztof Wilczynski)
- Avoid AMD FCH XHCI USB PME# from D0 defect that prevents wakeup on USB
2.0 or 1.1 connect events (Kai-Heng Feng)
- Removed unused sysfs attribute groups (Ben Dooks)
- Remove PTM and ASPM dependencies on PCIEPORTBUS (Bjorn Helgaas)
- Add PCIe Link Control 2 register field definitions to replace magic
numbers in AMDGPU and Radeon CIK/SI (Bjorn Helgaas)
- Fix incorrect Link Control 2 Transmit Margin usage in AMDGPU and Radeon
CIK/SI PCIe Gen3 link training (Bjorn Helgaas)
- Use pcie_capability_read_word() instead of pci_read_config_word() in
AMDGPU and Radeon CIK/SI (Frederick Lawler)
* pci/misc:
drm/radeon: Prefer pcie_capability_read_word()
drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions
drm/radeon: Correct Transmit Margin masks
drm/amdgpu: Prefer pcie_capability_read_word()
drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions
drm/amdgpu: Correct Transmit Margin masks
PCI: Add #defines for Enter Compliance, Transmit Margin
PCI: Allow building PCIe things without PCIEPORTBUS
PCI: Remove PCIe Kconfig dependencies on PCI
PCI/ASPM: Remove dependency on PCIEPORTBUS
PCI/PTM: Remove dependency on PCIEPORTBUS
PCI/PTM: Remove spurious "d" from granularity message
PCI: sysfs: Remove unused attribute groups
x86/PCI: Avoid AMD FCH XHCI USB PME# from D0 defect
PCI: Remove unused includes and superfluous struct declaration
x86/PCI: Replace deprecated EXTRA_CFLAGS with ccflags-y
x86/PCI: Correct SPDX comment style
x86/PCI: Add NumaChip SPDX GPL-2.0 to replace COPYING boilerplate
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/of_pci.h | 5 | ||||
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index 21a89c4880fa..29658c0ee71f 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -2,11 +2,10 @@ #ifndef __OF_PCI_H #define __OF_PCI_H -#include <linux/pci.h> -#include <linux/msi.h> +#include <linux/types.h> +#include <linux/errno.h> struct pci_dev; -struct of_phandle_args; struct device_node; #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PCI) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 29d6e93fd15e..5869e5778a05 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -673,6 +673,8 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ |