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authorJesse Barnes2011-10-16 10:23:31 +0200
committerKeith Packard2011-10-20 15:26:41 -0700
commit8d31528703ceda6f631e39953130abe9b3ca52b2 (patch)
treef64ff55c111adb9e479cad97ceede6174b824aa6 /kernel/dma.c
parent9d971b37534fb268251f74cc04a36a0a16f7da04 (diff)
drm/i915: Use PIPE_CONTROL for flushing on gen6+.
v2 by danvet: Use a new flag to flush the render target cache on gen6+ (hw reuses the old write flush bit), as suggested by Ben Widawsdy. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [danvet: this seems to fix cairo-perf-trace hangs on my snb] Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Keith Packard <keithp@keithp.com>
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