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authorKoji Matsuoka2016-05-16 11:28:15 +0900
committerLaurent Pinchart2016-11-15 01:44:50 +0200
commitfd1adef3bff0663c5ac31b45bc4a05fafd43d19b (patch)
tree4e8895caca0db0d50f0551e4c134a6ba1cc99f90 /mm/kmemcheck.c
parent9cdced8a39c04cf798ddb2a27cb5952f7d39f633 (diff)
drm: rcar-du: Fix H/V sync signal polarity configuration
The VSL and HSL bits in the DSMR register set the corresponding horizontal and vertical sync signal polarity to active high. The code got it the wrong way around, fix it. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'mm/kmemcheck.c')
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