diff options
| author | Zhong Kaihua | 2017-08-07 22:51:56 +0800 |
|---|---|---|
| committer | Stephen Boyd | 2017-11-14 09:48:59 -0800 |
| commit | d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8 (patch) | |
| tree | 3cbf8228d5ff1de69e50ed66726e281e0ecabb86 /net/mpls/mpls_gso.c | |
| parent | d2a3671ebe6479483a12f94fcca63c058d95ad64 (diff) | |
clk: hi3660: fix incorrect uart3 clock freqency
UART3 clock rate is doubled in previous commit.
This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.
This patch changes clock source rate of clk_factor_uart3 to 100000000.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'net/mpls/mpls_gso.c')
0 files changed, 0 insertions, 0 deletions