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authorNicholas Piggin2021-11-23 19:52:21 +1000
committerMichael Ellerman2021-11-24 21:09:01 +1100
commitd5c0e8332d82c04deee25dd6f28c5bbe84d49a73 (patch)
tree2701105bb0b52f1c89fd6f08ca6647fee5fa5397 /net/rose/Makefile
parent0ba0e5d5a691806cca3d4f290dcc61f656049872 (diff)
KVM: PPC: Book3S HV P9: Avoid tlbsync sequence on radix guest exit
Use the existing TLB flushing logic to IPI the previous CPU and run the necessary barriers before running a guest vCPU on a new physical CPU, to do the necessary radix GTSE barriers for handling the case of an interrupted guest tlbie sequence. This requires the vCPU TLB flush sequence that is currently just done on one thread, to be expanded to ensure the other threads execute a ptesync, because causing them to exit the guest will no longer cause a ptesync by itself. This results in more IPIs than the TLB flush logic requires, but it's a significant win for common case scheduling when the vCPU remains on the same physical CPU. This saves about 520 cycles (nearly 10%) on a guest entry+exit micro benchmark on a POWER9. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20211123095231.1036501-44-npiggin@gmail.com
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