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author | Sergei Shtylyov | 2018-06-26 18:42:33 +0300 |
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committer | David S. Miller | 2018-06-28 16:02:04 +0900 |
commit | 782e85c5f7aee0294cefb52a190b05e082c178d5 (patch) | |
tree | 401a187ebb0f12d342af085d5a563dd0fd8fb838 /samples/watchdog | |
parent | 5092ad4dd52dddc9957ebb8adde99f7a22c29f6a (diff) |
sh_eth: fix *enum* {A|M}PR_BIT
The *enum* {A|M}PR_BIT were declared in the commit 86a74ff21a7a ("net:
sh_eth: add support for Renesas SuperH Ethernet") adding SH771x support,
however the SH771x manual doesn't have the APR/MPR registers described
and the code writing to them for SH7710 was later removed by the commit
380af9e390ec ("net: sh_eth: CPU dependency code collect to "struct
sh_eth_cpu_data""). All the newer SoC manuals have these registers
documented as having a 16-bit TIME parameter of the PAUSE frame, not
1-bit -- update the *enum* accordingly, fixing up the APR/MPR writes...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'samples/watchdog')
0 files changed, 0 insertions, 0 deletions