diff options
author | Kuninori Morimoto | 2015-11-17 08:28:11 +0000 |
---|---|---|
committer | Mark Brown | 2015-11-17 11:43:46 +0000 |
commit | f46a93b820eb3707faf238cd769a004e2504515f (patch) | |
tree | de6cdba2145806fc7509bf9cce085ca043162bc9 /sound/soc | |
parent | 85d4a62140def5402bed3c6b914f6faafa185490 (diff) |
ASoC: rsnd: ssi: 24bit data needs right-aligned settings
Data left/right aligned is controlled by PDTA bit on SSICR.
But default is left-aligned. Thus 24bit sound will be very small sound
without this patch.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc')
-rw-r--r-- | sound/soc/sh/rcar/ssi.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/sound/soc/sh/rcar/ssi.c b/sound/soc/sh/rcar/ssi.c index 3e814711f301..60ef074082e8 100644 --- a/sound/soc/sh/rcar/ssi.c +++ b/sound/soc/sh/rcar/ssi.c @@ -39,6 +39,7 @@ #define SCKP (1 << 13) /* Serial Bit Clock Polarity */ #define SWSP (1 << 12) /* Serial WS Polarity */ #define SDTA (1 << 10) /* Serial Data Alignment */ +#define PDTA (1 << 9) /* Parallel Data Alignment */ #define DEL (1 << 8) /* Serial Data Delay */ #define CKDV(v) (v << 4) /* Serial Clock Division Ratio */ #define TRMD (1 << 1) /* Transmit/Receive Mode Select */ @@ -274,7 +275,7 @@ static int rsnd_ssi_init(struct rsnd_mod *mod, if (rsnd_ssi_is_parent(mod, io)) return 0; - cr = FORCE; + cr = FORCE | PDTA; /* * always use 32bit system word for easy clock calculation. |