diff options
| author | Mengdong Lin | 2015-04-20 17:33:57 +0800 |
|---|---|---|
| committer | Takashi Iwai | 2015-04-20 17:27:55 +0200 |
| commit | f4c1a311d8dc55c90c39e9cf7b003254a769574d (patch) | |
| tree | bb09e34b0fb05c7280b151a3528a13feebd1af6d /sound | |
| parent | 9476d369d7b39348945c297da5f2935904229813 (diff) | |
ALSA: hda - only sync BCLK to the display clock for Haswell & Broadwell
Only Intel Haswell and Broadwell have a separate HD-A controller (PCI device 3)
for display audio, which needs to get 24MHz HD-A link BCLK from the variable
display core clock through vendor specific registers EM4 & EM5. Other platforms
(Baytrail, Braswell and Skylake) don't have this feature.
So this patch checks the PCI device ID of the controller in haswell_set_bclk()
and only sync BCLK for HSW and BDW.
Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/pci/hda/hda_i915.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sound/pci/hda/hda_i915.c b/sound/pci/hda/hda_i915.c index 52a85d87c23c..3052a2b095f7 100644 --- a/sound/pci/hda/hda_i915.c +++ b/sound/pci/hda/hda_i915.c @@ -55,6 +55,12 @@ void haswell_set_bclk(struct hda_intel *hda) int cdclk_freq; unsigned int bclk_m, bclk_n; struct i915_audio_component *acomp = &hda->audio_component; + struct pci_dev *pci = hda->chip.pci; + + /* Only Haswell/Broadwell need set BCLK */ + if (pci->device != 0x0a0c && pci->device != 0x0c0c + && pci->device != 0x0d0c && pci->device != 0x160c) + return; if (!acomp->ops) return; |