diff options
| author | Bard Liao | 2015-04-28 11:27:39 +0800 |
|---|---|---|
| committer | Mark Brown | 2015-04-29 12:19:45 +0100 |
| commit | 60a8d62b8497c23eb3d48149af7e55dac2dd83a2 (patch) | |
| tree | 003e7199410f6df5b920c180c5b7bfc175efda07 /sound | |
| parent | 74d6ea52aeef0236242221c6eff6d892565c5a92 (diff) | |
ASoC: rt5677: fixed wrong DMIC ref clock
DMIC clock source is not from codec system clock directly. it is
generated from the division of system clock. And it should be 256 *
sample rate of AIF1.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/codecs/rt5677.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c index c6d4e8fa8bd3..84d162d91ff6 100644 --- a/sound/soc/codecs/rt5677.c +++ b/sound/soc/codecs/rt5677.c @@ -904,7 +904,7 @@ static int set_dmic_clk(struct snd_soc_dapm_widget *w, { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); - int idx = rl6231_calc_dmic_clk(rt5677->sysclk); + int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8); if (idx < 0) dev_err(codec->dev, "Failed to set DMIC clock\n"); |