diff options
| author | Arnaldo Carvalho de Melo | 2020-12-17 14:46:24 -0300 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo | 2020-12-18 17:32:28 -0300 |
| commit | e9bde94f1eb53c5721ba8e477dee837632fedebe (patch) | |
| tree | 3d1256201482f9ebb03e3d948fe9d3a6cc474354 /tools/include | |
| parent | eb2842da77e1f7a3c46033f930524ab76dffe67a (diff) | |
tools arch x86: Sync the msr-index.h copy with the kernel sources
To pick up the changes in:
d205e0f1426e0f99 ("x86/{cpufeatures,msr}: Add Intel SGX Launch Control hardware bits")
e7b6385b01d8e9fb ("x86/cpufeatures: Add Intel SGX hardware bits")
43756a298928c9a4 ("powercap: Add AMD Fam17h RAPL support")
298ed2b31f552806 ("x86/msr-index: sort AMD RAPL MSRs by address")
68299a42f8428853 ("x86/mce: Enable additional error logging on certain Intel CPUs")
That cause these changes in tooling:
$ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
$ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
$ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
$ diff -u before after
--- before 2020-12-17 14:45:49.036994450 -0300
+++ after 2020-12-17 14:46:01.654256639 -0300
@@ -22,6 +22,10 @@
[0x00000060] = "LBR_CORE_TO",
[0x00000079] = "IA32_UCODE_WRITE",
[0x0000008b] = "IA32_UCODE_REV",
+ [0x0000008C] = "IA32_SGXLEPUBKEYHASH0",
+ [0x0000008D] = "IA32_SGXLEPUBKEYHASH1",
+ [0x0000008E] = "IA32_SGXLEPUBKEYHASH2",
+ [0x0000008F] = "IA32_SGXLEPUBKEYHASH3",
[0x0000009b] = "IA32_SMM_MONITOR_CTL",
[0x0000009e] = "IA32_SMBASE",
[0x000000c1] = "IA32_PERFCTR0",
@@ -59,6 +63,7 @@
[0x00000179] = "IA32_MCG_CAP",
[0x0000017a] = "IA32_MCG_STATUS",
[0x0000017b] = "IA32_MCG_CTL",
+ [0x0000017f] = "ERROR_CONTROL",
[0x00000180] = "IA32_MCG_EAX",
[0x00000181] = "IA32_MCG_EBX",
[0x00000182] = "IA32_MCG_ECX",
@@ -294,6 +299,7 @@
[0xc0010241 - x86_AMD_V_KVM_MSRs_offset] = "F15H_NB_PERF_CTR",
[0xc0010280 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PTSC",
[0xc0010299 - x86_AMD_V_KVM_MSRs_offset] = "AMD_RAPL_POWER_UNIT",
+ [0xc001029a - x86_AMD_V_KVM_MSRs_offset] = "AMD_CORE_ENERGY_STATUS",
[0xc001029b - x86_AMD_V_KVM_MSRs_offset] = "AMD_PKG_ENERGY_STATUS",
[0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN_CTL",
[0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN",
$
Which causes these parts of tools/perf/ to be rebuilt:
CC /tmp/build/perf/trace/beauty/tracepoints/x86_msr.o
LD /tmp/build/perf/trace/beauty/tracepoints/perf-in.o
LD /tmp/build/perf/trace/beauty/perf-in.o
LD /tmp/build/perf/perf-in.o
LINK /tmp/build/perf/perf
At some point these should just be tables read by perf on demand.
This allows 'perf trace' users to use those strings to translate from
the msr ids provided by the msr: tracepoints.
This addresses this perf tools build warning:
diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/msr-index.h' differs from latest version at 'arch/x86/include/asm/msr-index.h'
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Victor Ding <victording@google.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/include')
0 files changed, 0 insertions, 0 deletions