diff options
| author | Srinivas Pandruvada | 2019-11-19 16:22:54 -0800 |
|---|---|---|
| committer | Andy Shevchenko | 2019-11-21 14:31:34 +0200 |
| commit | 1434a3d357d656d4b11fcbdc9b6c35dc673292a0 (patch) | |
| tree | f049f8e4933a3a877eedbcfc6d96737b6075ab4f /tools/power | |
| parent | 20183ccd3e4d01d23b0a01fe9f3ee73fbae312fa (diff) | |
tools/power/x86/intel-speed-select: Display TRL buckets for just base config level
When only base config level is present, this tool is displaying TRL
(Turbo-ratio-limits) by reading legacy MSR. In this case, also present
core count for TRL by reading MSR 0x1AE.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'tools/power')
| -rw-r--r-- | tools/power/x86/intel-speed-select/isst-core.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tools/power/x86/intel-speed-select/isst-core.c b/tools/power/x86/intel-speed-select/isst-core.c index aa19c9998e6c..d14c7bcd327a 100644 --- a/tools/power/x86/intel-speed-select/isst-core.c +++ b/tools/power/x86/intel-speed-select/isst-core.c @@ -681,6 +681,7 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev) } isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores); + isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info); continue; } |