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authorCharlie Jenkins2024-07-02 18:54:48 -0700
committerPalmer Dabbelt2024-07-03 13:04:54 -0700
commit3582ce0d7ccf2ee0eca66e5928e5550b8fc84e57 (patch)
treed6a53271b3daa41eda91be6dca8ddb4de8870858 /tools
parent210ac17dedc9810d744ae52f8780278211a490aa (diff)
riscv: selftests: Fix vsetivli args for clang
Clang does not support implicit LMUL in the vset* instruction sequences. Introduce an explicit LMUL in the vsetivli instruction. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Fixes: 9d5328eeb185 ("riscv: selftests: Add signal handling vector tests") Link: https://lore.kernel.org/r/20240702-fix_sigreturn_test-v1-1-485f88a80612@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools')
-rw-r--r--tools/testing/selftests/riscv/sigreturn/sigreturn.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/testing/selftests/riscv/sigreturn/sigreturn.c b/tools/testing/selftests/riscv/sigreturn/sigreturn.c
index 62397d5934f1..ed351a1cb917 100644
--- a/tools/testing/selftests/riscv/sigreturn/sigreturn.c
+++ b/tools/testing/selftests/riscv/sigreturn/sigreturn.c
@@ -51,7 +51,7 @@ static int vector_sigreturn(int data, void (*handler)(int, siginfo_t *, void *))
asm(".option push \n\
.option arch, +v \n\
- vsetivli x0, 1, e32, ta, ma \n\
+ vsetivli x0, 1, e32, m1, ta, ma \n\
vmv.s.x v0, %1 \n\
# Generate SIGSEGV \n\
lw a0, 0(x0) \n\