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authorBiju Das2022-04-25 10:52:41 +0100
committerGeert Uytterhoeven2022-04-28 16:37:44 +0200
commit666b5a010ef1e8d08227f5aa6e5b431ce0feca07 (patch)
tree29be5101a5f5e778c1439f764d40abc7dce77883 /virt
parentbe5b5fcbc779f04a6ad38e9d4772712fe05b6f15 (diff)
clk: renesas: r9a07g043: Add USB clocks/resets
Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'virt')
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