diff options
| -rw-r--r-- | arch/powerpc/Kconfig | 5 | ||||
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 10 | ||||
| -rw-r--r-- | arch/powerpc/mm/8xx_mmu.c | 12 |
3 files changed, 19 insertions, 8 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 394f9dc7be08..fcfe5332416f 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -1056,6 +1056,11 @@ config CONSISTENT_SIZE config PIN_TLB bool "Pinned Kernel TLBs (860 ONLY)" depends on ADVANCED_OPTIONS && 8xx + +config PIN_TLB_IMMR + bool "Pinned TLB for IMMR" + depends on PIN_TLB + default y endmenu if PPC64 diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 00cc9df7d322..43ddaae42baf 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -414,11 +414,11 @@ DataStoreTLBMiss: */ mfspr r11, SPRN_MD_EPN rlwinm r11, r11, 16, 0xfff8 -#ifndef CONFIG_PIN_TLB +#ifndef CONFIG_PIN_TLB_IMMR cmpli cr0, r11, VIRT_IMMR_BASE@h #endif cmpli cr7, r11, PAGE_OFFSET@h -#ifndef CONFIG_PIN_TLB +#ifndef CONFIG_PIN_TLB_IMMR _ENTRY(DTLBMiss_jmp) beq- DTLBMissIMMR #endif @@ -819,7 +819,6 @@ initial_mmu: #ifdef CONFIG_PIN_TLB oris r10, r10, MD_RSV4I@h - ori r10, r10, 0x1c00 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ #endif @@ -843,7 +842,10 @@ initial_mmu: /* Map a 512k page for the IMMR to get the processor * internal registers (among other things). */ -#ifdef CONFIG_PIN_TLB +#ifdef CONFIG_PIN_TLB_IMMR + ori r10, r10, 0x1c00 + mtspr SPRN_MD_CTR, r10 + mfspr r9, 638 /* Get current IMMR */ andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */ diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c index 0f0a83ed7a20..6c5025e81236 100644 --- a/arch/powerpc/mm/8xx_mmu.c +++ b/arch/powerpc/mm/8xx_mmu.c @@ -61,11 +61,15 @@ void __init MMU_init_hw(void) #ifdef CONFIG_PIN_TLB unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000; unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY; - int i; +#ifdef CONFIG_PIN_TLB_IMMR + int i = 29; +#else + int i = 28; +#endif unsigned long addr = 0; unsigned long mem = total_lowmem; - for (i = 29; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) { + for (; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) { mtspr(SPRN_MD_CTR, ctr | (i << 8)); mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) | MD_EVALID); mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID); @@ -88,7 +92,7 @@ static void mmu_mapin_immr(void) } /* Address of instructions to patch */ -#ifndef CONFIG_PIN_TLB +#ifndef CONFIG_PIN_TLB_IMMR extern unsigned int DTLBMiss_jmp; #endif extern unsigned int DTLBMiss_cmp, FixupDAR_cmp; @@ -109,7 +113,7 @@ unsigned long __init mmu_mapin_ram(unsigned long top) if (__map_without_ltlbs) { mapped = 0; mmu_mapin_immr(); -#ifndef CONFIG_PIN_TLB +#ifndef CONFIG_PIN_TLB_IMMR patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP); #endif } else { |