diff options
| -rw-r--r-- | arch/mips/Makefile | 6 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/Makefile (renamed from arch/mips/nxp/pnx8550/common/Makefile) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/int.c (renamed from arch/mips/nxp/pnx8550/common/int.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/pci.c | 134 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/platform.c (renamed from arch/mips/nxp/pnx8550/common/platform.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/proc.c (renamed from arch/mips/nxp/pnx8550/common/proc.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/prom.c (renamed from arch/mips/nxp/pnx8550/common/prom.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/reset.c (renamed from arch/mips/nxp/pnx8550/common/reset.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/setup.c | 145 | ||||
| -rw-r--r-- | arch/mips/pnx8550/common/time.c (renamed from arch/mips/nxp/pnx8550/common/time.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/jbs/Makefile (renamed from arch/mips/nxp/pnx8550/jbs/Makefile) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/jbs/board_setup.c (renamed from arch/mips/nxp/pnx8550/jbs/board_setup.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/jbs/init.c (renamed from arch/mips/nxp/pnx8550/jbs/init.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/jbs/irqmap.c (renamed from arch/mips/nxp/pnx8550/jbs/irqmap.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/stb810/Makefile (renamed from arch/mips/nxp/pnx8550/stb810/Makefile) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/stb810/board_setup.c (renamed from arch/mips/nxp/pnx8550/stb810/board_setup.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/stb810/irqmap.c (renamed from arch/mips/nxp/pnx8550/stb810/irqmap.c) | 0 | ||||
| -rw-r--r-- | arch/mips/pnx8550/stb810/prom_init.c (renamed from arch/mips/nxp/pnx8550/stb810/prom_init.c) | 0 |
18 files changed, 282 insertions, 3 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0556bc41e76d..ac50de18b6a4 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -202,19 +202,19 @@ load-$(CONFIG_NXP_STB225) += 0xffffffff80001000 # # Common NXP PNX8550 # -core-$(CONFIG_SOC_PNX8550) += arch/mips/nxp/pnx8550/common/ +core-$(CONFIG_SOC_PNX8550) += arch/mips/pnx8550/common/ cflags-$(CONFIG_SOC_PNX8550) += -I$(srctree)/arch/mips/include/asm/mach-pnx8550 # # NXP PNX8550 JBS board # -libs-$(CONFIG_PNX8550_JBS) += arch/mips/nxp/pnx8550/jbs/ +libs-$(CONFIG_PNX8550_JBS) += arch/mips/pnx8550/jbs/ #cflags-$(CONFIG_PNX8550_JBS) += -I$(srctree)/arch/mips/include/asm/mach-pnx8550 load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 # NXP PNX8550 STB810 board # -libs-$(CONFIG_PNX8550_STB810) += arch/mips/nxp/pnx8550/stb810/ +libs-$(CONFIG_PNX8550_STB810) += arch/mips/pnx8550/stb810/ load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic diff --git a/arch/mips/nxp/pnx8550/common/Makefile b/arch/mips/pnx8550/common/Makefile index dd9e7b1f7fd3..dd9e7b1f7fd3 100644 --- a/arch/mips/nxp/pnx8550/common/Makefile +++ b/arch/mips/pnx8550/common/Makefile diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c index cfed5051dc6d..cfed5051dc6d 100644 --- a/arch/mips/nxp/pnx8550/common/int.c +++ b/arch/mips/pnx8550/common/int.c diff --git a/arch/mips/pnx8550/common/pci.c b/arch/mips/pnx8550/common/pci.c new file mode 100644 index 000000000000..98e86ddb86cc --- /dev/null +++ b/arch/mips/pnx8550/common/pci.c @@ -0,0 +1,134 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * + * Author: source@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/init.h> + +#include <pci.h> +#include <glb.h> +#include <nand.h> + +static struct resource pci_io_resource = { + .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */ + .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE, + .name = "pci IO space", + .flags = IORESOURCE_IO +}; + +static struct resource pci_mem_resource = { + .start = PNX8550_PCIMEM, + .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1, + .name = "pci memory space", + .flags = IORESOURCE_MEM +}; + +extern struct pci_ops pnx8550_pci_ops; + +static struct pci_controller pnx8550_controller = { + .pci_ops = &pnx8550_pci_ops, + .io_map_base = PNX8550_PORT_BASE, + .io_resource = &pci_io_resource, + .mem_resource = &pci_mem_resource, +}; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +static inline unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +static int __init pnx8550_pci_setup(void) +{ + int pci_mem_code; + int mem_size = get_system_mem_size() >> 20; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* Calc the PCI mem size code */ + if (mem_size >= 128) + pci_mem_code = SIZE_128M; + else if (mem_size >= 64) + pci_mem_code = SIZE_64M; + else if (mem_size >= 32) + pci_mem_code = SIZE_32M; + else + pci_mem_code = SIZE_16M; + + /* Set PCI_XIO registers */ + outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO); + outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI); + outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO); + outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI); + + /* Send memory transaction via PCI_BASE2 */ + outl(0x00000001, PCI_BASE | PCI_IO); + + /* Unlock the setup register */ + outl(0xca, PCI_BASE | PCI_UNLOCKREG); + + /* + * BAR0 of PNX8550 (pci base 10) must be zero in order for ide + * to work, and in order for bus_to_baddr to work without any + * hacks. + */ + outl(0x00000000, PCI_BASE | PCI_BASE10); + + /* + *These two bars are set by default or the boot code. + * However, it's safer to set them here so we're not boot + * code dependent. + */ + outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */ + outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */ + + outl(PCI_EN_TA | + PCI_EN_PCI2MMI | + PCI_EN_XIO | + PCI_SETUP_BASE18_SIZE(SIZE_32M) | + PCI_SETUP_BASE18_EN | + PCI_SETUP_BASE14_EN | + PCI_SETUP_BASE10_PREF | + PCI_SETUP_BASE10_SIZE(pci_mem_code) | + PCI_SETUP_CFGMANAGE_EN | + PCI_SETUP_PCIARB_EN, + PCI_BASE | + PCI_SETUP); /* PCI_SETUP */ + outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */ + + register_pci_controller(&pnx8550_controller); + + return 0; +} + +arch_initcall(pnx8550_pci_setup); diff --git a/arch/mips/nxp/pnx8550/common/platform.c b/arch/mips/pnx8550/common/platform.c index 5264cc09a27b..5264cc09a27b 100644 --- a/arch/mips/nxp/pnx8550/common/platform.c +++ b/arch/mips/pnx8550/common/platform.c diff --git a/arch/mips/nxp/pnx8550/common/proc.c b/arch/mips/pnx8550/common/proc.c index 3bba5ec828e8..3bba5ec828e8 100644 --- a/arch/mips/nxp/pnx8550/common/proc.c +++ b/arch/mips/pnx8550/common/proc.c diff --git a/arch/mips/nxp/pnx8550/common/prom.c b/arch/mips/pnx8550/common/prom.c index 32f70097c3c7..32f70097c3c7 100644 --- a/arch/mips/nxp/pnx8550/common/prom.c +++ b/arch/mips/pnx8550/common/prom.c diff --git a/arch/mips/nxp/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c index fadd8744a6bc..fadd8744a6bc 100644 --- a/arch/mips/nxp/pnx8550/common/reset.c +++ b/arch/mips/pnx8550/common/reset.c diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c new file mode 100644 index 000000000000..64246c9c875c --- /dev/null +++ b/arch/mips/pnx8550/common/setup.c @@ -0,0 +1,145 @@ +/* + * + * 2.6 port, Embedded Alley Solutions, Inc + * + * Based on Per Hallsmark, per.hallsmark@mvista.com + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include <linux/init.h> +#include <linux/sched.h> +#include <linux/ioport.h> +#include <linux/irq.h> +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/serial_pnx8xxx.h> +#include <linux/pm.h> + +#include <asm/cpu.h> +#include <asm/bootinfo.h> +#include <asm/irq.h> +#include <asm/mipsregs.h> +#include <asm/reboot.h> +#include <asm/pgtable.h> +#include <asm/time.h> + +#include <glb.h> +#include <int.h> +#include <pci.h> +#include <uart.h> +#include <nand.h> + +extern void __init board_setup(void); +extern void pnx8550_machine_restart(char *); +extern void pnx8550_machine_halt(void); +extern void pnx8550_machine_power_off(void); +extern struct resource ioport_resource; +extern struct resource iomem_resource; +extern char *prom_getcmdline(void); + +struct resource standard_io_resources[] = { + { + .start = 0x00, + .end = 0x1f, + .name = "dma1", + .flags = IORESOURCE_BUSY + }, { + .start = 0x40, + .end = 0x5f, + .name = "timer", + .flags = IORESOURCE_BUSY + }, { + .start = 0x80, + .end = 0x8f, + .name = "dma page reg", + .flags = IORESOURCE_BUSY + }, { + .start = 0xc0, + .end = 0xdf, + .name = "dma2", + .flags = IORESOURCE_BUSY + }, +}; + +#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources) + +extern struct resource pci_io_resource; +extern struct resource pci_mem_resource; + +/* Return the total size of DRAM-memory, (RANK0 + RANK1) */ +unsigned long get_system_mem_size(void) +{ + /* Read IP2031_RANK0_ADDR_LO */ + unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010); + /* Read IP2031_RANK1_ADDR_HI */ + unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018); + + return dram_r1_hi - dram_r0_lo + 1; +} + +int pnx8550_console_port = -1; + +void __init plat_mem_setup(void) +{ + int i; + char* argptr; + + board_setup(); /* board specific setup */ + + _machine_restart = pnx8550_machine_restart; + _machine_halt = pnx8550_machine_halt; + pm_power_off = pnx8550_machine_power_off; + + /* Clear the Global 2 Register, PCI Inta Output Enable Registers + Bit 1:Enable DAC Powerdown + -> 0:DACs are enabled and are working normally + 1:DACs are powerdown + Bit 0:Enable of PCI inta output + -> 0 = Disable PCI inta output + 1 = Enable PCI inta output + */ + PNX8550_GLB2_ENAB_INTA_O = 0; + + /* IO/MEM resources. */ + set_io_port_base(PNX8550_PORT_BASE); + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + /* Request I/O space for devices on this board */ + for (i = 0; i < STANDARD_IO_RESOURCES; i++) + request_resource(&ioport_resource, standard_io_resources + i); + + /* Place the Mode Control bit for GPIO pin 16 in primary function */ + /* Pin 16 is used by UART1, UA1_TX */ + outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) | + (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT), + PNX8550_GPIO_MC1); + + argptr = prom_getcmdline(); + if ((argptr = strstr(argptr, "console=ttyS")) != NULL) { + argptr += strlen("console=ttyS"); + pnx8550_console_port = *argptr == '0' ? 0 : 1; + + /* We must initialize the UART (console) before early printk */ + /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ + ip3106_lcr(UART_BASE, pnx8550_console_port) = + PNX8XXX_UART_LCR_8BIT; + ip3106_baud(UART_BASE, pnx8550_console_port) = 5; + } + + return; +} diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c index 8836c6203df0..8836c6203df0 100644 --- a/arch/mips/nxp/pnx8550/common/time.c +++ b/arch/mips/pnx8550/common/time.c diff --git a/arch/mips/nxp/pnx8550/jbs/Makefile b/arch/mips/pnx8550/jbs/Makefile index ad6a8ca7d8ce..ad6a8ca7d8ce 100644 --- a/arch/mips/nxp/pnx8550/jbs/Makefile +++ b/arch/mips/pnx8550/jbs/Makefile diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/pnx8550/jbs/board_setup.c index 57dd903ca408..57dd903ca408 100644 --- a/arch/mips/nxp/pnx8550/jbs/board_setup.c +++ b/arch/mips/pnx8550/jbs/board_setup.c diff --git a/arch/mips/nxp/pnx8550/jbs/init.c b/arch/mips/pnx8550/jbs/init.c index d59b4a4e5e8b..d59b4a4e5e8b 100644 --- a/arch/mips/nxp/pnx8550/jbs/init.c +++ b/arch/mips/pnx8550/jbs/init.c diff --git a/arch/mips/nxp/pnx8550/jbs/irqmap.c b/arch/mips/pnx8550/jbs/irqmap.c index 7fc89842002c..7fc89842002c 100644 --- a/arch/mips/nxp/pnx8550/jbs/irqmap.c +++ b/arch/mips/pnx8550/jbs/irqmap.c diff --git a/arch/mips/nxp/pnx8550/stb810/Makefile b/arch/mips/pnx8550/stb810/Makefile index ab91d72c5664..ab91d72c5664 100644 --- a/arch/mips/nxp/pnx8550/stb810/Makefile +++ b/arch/mips/pnx8550/stb810/Makefile diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/pnx8550/stb810/board_setup.c index af2a55e0b4e9..af2a55e0b4e9 100644 --- a/arch/mips/nxp/pnx8550/stb810/board_setup.c +++ b/arch/mips/pnx8550/stb810/board_setup.c diff --git a/arch/mips/nxp/pnx8550/stb810/irqmap.c b/arch/mips/pnx8550/stb810/irqmap.c index 8c034963ddcd..8c034963ddcd 100644 --- a/arch/mips/nxp/pnx8550/stb810/irqmap.c +++ b/arch/mips/pnx8550/stb810/irqmap.c diff --git a/arch/mips/nxp/pnx8550/stb810/prom_init.c b/arch/mips/pnx8550/stb810/prom_init.c index ca7f4ada0640..ca7f4ada0640 100644 --- a/arch/mips/nxp/pnx8550/stb810/prom_init.c +++ b/arch/mips/pnx8550/stb810/prom_init.c |