diff options
Diffstat (limited to 'arch/arm')
70 files changed, 64 insertions, 140 deletions
diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c index 510e5b13aa2e..1bc34c7567fd 100644 --- a/arch/arm/common/mcpm_platsmp.c +++ b/arch/arm/common/mcpm_platsmp.c @@ -19,7 +19,7 @@ #include <asm/smp.h> #include <asm/smp_plat.h> -static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned int mpidr, pcpu, pcluster, ret; extern void secondary_startup(void); @@ -40,7 +40,7 @@ static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *i return 0; } -static void __cpuinit mcpm_secondary_init(unsigned int cpu) +static void mcpm_secondary_init(unsigned int cpu) { mcpm_cpu_powered_up(); } diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index accefe099182..e406d575c94f 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -89,7 +89,7 @@ static inline u64 arch_counter_get_cntvct(void) return cval; } -static inline void __cpuinit arch_counter_set_user_access(void) +static inline void arch_counter_set_user_access(void) { u32 cntkctl; diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index 76ab5ca50610..47cd974e57ea 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -149,7 +149,6 @@ ENDPROC(lookup_processor_type) * r5 = proc_info pointer in physical address space * r9 = cpuid (preserved) */ - __CPUINIT __lookup_processor_type: adr r3, __lookup_processor_type_data ldmia r3, {r4 - r6} diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 75f14cc3e073..b361de143756 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -87,7 +87,6 @@ ENTRY(stext) ENDPROC(stext) #ifdef CONFIG_SMP - __CPUINIT ENTRY(secondary_startup) /* * Common entry point for secondary CPUs. diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 45e8935cae4e..9cf6063020ae 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -343,7 +343,6 @@ __turn_mmu_on_loc: .long __turn_mmu_on_end #if defined(CONFIG_SMP) - __CPUINIT ENTRY(secondary_startup) /* * Common entry point for secondary CPUs. diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 1fd749ee4a1b..7b95de601357 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -1020,7 +1020,7 @@ out_mdbgen: cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); } -static int __cpuinit dbg_reset_notify(struct notifier_block *self, +static int dbg_reset_notify(struct notifier_block *self, unsigned long action, void *cpu) { if ((action & ~CPU_TASKS_FROZEN) == CPU_ONLINE) @@ -1029,7 +1029,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self, return NOTIFY_OK; } -static struct notifier_block __cpuinitdata dbg_reset_nb = { +static struct notifier_block dbg_reset_nb = { .notifier_call = dbg_reset_notify, }; diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 1f2740e3dbc0..aebe0e99c153 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -157,8 +157,8 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu) * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading * junk values out of them. */ -static int __cpuinit cpu_pmu_notify(struct notifier_block *b, - unsigned long action, void *hcpu) +static int cpu_pmu_notify(struct notifier_block *b, unsigned long action, + void *hcpu) { if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) return NOTIFY_DONE; @@ -171,7 +171,7 @@ static int __cpuinit cpu_pmu_notify(struct notifier_block *b, return NOTIFY_OK; } -static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = { +static struct notifier_block cpu_pmu_hotplug_notifier = { .notifier_call = cpu_pmu_notify, }; diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c index 219f1d73572a..70ded3fb42d9 100644 --- a/arch/arm/kernel/psci_smp.c +++ b/arch/arm/kernel/psci_smp.c @@ -46,8 +46,7 @@ extern void secondary_startup(void); -static int __cpuinit psci_boot_secondary(unsigned int cpu, - struct task_struct *idle) +static int psci_boot_secondary(unsigned int cpu, struct task_struct *idle) { if (psci_ops.cpu_on) return psci_ops.cpu_on(cpu_logical_map(cpu), diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index c5fb5469054b..c2b4f8f0be9a 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -58,7 +58,7 @@ struct secondary_data secondary_data; * control for which core is the next to come out of the secondary * boot "holding pen" */ -volatile int __cpuinitdata pen_release = -1; +volatile int pen_release = -1; enum ipi_msg_type { IPI_WAKEUP, @@ -86,7 +86,7 @@ static unsigned long get_arch_pgd(pgd_t *pgd) return pgdir >> ARCH_PGD_SHIFT; } -int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) +int __cpu_up(unsigned int cpu, struct task_struct *idle) { int ret; @@ -138,7 +138,7 @@ void __init smp_init_cpus(void) smp_ops.smp_init_cpus(); } -int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) +int boot_secondary(unsigned int cpu, struct task_struct *idle) { if (smp_ops.smp_boot_secondary) return smp_ops.smp_boot_secondary(cpu, idle); @@ -170,7 +170,7 @@ static int platform_cpu_disable(unsigned int cpu) /* * __cpu_disable runs on the processor to be shutdown. */ -int __cpuinit __cpu_disable(void) +int __cpu_disable(void) { unsigned int cpu = smp_processor_id(); int ret; @@ -216,7 +216,7 @@ static DECLARE_COMPLETION(cpu_died); * called on the thread which is asking for a CPU to be shutdown - * waits until shutdown has completed, or it is timed out. */ -void __cpuinit __cpu_die(unsigned int cpu) +void __cpu_die(unsigned int cpu) { if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) { pr_err("CPU%u: cpu didn't die\n", cpu); @@ -306,7 +306,7 @@ void __ref cpu_die(void) * Called by both boot and secondaries to move global data into * per-processor storage. */ -static void __cpuinit smp_store_cpu_info(unsigned int cpuid) +static void smp_store_cpu_info(unsigned int cpuid) { struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); @@ -322,7 +322,7 @@ static void percpu_timer_setup(void); * This is the secondary CPU boot entry. We're using this CPUs * idle thread stack, but a set of temporary page tables. */ -asmlinkage void __cpuinit secondary_start_kernel(void) +asmlinkage void secondary_start_kernel(void) { struct mm_struct *mm = &init_mm; unsigned int cpu; @@ -521,7 +521,7 @@ static void broadcast_timer_set_mode(enum clock_event_mode mode, { } -static void __cpuinit broadcast_timer_setup(struct clock_event_device *evt) +static void broadcast_timer_setup(struct clock_event_device *evt) { evt->name = "dummy_timer"; evt->features = CLOCK_EVT_FEAT_ONESHOT | @@ -550,7 +550,7 @@ int local_timer_register(struct local_timer_ops *ops) } #endif -static void __cpuinit percpu_timer_setup(void) +static void percpu_timer_setup(void) { unsigned int cpu = smp_processor_id(); struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index f6fd1d4398c6..25956204ef23 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -187,7 +187,7 @@ core_initcall(twd_cpufreq_init); #endif -static void __cpuinit twd_calibrate_rate(void) +static void twd_calibrate_rate(void) { unsigned long count; u64 waitjiffies; @@ -265,7 +265,7 @@ static void twd_get_clock(struct device_node *np) /* * Setup the local clock events for a CPU. */ -static int __cpuinit twd_timer_setup(struct clock_event_device *clk) +static int twd_timer_setup(struct clock_event_device *clk) { struct clock_event_device **this_cpu_clk; int cpu = smp_processor_id(); @@ -308,7 +308,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk) return 0; } -static struct local_timer_ops twd_lt_ops __cpuinitdata = { +static struct local_timer_ops twd_lt_ops = { .setup = twd_timer_setup, .stop = twd_timer_stop, }; diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c index 64dbfa57204a..5306de350133 100644 --- a/arch/arm/lib/delay.c +++ b/arch/arm/lib/delay.c @@ -86,7 +86,7 @@ void __init register_current_timer_delay(const struct delay_timer *timer) } } -unsigned long __cpuinit calibrate_delay_is_known(void) +unsigned long calibrate_delay_is_known(void) { delay_calibrated = true; return lpj_fine; diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index 5364d4bfa8bc..cdd9d91e9933 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S @@ -13,8 +13,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __CPUINIT - /* * exynos4 specific entry point for secondary CPUs. This provides * a "holding pen" into which all secondary cores are held until we're diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index deba1308ff16..58b43e6f9262 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -75,7 +75,7 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(boot_lock); -static void __cpuinit exynos_secondary_init(unsigned int cpu) +static void exynos_secondary_init(unsigned int cpu) { /* * let the primary processor know we're out of the @@ -90,7 +90,7 @@ static void __cpuinit exynos_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; unsigned long phys_cpu = cpu_logical_map(cpu); diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c index a984573e0d02..32d75cf55cbc 100644 --- a/arch/arm/mach-highbank/platsmp.c +++ b/arch/arm/mach-highbank/platsmp.c @@ -24,7 +24,7 @@ extern void secondary_startup(void); -static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int highbank_boot_secondary(unsigned int cpu, struct task_struct *idle) { highbank_set_cpu_jump(cpu, secondary_startup); arch_send_wakeup_ipi_mask(cpumask_of(cpu)); diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index c6e1ab544882..1f24c1fdfea4 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -53,7 +53,7 @@ void imx_scu_standby_enable(void) writel_relaxed(val, scu_base); } -static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle) { imx_set_cpu_jump(cpu, v7_secondary_startup); imx_enable_cpu(cpu, true); diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c index 1d4181e1daf2..14378e3fef16 100644 --- a/arch/arm/mach-keystone/platsmp.c +++ b/arch/arm/mach-keystone/platsmp.c @@ -21,7 +21,7 @@ #include "keystone.h" -static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu, +static int keystone_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long start = virt_to_phys(&secondary_startup); diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S index bcd5af223dea..6c62c3f82fe6 100644 --- a/arch/arm/mach-msm/headsmp.S +++ b/arch/arm/mach-msm/headsmp.S @@ -11,8 +11,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __CPUINIT - /* * MSM specific entry point for secondary CPUs. This provides * a "holding pen" into which all secondary cores are held until we're diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 00cdb0a5dac8..3f06edcdd0ce 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -38,7 +38,7 @@ static inline int get_core_count(void) return ((read_cpuid_id() >> 4) & 3) + 1; } -static void __cpuinit msm_secondary_init(unsigned int cpu) +static void msm_secondary_init(unsigned int cpu) { /* * let the primary processor know we're out of the @@ -54,7 +54,7 @@ static void __cpuinit msm_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static __cpuinit void prepare_cold_cpu(unsigned int cpu) +static void prepare_cold_cpu(unsigned int cpu) { int ret; ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), @@ -73,7 +73,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu) "address\n"); } -static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; static int cold_boot_done; diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index b6418fd5fe0d..8697cfc0d0b6 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -139,7 +139,7 @@ static struct clocksource msm_clocksource = { }; #ifdef CONFIG_LOCAL_TIMERS -static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt) +static int msm_local_timer_setup(struct clock_event_device *evt) { /* Use existing clock_event for cpu 0 */ if (!smp_processor_id()) @@ -164,7 +164,7 @@ static void msm_local_timer_stop(struct clock_event_device *evt) disable_percpu_irq(evt->irq); } -static struct local_timer_ops msm_local_timer_ops __cpuinitdata = { +static struct local_timer_ops msm_local_timer_ops = { .setup = msm_local_timer_setup, .stop = msm_local_timer_stop, }; diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index be117591f7f2..4c24303ec481 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -28,7 +28,7 @@ #include <asm/cacheflush.h> #include "armada-370-xp.h" -unsigned long __cpuinitdata coherency_phys_base; +unsigned long coherency_phys_base; static void __iomem *coherency_base; static void __iomem *coherency_cpu_base; diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S index 7147300c8af2..8a1b0c96e9ec 100644 --- a/arch/arm/mach-mvebu/headsmp.S +++ b/arch/arm/mach-mvebu/headsmp.S @@ -21,8 +21,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __CPUINIT - /* * Armada XP specific entry point for secondary CPUs. * We add the CPU to the coherency fabric and then jump to secondary diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index 93f2f3ab45f1..ce81d3031405 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -71,13 +71,12 @@ void __init set_secondary_cpus_clock(void) } } -static void __cpuinit armada_xp_secondary_init(unsigned int cpu) +static void armada_xp_secondary_init(unsigned int cpu) { armada_xp_mpic_smp_cpu_init(); } -static int __cpuinit armada_xp_boot_secondary(unsigned int cpu, - struct task_struct *idle) +static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle) { pr_info("Booting CPU %d\n", cpu); diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 4ea308114165..75e92952c18e 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -20,8 +20,6 @@ #include "omap44xx.h" - __CPUINIT - /* Physical address needed since MMU not enabled yet on secondary core */ #define AUX_CORE_BOOT0_PA 0x48281800 diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c index f993a4188701..f991016e2a6a 100644 --- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c +++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c @@ -291,7 +291,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) * @cpu : CPU ID * @power_state: CPU low power state. */ -int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) +int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) { struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); unsigned int cpu_state = 0; diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 98a11463a843..8708b2a9da45 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -51,7 +51,7 @@ void __iomem *omap4_get_scu_base(void) return scu_base; } -static void __cpuinit omap4_secondary_init(unsigned int cpu) +static void omap4_secondary_init(unsigned int cpu) { /* * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. @@ -72,7 +72,7 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) { static struct clockdomain *cpu1_clkdm; static bool booted; diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index f8bb3b9b6a76..813c61558a5f 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -323,8 +323,8 @@ static void irq_save_secure_context(void) #endif #ifdef CONFIG_HOTPLUG_CPU -static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self, - unsigned long action, void *hcpu) +static int irq_cpu_hotplug_notify(struct notifier_block *self, + unsigned long action, void *hcpu) { unsigned int cpu = (unsigned int)hcpu; diff --git a/arch/arm/mach-prima2/headsmp.S b/arch/arm/mach-prima2/headsmp.S index 5b8a408d8921..d86fe33c5f53 100644 --- a/arch/arm/mach-prima2/headsmp.S +++ b/arch/arm/mach-prima2/headsmp.S @@ -9,8 +9,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __CPUINIT - /* * SIRFSOC specific entry point for secondary CPUs. This provides * a "holding pen" into which all secondary cores are held until we're diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 1c3de7bed841..3dbcb1ab6e37 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c @@ -44,7 +44,7 @@ void __init sirfsoc_map_scu(void) scu_base = (void __iomem *)SIRFSOC_VA(base); } -static void __cpuinit sirfsoc_secondary_init(unsigned int cpu) +static void sirfsoc_secondary_init(unsigned int cpu) { /* * let the primary processor know we're out of the @@ -65,7 +65,7 @@ static struct of_device_id rsc_ids[] = { {}, }; -static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; struct device_node *np; diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S index 6f9865467258..bfd920083a3b 100644 --- a/arch/arm/mach-shmobile/headsmp-scu.S +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -23,7 +23,6 @@ #include <linux/init.h> #include <asm/memory.h> - __CPUINIT /* * Boot code for secondary CPUs. * diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 559d1ce5f57e..a9d212498987 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -14,8 +14,6 @@ #include <linux/init.h> #include <asm/memory.h> - __CPUINIT - ENTRY(shmobile_invalidate_start) bl v7_invalidate_l1 b secondary_startup diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 80991b35f4ac..22a05a869d25 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c @@ -30,7 +30,7 @@ #define EMEV2_SCU_BASE 0x1e000000 -static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) { arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); return 0; diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 526cfaae81c1..9bdf810f2a87 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -81,7 +81,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu) return ret ? ret : 1; } -static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { struct r8a7779_pm_ch *ch = NULL; int ret = -EIO; diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index d613113a04bd..d5fc3ed4e315 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -48,7 +48,7 @@ void __init sh73a0_register_twd(void) } #endif -static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { cpu = cpu_logical_map(cpu); diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S index 9004bfb1756e..95c115d8b5ee 100644 --- a/arch/arm/mach-socfpga/headsmp.S +++ b/arch/arm/mach-socfpga/headsmp.S @@ -10,7 +10,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __CPUINIT .arch armv7-a ENTRY(secondary_trampoline) diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c index b51ce8c7929d..5356a72bc8ce 100644 --- a/arch/arm/mach-socfpga/platsmp.c +++ b/arch/arm/mach-socfpga/platsmp.c @@ -29,7 +29,7 @@ #include "core.h" -static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) { int trampoline_size = &secondary_trampoline_end - &secondary_trampoline; diff --git a/arch/arm/mach-spear/generic.h b/arch/arm/mach-spear/generic.h index 904f2c907b46..a99d90a4d09c 100644 --- a/arch/arm/mach-spear/generic.h +++ b/arch/arm/mach-spear/generic.h @@ -37,7 +37,7 @@ void __init spear13xx_l2x0_init(void); void spear_restart(enum reboot_mode, const char *); void spear13xx_secondary_startup(void); -void __cpuinit spear13xx_cpu_die(unsigned int cpu); +void spear13xx_cpu_die(unsigned int cpu); extern struct smp_operations spear13xx_smp_ops; diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c index 9c4c722c954e..5c4a19887b2b 100644 --- a/arch/arm/mach-spear/platsmp.c +++ b/arch/arm/mach-spear/platsmp.c @@ -24,7 +24,7 @@ static DEFINE_SPINLOCK(boot_lock); static void __iomem *scu_base = IOMEM(VA_SCU_BASE); -static void __cpuinit spear13xx_secondary_init(unsigned int cpu) +static void spear13xx_secondary_init(unsigned int cpu) { /* * let the primary processor know we're out of the @@ -40,7 +40,7 @@ static void __cpuinit spear13xx_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c index 977a863468fc..dce50d983a8e 100644 --- a/arch/arm/mach-sti/platsmp.c +++ b/arch/arm/mach-sti/platsmp.c @@ -27,7 +27,7 @@ #include "smp.h" -static void __cpuinit write_pen_release(int val) +static void write_pen_release(int val) { pen_release = val; smp_wmb(); @@ -37,7 +37,7 @@ static void __cpuinit write_pen_release(int val) static DEFINE_SPINLOCK(boot_lock); -void __cpuinit sti_secondary_init(unsigned int cpu) +void sti_secondary_init(unsigned int cpu) { trace_hardirqs_off(); @@ -54,7 +54,7 @@ void __cpuinit sti_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle) +int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 24db4ac428ae..97b33a2a2d75 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -35,7 +35,7 @@ static cpumask_t tegra_cpu_init_mask; -static void __cpuinit tegra_secondary_init(unsigned int cpu) +static void tegra_secondary_init(unsigned int cpu) { cpumask_set_cpu(cpu, &tegra_cpu_init_mask); } @@ -167,7 +167,7 @@ static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) return ret; } -static int __cpuinit tegra_boot_secondary(unsigned int cpu, +static int tegra_boot_secondary(unsigned int cpu, struct task_struct *idle) { if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 94e69bee3da5..261fec140c06 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -191,7 +191,7 @@ static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { [TEGRA_SUSPEND_LP0] = "LP0", }; -static int __cpuinit tegra_suspend_enter(suspend_state_t state) +static int tegra_suspend_enter(suspend_state_t state) { enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 14d90469392f..1f296e796a4f 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -54,7 +54,7 @@ static void __iomem *scu_base_addr(void) static DEFINE_SPINLOCK(boot_lock); -static void __cpuinit ux500_secondary_init(unsigned int cpu) +static void ux500_secondary_init(unsigned int cpu) { /* * let the primary processor know we're out of the @@ -69,7 +69,7 @@ static void __cpuinit ux500_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) +static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index fbbd0e21c404..3040d219570f 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -27,7 +27,7 @@ extern void secondary_startup(void); extern char zynq_secondary_trampoline; extern char zynq_secondary_trampoline_jump; extern char zynq_secondary_trampoline_end; -extern int __cpuinit zynq_cpun_start(u32 address, int cpu); +extern int zynq_cpun_start(u32 address, int cpu); extern struct smp_operations zynq_smp_ops __initdata; #endif diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S index d183cd234a9b..d4cd5f34fe5c 100644 --- a/arch/arm/mach-zynq/headsmp.S +++ b/arch/arm/mach-zynq/headsmp.S @@ -9,8 +9,6 @@ #include <linux/linkage.h> #include <linux/init.h> - __CPUINIT - ENTRY(zynq_secondary_trampoline) ldr r0, [pc] bx r0 diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index 023f225493f2..689fbbc3d9c8 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -30,11 +30,11 @@ /* * Store number of cores in the system * Because of scu_get_core_count() must be in __init section and can't - * be called from zynq_cpun_start() because it is in __cpuinit section. + * be called from zynq_cpun_start() because it is not in __init section. */ static int ncores; -int __cpuinit zynq_cpun_start(u32 address, int cpu) +int zynq_cpun_start(u32 address, int cpu) { u32 trampoline_code_size = &zynq_secondary_trampoline_end - &zynq_secondary_trampoline; @@ -92,7 +92,7 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu) } EXPORT_SYMBOL(zynq_cpun_start); -static int __cpuinit zynq_boot_secondary(unsigned int cpu, +static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 2bb61e703d6c..d1a2d05971e0 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -443,8 +443,6 @@ ENTRY(cpu_arm1020_set_pte_ext) #endif /* CONFIG_MMU */ mov pc, lr - __CPUINIT - .type __arm1020_setup, #function __arm1020_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 8f96aa40f510..9d89405c3d03 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -425,8 +425,6 @@ ENTRY(cpu_arm1020e_set_pte_ext) #endif /* CONFIG_MMU */ mov pc, lr - __CPUINIT - .type __arm1020e_setup, #function __arm1020e_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index 8ebe4a469a22..6f01a0ae3b30 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -407,8 +407,6 @@ ENTRY(cpu_arm1022_set_pte_ext) #endif /* CONFIG_MMU */ mov pc, lr - __CPUINIT - .type __arm1022_setup, #function __arm1022_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 093fc7e520c3..4799a24b43e6 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -396,9 +396,6 @@ ENTRY(cpu_arm1026_set_pte_ext) #endif /* CONFIG_MMU */ mov pc, lr - - __CPUINIT - .type __arm1026_setup, #function __arm1026_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 0ac908c7ade1..d42c37f9f5bc 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -116,8 +116,6 @@ ENTRY(cpu_arm720_reset) ENDPROC(cpu_arm720_reset) .popsection - __CPUINIT - .type __arm710_setup, #function __arm710_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index fde2d2a794cf..9b0ae90cbf17 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -60,8 +60,6 @@ ENTRY(cpu_arm740_reset) ENDPROC(cpu_arm740_reset) .popsection - __CPUINIT - .type __arm740_setup, #function __arm740_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index 6ddea3e464bd..f6cc3f63ce39 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -51,8 +51,6 @@ ENTRY(cpu_arm7tdmi_reset) ENDPROC(cpu_arm7tdmi_reset) .popsection - __CPUINIT - .type __arm7tdmi_setup, #function __arm7tdmi_setup: mov pc, lr diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 2556cf1c2da1..549557df6d57 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -410,8 +410,6 @@ ENTRY(cpu_arm920_do_resume) ENDPROC(cpu_arm920_do_resume) #endif - __CPUINIT - .type __arm920_setup, #function __arm920_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index 4464c49d7449..2a758b06c6f6 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -388,8 +388,6 @@ ENTRY(cpu_arm922_set_pte_ext) #endif /* CONFIG_MMU */ mov pc, lr - __CPUINIT - .type __arm922_setup, #function __arm922_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 281eb9b9c1d6..97448c3acf38 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -438,8 +438,6 @@ ENTRY(cpu_arm925_set_pte_ext) #endif /* CONFIG_MMU */ mov pc, lr - __CPUINIT - .type __arm925_setup, #function __arm925_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 344c8a548cc0..0f098f407c9f 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -425,8 +425,6 @@ ENTRY(cpu_arm926_do_resume) ENDPROC(cpu_arm926_do_resume) #endif - __CPUINIT - .type __arm926_setup, #function __arm926_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index 8da189d4a402..1c39a704ff6e 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -273,8 +273,6 @@ ENDPROC(arm940_dma_unmap_area) @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) define_cache_functions arm940 - __CPUINIT - .type __arm940_setup, #function __arm940_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index f666cf34075a..0289cd905e73 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -326,8 +326,6 @@ ENTRY(cpu_arm946_dcache_clean_area) mcr p15, 0, r0, c7, c10, 4 @ drain WB mov pc, lr - __CPUINIT - .type __arm946_setup, #function __arm946_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 8881391dfb9e..f51197ba754a 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -51,8 +51,6 @@ ENTRY(cpu_arm9tdmi_reset) ENDPROC(cpu_arm9tdmi_reset) .popsection - __CPUINIT - .type __arm9tdmi_setup, #function __arm9tdmi_setup: mov pc, lr diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index aaeb6c127c7a..2dfc0f1d3bfd 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S @@ -135,8 +135,6 @@ ENTRY(cpu_fa526_set_pte_ext) #endif mov pc, lr - __CPUINIT - .type __fa526_setup, #function __fa526_setup: /* On return of this routine, r0 must carry correct flags for CFG register */ diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 4106b09e0c29..d5146b98c8d1 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -514,8 +514,6 @@ ENTRY(cpu_feroceon_set_pte_ext) #endif mov pc, lr - __CPUINIT - .type __feroceon_setup, #function __feroceon_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index 0b60dd3d742a..40acba595731 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -383,8 +383,6 @@ ENTRY(cpu_mohawk_do_resume) ENDPROC(cpu_mohawk_do_resume) #endif - __CPUINIT - .type __mohawk_setup, #function __mohawk_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index 775d70fba937..c45319c8f1d9 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -159,8 +159,6 @@ ENTRY(cpu_sa110_set_pte_ext) #endif mov pc, lr - __CPUINIT - .type __sa110_setup, #function __sa110_setup: mov r10, #0 diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index d92dfd081429..09d241ae2dbe 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -198,8 +198,6 @@ ENTRY(cpu_sa1100_do_resume) ENDPROC(cpu_sa1100_do_resume) #endif - __CPUINIT - .type __sa1100_setup, #function __sa1100_setup: mov r0, #0 diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 2d1ef87328a1..1128064fddcb 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -180,8 +180,6 @@ ENDPROC(cpu_v6_do_resume) .align - __CPUINIT - /* * __v6_setup * diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 9704097c450e..f64afb9f1bd5 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -160,8 +160,6 @@ ENDPROC(cpu_v7_set_pte_ext) mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1 .endm - __CPUINIT - /* AT * TFR EV X F I D LR S * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM @@ -172,5 +170,3 @@ ENDPROC(cpu_v7_set_pte_ext) .type v7_crval, #object v7_crval: crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c - - .previous diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 5ffe1956c6d9..c36ac69488c8 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -140,8 +140,6 @@ ENDPROC(cpu_v7_set_pte_ext) mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 .endm - __CPUINIT - /* * AT * TFR EV X F IHD LR S @@ -153,5 +151,3 @@ ENDPROC(cpu_v7_set_pte_ext) .type v7_crval, #object v7_crval: crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c - - .previous diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 7ef3ad05df39..5c6d5a3050ea 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -167,8 +167,6 @@ ENDPROC(cpu_pj4b_do_idle) #endif - __CPUINIT - /* * __v7_setup * diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index e8efd83b6f25..dc1645890042 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -446,8 +446,6 @@ ENTRY(cpu_xsc3_do_resume) ENDPROC(cpu_xsc3_do_resume) #endif - __CPUINIT - .type __xsc3_setup, #function __xsc3_setup: mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index e766f889bfd6..d19b1cfcad91 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -558,8 +558,6 @@ ENTRY(cpu_xscale_do_resume) ENDPROC(cpu_xscale_do_resume) #endif - __CPUINIT - .type __xscale_setup, #function __xscale_setup: mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index 1e1b2d769748..39895d892c3b 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c @@ -23,7 +23,7 @@ * observers, irrespective of whether they're taking part in coherency * or not. This is necessary for the hotplug code to work reliably. */ -static void __cpuinit write_pen_release(int val) +static void write_pen_release(int val) { pen_release = val; smp_wmb(); @@ -33,7 +33,7 @@ static void __cpuinit write_pen_release(int val) static DEFINE_SPINLOCK(boot_lock); -void __cpuinit versatile_secondary_init(unsigned int cpu) +void versatile_secondary_init(unsigned int cpu) { /* * let the primary processor know we're out of the @@ -48,7 +48,7 @@ void __cpuinit versatile_secondary_init(unsigned int cpu) spin_unlock(&boot_lock); } -int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle) +int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned long timeout; |