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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi1
-rw-r--r--arch/arm/boot/dts/sunplus-sp7021-achip.dtsi84
-rw-r--r--arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts30
-rw-r--r--arch/arm/boot/dts/sunplus-sp7021.dtsi310
-rw-r--r--arch/arm/configs/multi_v7_defconfig1
-rw-r--r--arch/arm/configs/sp7021_defconfig59
-rw-r--r--arch/arm/mach-sunplus/Kconfig27
-rw-r--r--arch/arm/mach-sunplus/Makefile8
-rw-r--r--arch/arm/mach-sunplus/sp7021.c16
12 files changed, 541 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7630ba9cb6cc..cb37b17226e5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -588,6 +588,8 @@ source "arch/arm/mach-sti/Kconfig"
source "arch/arm/mach-stm32/Kconfig"
+source "arch/arm/mach-sunplus/Kconfig"
+
source "arch/arm/mach-sunxi/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c8e3633f5434..56f655deebb1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -215,6 +215,7 @@ machine-$(CONFIG_ARCH_RENESAS) += shmobile
machine-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_STI) += sti
machine-$(CONFIG_ARCH_STM32) += stm32
+machine-$(CONFIG_ARCH_SUNPLUS) += sunplus
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += ux500
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b327059c83da..05d8aef6e5d2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -79,6 +79,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-vinco.dtb
dtb-$(CONFIG_SOC_SAMA7G5) += \
at91-sama7g5ek.dtb
+dtb-$(CONFIG_SOC_SP7021) += \
+ sunplus-sp7021-demo-v3.dtb
dtb-$(CONFIG_ARCH_AXXIA) += \
axm5516-amarillo.dtb
dtb-$(CONFIG_ARCH_BCM2835) += \
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
index 9633b50a9c6d..c7b5ef15b716 100644
--- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
+++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
@@ -110,6 +110,7 @@
compatible = "nuvoton,npcm750-reset";
reg = <0xf0801000 0x70>;
#reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
};
clk: clock-controller@f0801000 {
diff --git a/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi b/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi
new file mode 100644
index 000000000000..493d32357e4e
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus-sp7021-achip.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Sunplus SP7021
+ *
+ * Copyright (C) 2021 Sunplus Technology Co.
+ */
+
+#include "sunplus-sp7021.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
+ model = "Sunplus SP7021 (CA7)";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <931000000>;
+ };
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ clock-frequency = <931000000>;
+ };
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ clock-frequency = <931000000>;
+ };
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ clock-frequency = <931000000>;
+ };
+ };
+
+ gic: interrupt-controller@9f101000 {
+ compatible = "arm,cortex-a7-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x9f101000 0x1000>,
+ <0x9f102000 0x2000>,
+ <0x9f104000 0x2000>,
+ <0x9f106000 0x2000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <XTAL>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ soc@9c000000 {
+ intc: interrupt-controller@780 {
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts b/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts
new file mode 100644
index 000000000000..d5c5ffc20565
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus-sp7021-demo-v3.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Sunplus SP7021 Demo V3 SBC board
+ *
+ * Copyright (C) Sunplus Technology Co.
+ */
+
+/dts-v1/;
+
+#include "sunplus-sp7021-achip.dtsi"
+
+/ {
+ compatible = "sunplus,sp7021-demo-v3", "sunplus,sp7021";
+ model = "Sunplus SP7021/CA7/Demo_V3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus-sp7021.dtsi
new file mode 100644
index 000000000000..7dc4ce3619c7
--- /dev/null
+++ b/arch/arm/boot/dts/sunplus-sp7021.dtsi
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for Sunplus SP7021
+ *
+ * Copyright (C) 2021 Sunplus Technology Co.
+ */
+
+#include <dt-bindings/clock/sunplus,sp7021-clkc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sunplus,sp7021-reset.h>
+#include <dt-bindings/pinctrl/sppctl-sp7021.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define XTAL 27000000
+
+/ {
+ compatible = "sunplus,sp7021";
+ model = "Sunplus SP7021";
+
+ clocks {
+ extclk: osc0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <XTAL>;
+ clock-output-names = "extclk";
+ };
+ };
+
+ soc@9c000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x9c000000 0x400000>;
+ interrupt-parent = <&intc>;
+
+ clkc: clock-controller@4 {
+ compatible = "sunplus,sp7021-clkc";
+ reg = <0x4 0x28>,
+ <0x200 0x44>,
+ <0x268 0x04>;
+ clocks = <&extclk>;
+ #clock-cells = <1>;
+ };
+
+ intc: interrupt-controller@780 {
+ compatible = "sunplus,sp7021-intc";
+ reg = <0x780 0x80>, <0xa80 0x80>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ otp: otp@af00 {
+ compatible = "sunplus,sp7021-ocotp";
+ reg = <0xaf00 0x34>, <0xaf80 0x58>;
+ reg-names = "hb_gpio", "otprx";
+ clocks = <&clkc CLK_OTPRX>;
+ resets = <&rstc RST_OTPRX>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ therm_calib: thermal-calibration@14 {
+ reg = <0x14 0x3>;
+ };
+ disc_vol: disconnect-voltage@18 {
+ reg = <0x18 0x2>;
+ };
+ mac_addr0: mac-address0@34 {
+ reg = <0x34 0x6>;
+ };
+ mac_addr1: mac-address1@3a {
+ reg = <0x3a 0x6>;
+ };
+ };
+
+ pctl: pinctrl@100 {
+ compatible = "sunplus,sp7021-pctl";
+ reg = <0x100 0x100>,
+ <0x300 0x100>,
+ <0x32e4 0x1C>,
+ <0x80 0x20>;
+ reg-names = "moon2", "gpioxt", "first", "moon1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clkc CLK_GPIO>;
+ resets = <&rstc RST_GPIO>;
+
+ emac_pins: pinmux-emac-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
+ SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
+ SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
+ SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
+ SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
+ SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
+ SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
+ SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
+ SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
+ SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
+ SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
+ SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
+ SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
+ SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
+ SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
+ SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
+ SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
+ >;
+ sunplus,zerofunc = <
+ MUXF_L2SW_LED_FLASH0
+ MUXF_L2SW_LED_FLASH1
+ MUXF_L2SW_LED_ON0
+ MUXF_L2SW_LED_ON1
+ MUXF_DAISY_MODE
+ >;
+ };
+
+ emmc_pins: pinmux-emmc-pins {
+ function = "CARD0_EMMC";
+ groups = "CARD0_EMMC";
+ };
+
+ leds_pins: pinmux-leds-pins {
+ sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
+ };
+
+ sdcard_pins: pinmux-sdcard-pins {
+ function = "SD_CARD";
+ groups = "SD_CARD";
+ sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
+ };
+
+ spi0_pins: pinmux-spi0-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
+ SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0)
+ SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0)
+ SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0)
+ SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0)
+ >;
+ };
+
+ uart0_pins: pinmux-uart0-pins {
+ function = "UA0";
+ groups = "UA0";
+ };
+
+ uart1_pins: pinmux-uart1-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
+ SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
+ >;
+ };
+
+ uart2_pins: pinmux-uart2-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0)
+ SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0)
+ SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0)
+ SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0)
+ >;
+ };
+
+ uart4_pins: pinmux-uart4-pins {
+ sunplus,pins = <
+ SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
+ SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
+ SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0)
+ SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0)
+ >;
+ };
+ };
+
+ rstc: reset@54 {
+ compatible = "sunplus,sp7021-reset";
+ reg = <0x54 0x28>;
+ #reset-cells = <1>;
+ };
+
+ rtc: rtc@3a00 {
+ compatible = "sunplus,sp7021-rtc";
+ reg = <0x3a00 0x80>;
+ reg-names = "rtc";
+ clocks = <&clkc CLK_RTC>;
+ resets = <&rstc RST_RTC>;
+ interrupts = <163 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ spi_controller0: spi@2d80 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0x2d80 0x80>, <0x2e00 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
+ <146 IRQ_TYPE_LEVEL_HIGH>,
+ <145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_0>;
+ resets = <&rstc RST_SPI_COMBO_0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>,
+ <&pctl 28 GPIO_ACTIVE_LOW>;
+ };
+
+ spi_controller1: spi@f480 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0xf480 0x80>, <0xf500 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <67 IRQ_TYPE_LEVEL_HIGH>,
+ <69 IRQ_TYPE_LEVEL_HIGH>,
+ <68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_1>;
+ resets = <&rstc RST_SPI_COMBO_1>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ spi_controller2: spi@f600 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0xf600 0x80>, <0xf680 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <70 IRQ_TYPE_LEVEL_HIGH>,
+ <72 IRQ_TYPE_LEVEL_HIGH>,
+ <71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_2>;
+ resets = <&rstc RST_SPI_COMBO_2>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ spi_controller3: spi@f780 {
+ compatible = "sunplus,sp7021-spi";
+ reg = <0xf780 0x80>, <0xf800 0x80>;
+ reg-names = "master", "slave";
+ interrupts = <73 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma_w", "master_risc", "slave_risc";
+ clocks = <&clkc CLK_SPI_COMBO_3>;
+ resets = <&rstc RST_SPI_COMBO_3>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ uart0: serial@900 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x900 0x80>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA0>;
+ resets = <&rstc RST_UA0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ };
+
+ uart1: serial@980 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x980 0x80>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA1>;
+ resets = <&rstc RST_UA1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+ };
+
+ uart2: serial@800 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x800 0x80>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA2>;
+ resets = <&rstc RST_UA2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+ };
+
+ uart3: serial@880 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x880 0x80>;
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA3>;
+ resets = <&rstc RST_UA3>;
+ status = "disabled";
+ };
+
+ uart4: serial@8780 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x8780 0x80>;
+ interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLK_UA4>;
+ resets = <&rstc RST_UA4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins>;
+ status = "disabled";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_pins>;
+ system-led {
+ label = "system-led";
+ gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index cff991cfe864..bcd7a431c66e 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -96,6 +96,7 @@ CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
CONFIG_ARCH_STI=y
CONFIG_ARCH_STM32=y
+CONFIG_ARCH_SUNPLUS=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_UNIPHIER=y
diff --git a/arch/arm/configs/sp7021_defconfig b/arch/arm/configs/sp7021_defconfig
new file mode 100644
index 000000000000..703b9aaa40f0
--- /dev/null
+++ b/arch/arm/configs/sp7021_defconfig
@@ -0,0 +1,59 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_ARCH_SUNPLUS=y
+# CONFIG_VDSO is not set
+CONFIG_SMP=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_UEVENT_HELPER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_EXT4_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FANOTIFY=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
+CONFIG_EXFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/mach-sunplus/Kconfig b/arch/arm/mach-sunplus/Kconfig
new file mode 100644
index 000000000000..926cde5e3cd9
--- /dev/null
+++ b/arch/arm/mach-sunplus/Kconfig
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+menuconfig ARCH_SUNPLUS
+ bool "Sunplus SoCs"
+ depends on ARCH_MULTI_V7
+ help
+ Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
+ such as the Banana Pi BPI-F2S development board (and derivatives).
+ (<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
+ (<https://tibbo.com/store/plus1.html>)
+
+config SOC_SP7021
+ bool "Sunplus SP7021 SoC support"
+ depends on ARCH_SUNPLUS
+ default ARCH_SUNPLUS
+ select HAVE_ARM_ARCH_TIMER
+ select ARM_GIC
+ select ARM_PSCI
+ select PINCTRL
+ select PINCTRL_SPPCTL
+ select SERIAL_SUNPLUS
+ select SERIAL_SUNPLUS_CONSOLE
+ help
+ Support for Sunplus SP7021 SoC. It is based on ARM 4-core
+ Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO,
+ Ethernet, etc.), FPGA interface, chip-to-chip bus.
+ It is designed for industrial control.
diff --git a/arch/arm/mach-sunplus/Makefile b/arch/arm/mach-sunplus/Makefile
new file mode 100644
index 000000000000..d211de6af2db
--- /dev/null
+++ b/arch/arm/mach-sunplus/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-$(CONFIG_SOC_SP7021) += sp7021.o
diff --git a/arch/arm/mach-sunplus/sp7021.c b/arch/arm/mach-sunplus/sp7021.c
new file mode 100644
index 000000000000..774d0a5bd4eb
--- /dev/null
+++ b/arch/arm/mach-sunplus/sp7021.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (C) Sunplus Technology Co., Ltd.
+ * All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <asm/mach/arch.h>
+
+static const char *sp7021_compat[] __initconst = {
+ "sunplus,sp7021",
+ NULL
+};
+
+DT_MACHINE_START(SP7021_DT, "SP7021")
+ .dt_compat = sp7021_compat,
+MACHINE_END
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 09:16:09 +0000