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-rw-r--r--arch/arm/mach-zynq/timer.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index f1d224bf162d..80bf4742fe37 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -39,9 +39,6 @@
#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
-#define XTTCPS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
-#define XTTCPS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
-#define XTTCPS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */