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-rw-r--r--arch/mips/bmips/Makefile1
-rw-r--r--arch/mips/bmips/Platform7
-rw-r--r--arch/mips/bmips/dma.c81
-rw-r--r--arch/mips/bmips/irq.c193
-rw-r--r--arch/mips/bmips/setup.c97
5 files changed, 379 insertions, 0 deletions
diff --git a/arch/mips/bmips/Makefile b/arch/mips/bmips/Makefile
new file mode 100644
index 000000000000..a393955cba08
--- /dev/null
+++ b/arch/mips/bmips/Makefile
@@ -0,0 +1 @@
+obj-y += setup.o irq.o dma.o
diff --git a/arch/mips/bmips/Platform b/arch/mips/bmips/Platform
new file mode 100644
index 000000000000..5f127fd7f4b5
--- /dev/null
+++ b/arch/mips/bmips/Platform
@@ -0,0 +1,7 @@
+#
+# Broadcom Generic BMIPS kernel
+#
+platform-$(CONFIG_BMIPS_GENERIC) += bmips/
+cflags-$(CONFIG_BMIPS_GENERIC) += \
+ -I$(srctree)/arch/mips/include/asm/mach-bmips/
+load-$(CONFIG_BMIPS_GENERIC) := 0xffffffff80010000
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
new file mode 100644
index 000000000000..ea42012fd4f5
--- /dev/null
+++ b/arch/mips/bmips/dma.c
@@ -0,0 +1,81 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
+ */
+
+#include <linux/device.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <dma-coherence.h>
+
+/*
+ * BCM3384 has configurable address translation windows which allow the
+ * peripherals' DMA addresses to be different from the Zephyr-visible
+ * physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
+ *
+ * If our DT "memory" node has a "dma-xor-mask" property we will enable this
+ * translation using the provided offset.
+ */
+static u32 bcm3384_dma_xor_mask;
+static u32 bcm3384_dma_xor_limit = 0xffffffff;
+
+/*
+ * PCI collapses the memory hole at 0x10000000 - 0x1fffffff.
+ * On systems with a dma-xor-mask, this range is guaranteed to live above
+ * the dma-xor-limit.
+ */
+#define BCM3384_MEM_HOLE_PA 0x10000000
+#define BCM3384_MEM_HOLE_SIZE 0x10000000
+
+static dma_addr_t bcm3384_phys_to_dma(struct device *dev, phys_addr_t pa)
+{
+ if (dev && dev_is_pci(dev) &&
+ pa >= (BCM3384_MEM_HOLE_PA + BCM3384_MEM_HOLE_SIZE))
+ return pa - BCM3384_MEM_HOLE_SIZE;
+ if (pa <= bcm3384_dma_xor_limit)
+ return pa ^ bcm3384_dma_xor_mask;
+ return pa;
+}
+
+dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+{
+ return bcm3384_phys_to_dma(dev, virt_to_phys(addr));
+}
+
+dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
+ return bcm3384_phys_to_dma(dev, page_to_phys(page));
+}
+
+unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
+ if (dev && dev_is_pci(dev) &&
+ dma_addr >= BCM3384_MEM_HOLE_PA)
+ return dma_addr + BCM3384_MEM_HOLE_SIZE;
+ if ((dma_addr ^ bcm3384_dma_xor_mask) <= bcm3384_dma_xor_limit)
+ return dma_addr ^ bcm3384_dma_xor_mask;
+ return dma_addr;
+}
+
+static int __init bcm3384_init_dma_xor(void)
+{
+ struct device_node *np = of_find_node_by_type(NULL, "memory");
+
+ if (!np)
+ return 0;
+
+ of_property_read_u32(np, "dma-xor-mask", &bcm3384_dma_xor_mask);
+ of_property_read_u32(np, "dma-xor-limit", &bcm3384_dma_xor_limit);
+
+ of_node_put(np);
+ return 0;
+}
+arch_initcall(bcm3384_init_dma_xor);
diff --git a/arch/mips/bmips/irq.c b/arch/mips/bmips/irq.c
new file mode 100644
index 000000000000..fd94fe849af6
--- /dev/null
+++ b/arch/mips/bmips/irq.c
@@ -0,0 +1,193 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Partially based on arch/mips/ralink/irq.c
+ *
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
+ */
+
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <asm/bmips.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+
+/* INTC register offsets */
+#define INTC_REG_ENABLE 0x00
+#define INTC_REG_STATUS 0x04
+
+#define MAX_WORDS 2
+#define IRQS_PER_WORD 32
+
+struct bcm3384_intc {
+ int n_words;
+ void __iomem *reg[MAX_WORDS];
+ u32 enable[MAX_WORDS];
+ spinlock_t lock;
+};
+
+static void bcm3384_intc_irq_unmask(struct irq_data *d)
+{
+ struct bcm3384_intc *priv = d->domain->host_data;
+ unsigned long flags;
+ int idx = d->hwirq / IRQS_PER_WORD;
+ int bit = d->hwirq % IRQS_PER_WORD;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->enable[idx] |= BIT(bit);
+ __raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
+ spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static void bcm3384_intc_irq_mask(struct irq_data *d)
+{
+ struct bcm3384_intc *priv = d->domain->host_data;
+ unsigned long flags;
+ int idx = d->hwirq / IRQS_PER_WORD;
+ int bit = d->hwirq % IRQS_PER_WORD;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ priv->enable[idx] &= ~BIT(bit);
+ __raw_writel(priv->enable[idx], priv->reg[idx] + INTC_REG_ENABLE);
+ spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static struct irq_chip bcm3384_intc_irq_chip = {
+ .name = "INTC",
+ .irq_unmask = bcm3384_intc_irq_unmask,
+ .irq_mask = bcm3384_intc_irq_mask,
+ .irq_mask_ack = bcm3384_intc_irq_mask,
+};
+
+unsigned int get_c0_compare_int(void)
+{
+ return CP0_LEGACY_COMPARE_IRQ;
+}
+
+static void bcm3384_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct irq_domain *domain = irq_get_handler_data(irq);
+ struct bcm3384_intc *priv = domain->host_data;
+ unsigned long flags;
+ unsigned int idx;
+
+ for (idx = 0; idx < priv->n_words; idx++) {
+ unsigned long pending;
+ int hwirq;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ pending = __raw_readl(priv->reg[idx] + INTC_REG_STATUS) &
+ priv->enable[idx];
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
+ generic_handle_irq(irq_find_mapping(domain,
+ hwirq + idx * IRQS_PER_WORD));
+ }
+ }
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+ unsigned long pending =
+ (read_c0_status() & read_c0_cause() & ST0_IM) >> STATUSB_IP0;
+ int bit;
+
+ for_each_set_bit(bit, &pending, 8)
+ do_IRQ(MIPS_CPU_IRQ_BASE + bit);
+}
+
+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(irq, &bcm3384_intc_irq_chip, handle_level_irq);
+ return 0;
+}
+
+static const struct irq_domain_ops irq_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = intc_map,
+};
+
+static int __init ioremap_one_pair(struct bcm3384_intc *priv,
+ struct device_node *node,
+ int idx)
+{
+ struct resource res;
+
+ if (of_address_to_resource(node, idx, &res))
+ return 0;
+
+ if (request_mem_region(res.start, resource_size(&res),
+ res.name) < 0)
+ pr_err("Failed to request INTC register region\n");
+
+ priv->reg[idx] = ioremap_nocache(res.start, resource_size(&res));
+ if (!priv->reg[idx])
+ panic("Failed to ioremap INTC register range");
+
+ /* start up with everything masked before we hook the parent IRQ */
+ __raw_writel(0, priv->reg[idx] + INTC_REG_ENABLE);
+ priv->enable[idx] = 0;
+
+ return IRQS_PER_WORD;
+}
+
+static int __init intc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_domain *domain;
+ unsigned int parent_irq, n_irqs = 0;
+ struct bcm3384_intc *priv;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ panic("Failed to allocate bcm3384_intc struct");
+
+ spin_lock_init(&priv->lock);
+
+ parent_irq = irq_of_parse_and_map(node, 0);
+ if (!parent_irq)
+ panic("Failed to get INTC IRQ");
+
+ n_irqs += ioremap_one_pair(priv, node, 0);
+ n_irqs += ioremap_one_pair(priv, node, 1);
+
+ if (!n_irqs)
+ panic("Failed to map INTC registers");
+
+ priv->n_words = n_irqs / IRQS_PER_WORD;
+ domain = irq_domain_add_linear(node, n_irqs, &irq_domain_ops, priv);
+ if (!domain)
+ panic("Failed to add irqdomain");
+
+ irq_set_chained_handler(parent_irq, bcm3384_intc_irq_handler);
+ irq_set_handler_data(parent_irq, domain);
+
+ return 0;
+}
+
+static struct of_device_id of_irq_ids[] __initdata = {
+ { .compatible = "mti,cpu-interrupt-controller",
+ .data = mips_cpu_irq_of_init },
+ { .compatible = "brcm,bcm3384-intc",
+ .data = intc_of_init },
+ {},
+};
+
+void __init arch_init_irq(void)
+{
+ bmips_tp1_irqs = 0;
+ of_irq_init(of_irq_ids);
+}
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
new file mode 100644
index 000000000000..5099109b2325
--- /dev/null
+++ b/arch/mips/bmips/setup.c
@@ -0,0 +1,97 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
+ */
+
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/clk-provider.h>
+#include <linux/ioport.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <linux/smp.h>
+#include <asm/addrspace.h>
+#include <asm/bmips.h>
+#include <asm/bootinfo.h>
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+#include <asm/time.h>
+
+void __init prom_init(void)
+{
+ register_bmips_smp_ops();
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+const char *get_system_type(void)
+{
+ return "Generic BMIPS kernel";
+}
+
+void __init plat_time_init(void)
+{
+ struct device_node *np;
+ u32 freq;
+
+ np = of_find_node_by_name(NULL, "cpus");
+ if (!np)
+ panic("missing 'cpus' DT node");
+ if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
+ panic("missing 'mips-hpt-frequency' property");
+ of_node_put(np);
+
+ mips_hpt_frequency = freq;
+}
+
+void __init plat_mem_setup(void)
+{
+ void *dtb = __dtb_start;
+
+ set_io_port_base(0);
+ ioport_resource.start = 0;
+ ioport_resource.end = ~0;
+
+ /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
+ if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
+ dtb = phys_to_virt(fw_arg2);
+
+ __dt_setup_arch(dtb);
+
+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
+}
+
+void __init device_tree_init(void)
+{
+ struct device_node *np;
+
+ unflatten_and_copy_device_tree();
+
+ /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
+ np = of_find_node_by_name(NULL, "cpus");
+ if (np && of_get_available_child_count(np) <= 1)
+ bmips_smp_enabled = 0;
+ of_node_put(np);
+}
+
+int __init plat_of_setup(void)
+{
+ return __dt_register_buses("brcm,bcm3384", "simple-bus");
+}
+
+arch_initcall(plat_of_setup);
+
+static int __init plat_dev_init(void)
+{
+ of_clk_init(NULL);
+ return 0;
+}
+
+device_initcall(plat_dev_init);
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 01:32:41 +0000