diff options
Diffstat (limited to 'arch/mips/mips-boards')
| -rw-r--r-- | arch/mips/mips-boards/generic/init.c | 29 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/memory.c | 29 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/mipsIRQ.S | 110 | ||||
| -rw-r--r-- | arch/mips/mips-boards/generic/time.c | 49 | ||||
| -rw-r--r-- | arch/mips/mips-boards/malta/malta_int.c | 136 |
5 files changed, 243 insertions, 110 deletions
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c index d821b13d24a0..58256ea33102 100644 --- a/arch/mips/mips-boards/generic/init.c +++ b/arch/mips/mips-boards/generic/init.c @@ -28,6 +28,8 @@ #include <asm/gt64120.h> #include <asm/io.h> #include <asm/system.h> +#include <asm/cacheflush.h> +#include <asm/traps.h> #include <asm/mips-boards/prom.h> #include <asm/mips-boards/generic.h> @@ -224,6 +226,30 @@ void __init kgdb_config (void) } #endif +void __init mips_nmi_setup (void) +{ + void *base; + extern char except_vec_nmi; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); + memcpy(base, &except_vec_nmi, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + +void __init mips_ejtag_setup (void) +{ + void *base; + extern char except_vec_ejtag_debug; + + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); + memcpy(base, &except_vec_ejtag_debug, 0x80); + flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); +} + void __init prom_init(void) { u32 start, map, mask, data; @@ -353,6 +379,9 @@ void __init prom_init(void) while(1); /* We die here... */ } #endif + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c index 5ae2b43e4c2e..2c8afd77a20b 100644 --- a/arch/mips/mips-boards/generic/memory.c +++ b/arch/mips/mips-boards/generic/memory.c @@ -22,6 +22,7 @@ #include <linux/init.h> #include <linux/mm.h> #include <linux/bootmem.h> +#include <linux/string.h> #include <asm/bootinfo.h> #include <asm/page.h> @@ -55,18 +56,30 @@ struct prom_pmemblock * __init prom_getmdesc(void) { char *memsize_str; unsigned int memsize; + char cmdline[CL_SIZE], *ptr; - memsize_str = prom_getenv("memsize"); - if (!memsize_str) { - prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); - memsize = 0x02000000; - } else { + /* Check the command line first for a memsize directive */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) { + memsize = memparse(ptr + 8, &ptr); + } + else { + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + if (!memsize_str) { + prom_printf("memsize not set in boot prom, set to default (32Mb)\n"); + memsize = 0x02000000; + } else { #ifdef DEBUG - prom_printf("prom_memsize = %s\n", memsize_str); + prom_printf("prom_memsize = %s\n", memsize_str); #endif - memsize = simple_strtol(memsize_str, NULL, 0); + memsize = simple_strtol(memsize_str, NULL, 0); + } } - memset(mdesc, 0, sizeof(mdesc)); mdesc[0].type = yamon_dontuse; diff --git a/arch/mips/mips-boards/generic/mipsIRQ.S b/arch/mips/mips-boards/generic/mipsIRQ.S index 131f49bccb20..a397ecb872d6 100644 --- a/arch/mips/mips-boards/generic/mipsIRQ.S +++ b/arch/mips/mips-boards/generic/mipsIRQ.S @@ -29,6 +29,20 @@ #include <asm/regdef.h> #include <asm/stackframe.h> +#ifdef CONFIG_MIPS_ATLAS +#include <asm/mips-boards/atlasint.h> +#define CASCADE_IRQ MIPSCPU_INT_ATLAS +#define CASCADE_DISPATCH atlas_hw0_irqdispatch +#endif +#ifdef CONFIG_MIPS_MALTA +#include <asm/mips-boards/maltaint.h> +#define CASCADE_IRQ MIPSCPU_INT_I8259A +#define CASCADE_DISPATCH malta_hw0_irqdispatch +#endif +#ifdef CONFIG_MIPS_SEAD +#include <asm/mips-boards/seadint.h> +#endif + /* A lot of complication here is taken away because: * * 1) We handle one interrupt and return, sitting in a loop and moving across @@ -80,74 +94,62 @@ mfc0 s0, CP0_CAUSE # get irq bits mfc0 s1, CP0_STATUS # get irq mask + andi s0, ST0_IM # CAUSE.CE may be non-zero! and s0, s1 - /* First we check for r4k counter/timer IRQ. */ - andi a0, s0, CAUSEF_IP7 - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + .set mips32 + clz a0, s0 + .set mips0 + negu a0 + addu a0, 31-CAUSEB_IP + bltz a0, spurious +#else + beqz s0, spurious + li a0, 7 - /* Wheee, a timer interrupt. */ - move a0, sp - jal mips_timer_interrupt - nop + and t0, s0, 0xf000 + sltiu t0, t0, 1 + sll t0, 2 + subu a0, t0 + sll s0, t0 - j ret_from_irq - nop + and t0, s0, 0xc000 + sltiu t0, t0, 1 + sll t0, 1 + subu a0, t0 + sll s0, t0 -1: -#if defined(CONFIG_MIPS_SEAD) - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt -#else - beq a0, zero, 1f # delay slot, check hw3 interrupt - andi a0, s0, CAUSEF_IP5 + and t0, s0, 0x8000 + sltiu t0, t0, 1 + # sll t0, 0 + subu a0, t0 + # sll s0, t0 #endif - /* Wheee, combined hardware level zero interrupt. */ -#if defined(CONFIG_MIPS_ATLAS) - jal atlas_hw0_irqdispatch -#elif defined(CONFIG_MIPS_MALTA) - jal malta_hw0_irqdispatch -#elif defined(CONFIG_MIPS_SEAD) - jal sead_hw0_irqdispatch -#else -#error "MIPS board not supported\n" -#endif - move a0, sp # delay slot +#ifdef CASCADE_IRQ + li a1, CASCADE_IRQ + bne a0, a1, 1f + addu a0, MIPSCPU_INT_BASE - j ret_from_irq - nop # delay slot + jal CASCADE_DISPATCH + move a0, sp -1: -#if defined(CONFIG_MIPS_SEAD) - beq a0, zero, 1f - andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt - jal sead_hw1_irqdispatch - move a0, sp # delay slot - j ret_from_irq - nop # delay slot -1: -#endif -#if defined(CONFIG_MIPS_MALTA) - beq a0, zero, 1f # check hw3 (coreHI) interrupt - nop - jal corehi_irqdispatch - move a0, sp j ret_from_irq nop 1: +#else + addu a0, MIPSCPU_INT_BASE #endif - /* - * Here by mistake? This is possible, what can happen is that by the - * time we take the exception the IRQ pin goes low, so just leave if - * this is the case. - */ - move a1,s0 - PRINT("Got interrupt: c0_cause = %08x\n") - mfc0 a1, CP0_EPC - PRINT("c0_epc = %08x\n") + + jal do_IRQ + move a1, sp j ret_from_irq nop + + +spurious: + j spurious_interrupt + nop END(mipsIRQ) diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index 16315444dd5a..3a6f1428b2cb 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -31,22 +31,21 @@ #include <asm/mipsregs.h> #include <asm/ptrace.h> +#include <asm/hardirq.h> +#include <asm/irq.h> #include <asm/div64.h> #include <asm/cpu.h> #include <asm/time.h> #include <asm/mc146818-time.h> +#include <asm/msc01_ic.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/prom.h> +#include <asm/mips-boards/maltaint.h> +#include <asm/mc146818-time.h> unsigned long cpu_khz; -#if defined(CONFIG_MIPS_SEAD) -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5) -#else -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) -#endif - #if defined(CONFIG_MIPS_ATLAS) static char display_string[] = " LINUX ON ATLAS "; #endif @@ -59,20 +58,27 @@ static char display_string[] = " LINUX ON SEAD "; static unsigned int display_count = 0; #define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) -#define MIPS_CPU_TIMER_IRQ (NR_IRQS-1) - static unsigned int timer_tick_count=0; +static int mips_cpu_timer_irq; -void mips_timer_interrupt(struct pt_regs *regs) +static void mips_timer_dispatch (struct pt_regs *regs) { + do_IRQ (mips_cpu_timer_irq, regs); +} + +irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) +{ + irqreturn_t r; + + r = timer_interrupt(irq, dev_id, regs); + if ((timer_tick_count++ % HZ) == 0) { mips_display_message(&display_string[display_count++]); if (display_count == MAX_DISPLAY_COUNT) - display_count = 0; - + display_count = 0; } - ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs); + return r; } /* @@ -140,10 +146,8 @@ void __init mips_time_init(void) local_irq_save(flags); -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) /* Set Data mode - binary. */ CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); -#endif est_freq = estimate_cpu_frequency (); @@ -157,11 +161,22 @@ void __init mips_time_init(void) void __init mips_timer_setup(struct irqaction *irq) { + if (cpu_has_veic) { + set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; + } + else { + if (cpu_has_vint) + set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); + mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; + } + + /* we are using the cpu counter for timer interrupts */ - irq->handler = no_action; /* we use our own handler */ - setup_irq(MIPS_CPU_TIMER_IRQ, irq); + irq->handler = mips_timer_interrupt; /* we use our own handler */ + setup_irq(mips_cpu_timer_irq, irq); + /* to generate the first timer interrupt */ write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); - set_c0_status(ALLINTS); } diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index dd2db35966bc..6f99a4492015 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -30,6 +30,7 @@ #include <linux/random.h> #include <asm/i8259.h> +#include <asm/irq_cpu.h> #include <asm/io.h> #include <asm/mips-boards/malta.h> #include <asm/mips-boards/maltaint.h> @@ -37,8 +38,10 @@ #include <asm/gt64120.h> #include <asm/mips-boards/generic.h> #include <asm/mips-boards/msc01_pci.h> +#include <asm/msc01_ic.h> extern asmlinkage void mipsIRQ(void); +extern void mips_timer_interrupt(void); static DEFINE_SPINLOCK(mips_irq_lock); @@ -91,13 +94,13 @@ static inline int mips_pcibios_iack(void) return irq; } -static inline int get_int(int *irq) +static inline int get_int(void) { unsigned long flags; - + int irq; spin_lock_irqsave(&mips_irq_lock, flags); - *irq = mips_pcibios_iack(); + irq = mips_pcibios_iack(); /* * IRQ7 is used to detect spurious interrupts. @@ -106,73 +109,82 @@ static inline int get_int(int *irq) * We can differentiate between this situation and a * "Normal" IRQ7 by reading the ISR. */ - if (*irq == 7) + if (irq == 7) { outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, PIIX4_ICTLR1_OCW3); if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) { - spin_unlock_irqrestore(&mips_irq_lock, flags); + irq = -1; /* Spurious interrupt */ printk("We got a spurious interrupt from PIIX4.\n"); atomic_inc(&irq_err_count); - return -1; /* Spurious interrupt. */ } } spin_unlock_irqrestore(&mips_irq_lock, flags); - return 0; + return irq; } void malta_hw0_irqdispatch(struct pt_regs *regs) { int irq; - if (get_int(&irq)) - return; /* interrupt has already been cleared */ + irq = get_int(); + if (irq < 0) + return; /* interrupt has already been cleared */ - do_IRQ(irq, regs); + do_IRQ(MALTA_INT_BASE+irq, regs); } void corehi_irqdispatch(struct pt_regs *regs) { - unsigned int data,datahi; - - /* Mask out corehi interrupt. */ - clear_c0_status(IE_IRQ3); + unsigned int intrcause,datalo,datahi; + unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr; printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); + + /* Read all the registers and then print them as there is a + problem with interspersed printk's upsetting the Bonito controller. + Do it for the others too. + */ + switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + ll_msc_irq(regs); break; case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: - data = GT_READ(GT_INTRCAUSE_OFS); - printk("GT_INTRCAUSE = %08x\n", data); - data = GT_READ(GT_CPUERR_ADDRLO_OFS); + intrcause = GT_READ(GT_INTRCAUSE_OFS); + datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); - printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, data); + printk("GT_INTRCAUSE = %08x\n", intrcause); + printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: case MIPS_REVISION_CORID_CORE_EMUL_BON: - data = BONITO_INTISR; - printk("BONITO_INTISR = %08x\n", data); - data = BONITO_INTEN; - printk("BONITO_INTEN = %08x\n", data); - data = BONITO_INTPOL; - printk("BONITO_INTPOL = %08x\n", data); - data = BONITO_INTEDGE; - printk("BONITO_INTEDGE = %08x\n", data); - data = BONITO_INTSTEER; - printk("BONITO_INTSTEER = %08x\n", data); - data = BONITO_PCICMD; - printk("BONITO_PCICMD = %08x\n", data); + pcibadaddr = BONITO_PCIBADADDR; + pcimstat = BONITO_PCIMSTAT; + intisr = BONITO_INTISR; + inten = BONITO_INTEN; + intpol = BONITO_INTPOL; + intedge = BONITO_INTEDGE; + intsteer = BONITO_INTSTEER; + pcicmd = BONITO_PCICMD; + printk("BONITO_INTISR = %08x\n", intisr); + printk("BONITO_INTEN = %08x\n", inten); + printk("BONITO_INTPOL = %08x\n", intpol); + printk("BONITO_INTEDGE = %08x\n", intedge); + printk("BONITO_INTSTEER = %08x\n", intsteer); + printk("BONITO_PCICMD = %08x\n", pcicmd); + printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr); + printk("BONITO_PCIMSTAT = %08x\n", pcimstat); break; } @@ -180,8 +192,70 @@ void corehi_irqdispatch(struct pt_regs *regs) die("CoreHi interrupt", regs); } +static struct irqaction i8259irq = { + .handler = no_action, + .name = "XT-PIC cascade" +}; + +static struct irqaction corehi_irqaction = { + .handler = no_action, + .name = "CoreHi" +}; + +msc_irqmap_t __initdata msc_irqmap[] = { + {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, +}; +int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t); + +msc_irqmap_t __initdata msc_eicirqmap[] = { + {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, + {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, + {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} +}; +int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t); + void __init arch_init_irq(void) { set_except_vector(0, mipsIRQ); init_i8259_irqs(); + + if (!cpu_has_veic) + mips_cpu_irq_init (MIPSCPU_INT_BASE); + + switch(mips_revision_corid) { + case MIPS_REVISION_CORID_CORE_MSC: + case MIPS_REVISION_CORID_CORE_FPGA2: + case MIPS_REVISION_CORID_CORE_EMUL_MSC: + if (cpu_has_veic) + init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); + else + init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); + } + + if (cpu_has_veic) { + set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); + setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); + setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); + } + else if (cpu_has_vint) { + set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); + set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); + + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + } + else { + set_except_vector(0, mipsIRQ); + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); + setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); + } } |