diff options
Diffstat (limited to 'drivers/clk/tegra/clk-dfll.h')
| -rw-r--r-- | drivers/clk/tegra/clk-dfll.h | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 2e4c0772a5dc..ed2ad888268f 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -24,22 +24,18 @@ /** * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver - * @opp_dev: struct device * that holds the OPP table for the DFLL - * @min_millivolts: minimum voltage (in mV) that the DFLL can operate - * @tune0_low: DFLL tuning register 0 (low voltage range) - * @tune0_high: DFLL tuning register 0 (high voltage range) - * @tune1: DFLL tuning register 1 - * @assert_dvco_reset: fn ptr to place the DVCO in reset - * @deassert_dvco_reset: fn ptr to release the DVCO reset - * @set_clock_trimmers_high: fn ptr to tune clock trimmers for high voltage - * @set_clock_trimmers_low: fn ptr to tune clock trimmers for low voltage + * @dev: struct device * that holds the OPP table for the DFLL + * @max_freq: maximum frequency supported on this SoC + * @cvb: CPU frequency table for this SoC + * @init_clock_trimmers: callback to initialize clock trimmers + * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage + * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage */ struct tegra_dfll_soc_data { struct device *dev; - unsigned int min_millivolts; - u32 tune0_low; - u32 tune0_high; - u32 tune1; + unsigned long max_freq; + const struct cvb_table *cvb; + void (*init_clock_trimmers)(void); void (*set_clock_trimmers_high)(void); void (*set_clock_trimmers_low)(void); |