diff options
Diffstat (limited to 'drivers')
254 files changed, 19228 insertions, 2660 deletions
diff --git a/drivers/acpi/arm64/amba.c b/drivers/acpi/arm64/amba.c index b2a7631d7ac7..60be8ee1dbdc 100644 --- a/drivers/acpi/arm64/amba.c +++ b/drivers/acpi/arm64/amba.c @@ -22,7 +22,6 @@ static const struct acpi_device_id amba_id_list[] = { {"ARMH0061", 0}, /* PL061 GPIO Device */ {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */ - {"ARMHC500", 0}, /* ARM CoreSight ETM4x */ {"ARMHC501", 0}, /* ARM CoreSight ETR */ {"ARMHC502", 0}, /* ARM CoreSight STM */ {"ARMHC503", 0}, /* ARM CoreSight Debug */ diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index ce88af9eb562..09e72967b8ab 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -528,6 +528,7 @@ static void amba_device_release(struct device *dev) { struct amba_device *d = to_amba_device(dev); + of_node_put(d->dev.of_node); if (d->res.parent) release_resource(&d->res); mutex_destroy(&d->periphid_lock); diff --git a/drivers/android/binder.c b/drivers/android/binder.c index d720f93d8b19..367afac5f1bf 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -6557,6 +6557,7 @@ static int __init binder_init(void) struct binder_device *device; struct hlist_node *tmp; char *device_names = NULL; + const struct binder_debugfs_entry *db_entry; ret = binder_alloc_shrinker_init(); if (ret) @@ -6566,19 +6567,16 @@ static int __init binder_init(void) atomic_set(&binder_transaction_log_failed.cur, ~0U); binder_debugfs_dir_entry_root = debugfs_create_dir("binder", NULL); - if (binder_debugfs_dir_entry_root) { - const struct binder_debugfs_entry *db_entry; - binder_for_each_debugfs_entry(db_entry) - debugfs_create_file(db_entry->name, - db_entry->mode, - binder_debugfs_dir_entry_root, - db_entry->data, - db_entry->fops); + binder_for_each_debugfs_entry(db_entry) + debugfs_create_file(db_entry->name, + db_entry->mode, + binder_debugfs_dir_entry_root, + db_entry->data, + db_entry->fops); - binder_debugfs_dir_entry_proc = debugfs_create_dir("proc", - binder_debugfs_dir_entry_root); - } + binder_debugfs_dir_entry_proc = debugfs_create_dir("proc", + binder_debugfs_dir_entry_root); if (!IS_ENABLED(CONFIG_ANDROID_BINDERFS) && strcmp(binder_devices_param, "") != 0) { diff --git a/drivers/android/binderfs.c b/drivers/android/binderfs.c index faebe9f5412a..81effec17b3d 100644 --- a/drivers/android/binderfs.c +++ b/drivers/android/binderfs.c @@ -19,7 +19,6 @@ #include <linux/mutex.h> #include <linux/mount.h> #include <linux/fs_parser.h> -#include <linux/radix-tree.h> #include <linux/sched.h> #include <linux/seq_file.h> #include <linux/slab.h> diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c index d2a19b07ccb8..edc0ec5a0933 100644 --- a/drivers/bus/mhi/host/boot.c +++ b/drivers/bus/mhi/host/boot.c @@ -365,12 +365,10 @@ error_alloc_mhi_buf: } static void mhi_firmware_copy(struct mhi_controller *mhi_cntrl, - const struct firmware *firmware, + const u8 *buf, size_t remainder, struct image_info *img_info) { - size_t remainder = firmware->size; size_t to_cpy; - const u8 *buf = firmware->data; struct mhi_buf *mhi_buf = img_info->mhi_buf; struct bhi_vec_entry *bhi_vec = img_info->bhi_vec; @@ -393,9 +391,10 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) struct device *dev = &mhi_cntrl->mhi_dev->dev; enum mhi_pm_state new_state; const char *fw_name; + const u8 *fw_data; void *buf; dma_addr_t dma_addr; - size_t size; + size_t size, fw_sz; int i, ret; if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) { @@ -425,6 +424,20 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) fw_name = (mhi_cntrl->ee == MHI_EE_EDL) ? mhi_cntrl->edl_image : mhi_cntrl->fw_image; + /* check if the driver has already provided the firmware data */ + if (!fw_name && mhi_cntrl->fbc_download && + mhi_cntrl->fw_data && mhi_cntrl->fw_sz) { + if (!mhi_cntrl->sbl_size) { + dev_err(dev, "fw_data provided but no sbl_size\n"); + goto error_fw_load; + } + + size = mhi_cntrl->sbl_size; + fw_data = mhi_cntrl->fw_data; + fw_sz = mhi_cntrl->fw_sz; + goto skip_req_fw; + } + if (!fw_name || (mhi_cntrl->fbc_download && (!mhi_cntrl->sbl_size || !mhi_cntrl->seg_len))) { dev_err(dev, @@ -444,6 +457,10 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) if (size > firmware->size) size = firmware->size; + fw_data = firmware->data; + fw_sz = firmware->size; + +skip_req_fw: buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, size, &dma_addr, GFP_KERNEL); if (!buf) { @@ -452,7 +469,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) } /* Download image using BHI */ - memcpy(buf, firmware->data, size); + memcpy(buf, fw_data, size); ret = mhi_fw_load_bhi(mhi_cntrl, dma_addr, size); dma_free_coherent(mhi_cntrl->cntrl_dev, size, buf, dma_addr); @@ -464,7 +481,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) } /* Wait for ready since EDL image was loaded */ - if (fw_name == mhi_cntrl->edl_image) { + if (fw_name && fw_name == mhi_cntrl->edl_image) { release_firmware(firmware); goto fw_load_ready_state; } @@ -478,15 +495,14 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) * device transitioning into MHI READY state */ if (mhi_cntrl->fbc_download) { - ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image, - firmware->size); + ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image, fw_sz); if (ret) { release_firmware(firmware); goto error_fw_load; } /* Load the firmware into BHIE vec table */ - mhi_firmware_copy(mhi_cntrl, firmware, mhi_cntrl->fbc_image); + mhi_firmware_copy(mhi_cntrl, fw_data, fw_sz, mhi_cntrl->fbc_image); } release_firmware(firmware); diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index f72fcb66f408..f78aefd2d7a3 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -759,7 +759,7 @@ static int parse_ch_cfg(struct mhi_controller *mhi_cntrl, * so to avoid any memory possible allocation failures, vzalloc is * used here */ - mhi_cntrl->mhi_chan = vzalloc(mhi_cntrl->max_chan * + mhi_cntrl->mhi_chan = vcalloc(mhi_cntrl->max_chan, sizeof(*mhi_cntrl->mhi_chan)); if (!mhi_cntrl->mhi_chan) return -ENOMEM; diff --git a/drivers/bus/mhi/host/main.c b/drivers/bus/mhi/host/main.c index 74a75439c713..dcf627b36e82 100644 --- a/drivers/bus/mhi/host/main.c +++ b/drivers/bus/mhi/host/main.c @@ -938,7 +938,6 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, if (!mhi_chan->configured) break; parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); - event_quota--; } break; default: diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index db0a0b062d8e..08f3f039dbdd 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -212,6 +212,19 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } +#define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ + { \ + .num_elements = el_count, \ + .irq_moderation_ms = 0, \ + .irq = (ev_ring) + 1, \ + .priority = 1, \ + .mode = MHI_DB_BRST_DISABLE, \ + .data_type = MHI_ER_DATA, \ + .hardware_event = false, \ + .client_managed = false, \ + .offload_channel = false, \ + } + #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ { \ .num_elements = el_count, \ @@ -237,8 +250,10 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), - MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), - MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), }; static struct mhi_event_config modem_qcom_v1_mhi_events[] = { @@ -246,9 +261,12 @@ static struct mhi_event_config modem_qcom_v1_mhi_events[] = { MHI_EVENT_CONFIG_CTRL(0, 64), /* DIAG dedicated event ring */ MHI_EVENT_CONFIG_DATA(1, 128), + /* Software channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(2, 64), + MHI_EVENT_CONFIG_SW_DATA(3, 64), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), - MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) + MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) }; static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { @@ -334,6 +352,16 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { .sideband_wake = true, }; +static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { + .name = "quectel-rm5xx", + .edl = "qcom/prog_firehose_sdx6x.elf", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .mru_default = 32768, + .sideband_wake = true, +}; + static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), @@ -567,12 +595,23 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* Telit FN990 */ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, + /* Telit FE990 */ + { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), + .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + /* RM520N-GL (sdx6x), eSIM */ + { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), + .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, + /* RM520N-GL (sdx6x), Lenovo variant */ + { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), + .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, + { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ @@ -605,6 +644,12 @@ static const struct pci_device_id mhi_pci_id_table[] = { /* T99W510 (sdx24), variant 3 */ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info }, + /* DW5932e-eSIM (sdx62), With eSIM */ + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, + /* DW5932e (sdx62), Non-eSIM */ + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, /* MV31-W (Cinterion) */ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), .driver_data = (kernel_ulong_t) &mhi_mv31_info }, diff --git a/drivers/bus/mhi/host/pm.c b/drivers/bus/mhi/host/pm.c index 083459028a4b..8a4362d75fc4 100644 --- a/drivers/bus/mhi/host/pm.c +++ b/drivers/bus/mhi/host/pm.c @@ -470,6 +470,10 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl) /* Trigger MHI RESET so that the device will not access host memory */ if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) { + /* Skip MHI RESET if in RDDM state */ + if (mhi_cntrl->rddm_image && mhi_get_exec_env(mhi_cntrl) == MHI_EE_RDDM) + goto skip_mhi_reset; + dev_dbg(dev, "Triggering MHI Reset in device\n"); mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET); @@ -495,6 +499,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl) } } +skip_mhi_reset: dev_dbg(dev, "Waiting for all pending event ring processing to complete\n"); mhi_event = mhi_cntrl->mhi_event; diff --git a/drivers/cdx/controller/cdx_controller.c b/drivers/cdx/controller/cdx_controller.c index dc52f95f8978..bb4ae7970e21 100644 --- a/drivers/cdx/controller/cdx_controller.c +++ b/drivers/cdx/controller/cdx_controller.c @@ -5,7 +5,8 @@ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. */ -#include <linux/of_platform.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <linux/slab.h> #include <linux/cdx/cdx_bus.h> diff --git a/drivers/cdx/controller/cdx_rpmsg.c b/drivers/cdx/controller/cdx_rpmsg.c index f37e639d6ce3..04b578a0be17 100644 --- a/drivers/cdx/controller/cdx_rpmsg.c +++ b/drivers/cdx/controller/cdx_rpmsg.c @@ -7,7 +7,8 @@ #include <linux/rpmsg.h> #include <linux/remoteproc.h> -#include <linux/of_platform.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/cdx/cdx_bus.h> #include <linux/module.h> diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c index 62de7f4ba864..84411b13c49f 100644 --- a/drivers/char/agp/uninorth-agp.c +++ b/drivers/char/agp/uninorth-agp.c @@ -3,6 +3,7 @@ * UniNorth AGPGART routines. */ #include <linux/module.h> +#include <linux/of.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/init.h> diff --git a/drivers/char/bsr.c b/drivers/char/bsr.c index 12143854aeac..70d31aed9011 100644 --- a/drivers/char/bsr.c +++ b/drivers/char/bsr.c @@ -6,11 +6,10 @@ * Author: Sonny Rao <sonnyrao@us.ibm.com> */ +#include <linux/device.h> #include <linux/kernel.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> #include <linux/fs.h> #include <linux/module.h> #include <linux/cdev.h> diff --git a/drivers/char/xillybus/Kconfig b/drivers/char/xillybus/Kconfig index a8036dad437e..f51d533390a9 100644 --- a/drivers/char/xillybus/Kconfig +++ b/drivers/char/xillybus/Kconfig @@ -29,7 +29,7 @@ config XILLYBUS_PCIE config XILLYBUS_OF tristate "Xillybus over Device Tree" - depends on OF && HAS_DMA + depends on OF && HAS_DMA && HAS_IOMEM help Set to M if you want Xillybus to find its resources from the Open Firmware Flattened Device Tree. If the target is an embedded diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c index e2d1dc6ca668..975e431d1590 100644 --- a/drivers/counter/microchip-tcb-capture.c +++ b/drivers/counter/microchip-tcb-capture.c @@ -10,7 +10,6 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <soc/at91/atmel_tcb.h> diff --git a/drivers/counter/rz-mtu3-cnt.c b/drivers/counter/rz-mtu3-cnt.c index 48c83933aa2f..ee821493b166 100644 --- a/drivers/counter/rz-mtu3-cnt.c +++ b/drivers/counter/rz-mtu3-cnt.c @@ -500,8 +500,8 @@ static int rz_mtu3_count_enable_write(struct counter_device *counter, int ret = 0; if (enable) { - pm_runtime_get_sync(ch->dev); mutex_lock(&priv->lock); + pm_runtime_get_sync(ch->dev); ret = rz_mtu3_initialize_counter(counter, count->id); if (ret == 0) priv->count_is_enabled[count->id] = true; @@ -510,8 +510,8 @@ static int rz_mtu3_count_enable_write(struct counter_device *counter, mutex_lock(&priv->lock); rz_mtu3_terminate_counter(counter, count->id); priv->count_is_enabled[count->id] = false; - mutex_unlock(&priv->lock); pm_runtime_put(ch->dev); + mutex_unlock(&priv->lock); } return ret; diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index 0ef1971d22bb..8de9023c2a38 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -62,6 +62,7 @@ config EXTCON_INTEL_CHT_WC tristate "Intel Cherrytrail Whiskey Cove PMIC extcon driver" depends on INTEL_SOC_PMIC_CHTWC depends on USB_SUPPORT + depends on POWER_SUPPLY select USB_ROLE_SWITCH help Say Y here to enable extcon support for charger detection / control diff --git a/drivers/firmware/google/Kconfig b/drivers/firmware/google/Kconfig index 1bc7cbf2f65d..41b78f5cb735 100644 --- a/drivers/firmware/google/Kconfig +++ b/drivers/firmware/google/Kconfig @@ -59,7 +59,7 @@ config GOOGLE_MEMCONSOLE_X86_LEGACY config GOOGLE_FRAMEBUFFER_COREBOOT tristate "Coreboot Framebuffer" - depends on FB_SIMPLE + depends on FB_SIMPLE || DRM_SIMPLEDRM depends on GOOGLE_COREBOOT_TABLE help This option enables the kernel to search for a framebuffer in diff --git a/drivers/firmware/stratix10-rsu.c b/drivers/firmware/stratix10-rsu.c index ab3074705380..4f7a7abada48 100644 --- a/drivers/firmware/stratix10-rsu.c +++ b/drivers/firmware/stratix10-rsu.c @@ -33,6 +33,10 @@ #define INVALID_RETRY_COUNTER 0xFF #define INVALID_DCMF_VERSION 0xFF #define INVALID_DCMF_STATUS 0xFFFFFFFF +#define INVALID_SPT_ADDRESS 0x0 + +#define RSU_GET_SPT_CMD 0x5A +#define RSU_GET_SPT_RESP_LEN (4 * sizeof(unsigned int)) typedef void (*rsu_callback)(struct stratix10_svc_client *client, struct stratix10_svc_cb_data *data); @@ -58,6 +62,9 @@ typedef void (*rsu_callback)(struct stratix10_svc_client *client, * @dcmf_status.dcmf3: dcmf3 status * @retry_counter: the current image's retry counter * @max_retry: the preset max retry value + * @spt0_address: address of spt0 + * @spt1_address: address of spt1 + * @get_spt_response_buf: response from sdm for get_spt command */ struct stratix10_rsu_priv { struct stratix10_svc_chan *chan; @@ -89,6 +96,11 @@ struct stratix10_rsu_priv { unsigned int retry_counter; unsigned int max_retry; + + unsigned long spt0_address; + unsigned long spt1_address; + + unsigned int *get_spt_response_buf; }; /** @@ -258,6 +270,36 @@ static void rsu_dcmf_status_callback(struct stratix10_svc_client *client, complete(&priv->completion); } +static void rsu_get_spt_callback(struct stratix10_svc_client *client, + struct stratix10_svc_cb_data *data) +{ + struct stratix10_rsu_priv *priv = client->priv; + unsigned long *mbox_err = (unsigned long *)data->kaddr1; + unsigned long *resp_len = (unsigned long *)data->kaddr2; + + if (data->status != BIT(SVC_STATUS_OK) || (*mbox_err) || + (*resp_len != RSU_GET_SPT_RESP_LEN)) + goto error; + + priv->spt0_address = priv->get_spt_response_buf[0]; + priv->spt0_address <<= 32; + priv->spt0_address |= priv->get_spt_response_buf[1]; + + priv->spt1_address = priv->get_spt_response_buf[2]; + priv->spt1_address <<= 32; + priv->spt1_address |= priv->get_spt_response_buf[3]; + + goto complete; + +error: + dev_err(client->dev, "failed to get SPTs\n"); + +complete: + stratix10_svc_free_memory(priv->chan, priv->get_spt_response_buf); + priv->get_spt_response_buf = NULL; + complete(&priv->completion); +} + /** * rsu_send_msg() - send a message to Intel service layer * @priv: pointer to rsu private data @@ -287,6 +329,14 @@ static int rsu_send_msg(struct stratix10_rsu_priv *priv, if (arg) msg.arg[0] = arg; + if (command == COMMAND_MBOX_SEND_CMD) { + msg.arg[1] = 0; + msg.payload = NULL; + msg.payload_length = 0; + msg.payload_output = priv->get_spt_response_buf; + msg.payload_length_output = RSU_GET_SPT_RESP_LEN; + } + ret = stratix10_svc_send(priv->chan, &msg); if (ret < 0) goto status_done; @@ -571,6 +621,34 @@ static ssize_t notify_store(struct device *dev, return count; } +static ssize_t spt0_address_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stratix10_rsu_priv *priv = dev_get_drvdata(dev); + + if (!priv) + return -ENODEV; + + if (priv->spt0_address == INVALID_SPT_ADDRESS) + return -EIO; + + return scnprintf(buf, PAGE_SIZE, "0x%08lx\n", priv->spt0_address); +} + +static ssize_t spt1_address_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stratix10_rsu_priv *priv = dev_get_drvdata(dev); + + if (!priv) + return -ENODEV; + + if (priv->spt1_address == INVALID_SPT_ADDRESS) + return -EIO; + + return scnprintf(buf, PAGE_SIZE, "0x%08lx\n", priv->spt1_address); +} + static DEVICE_ATTR_RO(current_image); static DEVICE_ATTR_RO(fail_image); static DEVICE_ATTR_RO(state); @@ -589,6 +667,8 @@ static DEVICE_ATTR_RO(dcmf2_status); static DEVICE_ATTR_RO(dcmf3_status); static DEVICE_ATTR_WO(reboot_image); static DEVICE_ATTR_WO(notify); +static DEVICE_ATTR_RO(spt0_address); +static DEVICE_ATTR_RO(spt1_address); static struct attribute *rsu_attrs[] = { &dev_attr_current_image.attr, @@ -609,6 +689,8 @@ static struct attribute *rsu_attrs[] = { &dev_attr_dcmf3_status.attr, &dev_attr_reboot_image.attr, &dev_attr_notify.attr, + &dev_attr_spt0_address.attr, + &dev_attr_spt1_address.attr, NULL }; @@ -638,11 +720,13 @@ static int stratix10_rsu_probe(struct platform_device *pdev) priv->dcmf_version.dcmf1 = INVALID_DCMF_VERSION; priv->dcmf_version.dcmf2 = INVALID_DCMF_VERSION; priv->dcmf_version.dcmf3 = INVALID_DCMF_VERSION; - priv->max_retry = INVALID_RETRY_COUNTER; priv->dcmf_status.dcmf0 = INVALID_DCMF_STATUS; priv->dcmf_status.dcmf1 = INVALID_DCMF_STATUS; priv->dcmf_status.dcmf2 = INVALID_DCMF_STATUS; priv->dcmf_status.dcmf3 = INVALID_DCMF_STATUS; + priv->max_retry = INVALID_RETRY_COUNTER; + priv->spt0_address = INVALID_SPT_ADDRESS; + priv->spt1_address = INVALID_SPT_ADDRESS; mutex_init(&priv->lock); priv->chan = stratix10_svc_request_channel_byname(&priv->client, @@ -692,6 +776,20 @@ static int stratix10_rsu_probe(struct platform_device *pdev) stratix10_svc_free_channel(priv->chan); } + priv->get_spt_response_buf = + stratix10_svc_allocate_memory(priv->chan, RSU_GET_SPT_RESP_LEN); + + if (IS_ERR(priv->get_spt_response_buf)) { + dev_err(dev, "failed to allocate get spt buffer\n"); + } else { + ret = rsu_send_msg(priv, COMMAND_MBOX_SEND_CMD, + RSU_GET_SPT_CMD, rsu_get_spt_callback); + if (ret) { + dev_err(dev, "Error, getting SPT table %i\n", ret); + stratix10_svc_free_channel(priv->chan); + } + } + return ret; } diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-svc.c index 2d674126160f..c693da60e9a9 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -37,6 +37,7 @@ #define SVC_NUM_CHANNEL 3 #define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS 200 #define FPGA_CONFIG_STATUS_TIMEOUT_SEC 30 +#define BYTE_TO_WORD_SIZE 4 /* stratix10 service layer clients */ #define STRATIX10_RSU "stratix10-rsu" @@ -361,6 +362,13 @@ static void svc_thread_recv_status_ok(struct stratix10_svc_data *p_data, cb_data->kaddr2 = svc_pa_to_va(res.a2); cb_data->kaddr3 = &res.a3; break; + case COMMAND_MBOX_SEND_CMD: + cb_data->status = BIT(SVC_STATUS_OK); + cb_data->kaddr1 = &res.a1; + /* SDM return size in u8. Convert size to u32 word */ + res.a2 = res.a2 * BYTE_TO_WORD_SIZE; + cb_data->kaddr2 = &res.a2; + break; default: pr_warn("it shouldn't happen\n"); break; @@ -534,6 +542,15 @@ static int svc_normal_to_secure_thread(void *data) a1 = 0; a2 = 0; break; + case COMMAND_MBOX_SEND_CMD: + a0 = INTEL_SIP_SMC_MBOX_SEND_CMD; + a1 = pdata->arg[0]; + a2 = (unsigned long)pdata->paddr; + a3 = (unsigned long)pdata->size / BYTE_TO_WORD_SIZE; + a4 = pdata->arg[1]; + a5 = (unsigned long)pdata->paddr_output; + a6 = (unsigned long)pdata->size_output / BYTE_TO_WORD_SIZE; + break; default: pr_warn("it shouldn't happen\n"); break; @@ -597,6 +614,7 @@ static int svc_normal_to_secure_thread(void *data) case COMMAND_FCS_DATA_ENCRYPTION: case COMMAND_FCS_DATA_DECRYPTION: case COMMAND_FCS_RANDOM_NUMBER_GEN: + case COMMAND_MBOX_SEND_CMD: cbdata->status = BIT(SVC_STATUS_INVALID_PARAM); cbdata->kaddr1 = NULL; cbdata->kaddr2 = NULL; @@ -756,7 +774,7 @@ svc_create_memory_pool(struct platform_device *pdev, paddr = begin; size = end - begin; va = devm_memremap(dev, paddr, size, MEMREMAP_WC); - if (!va) { + if (IS_ERR(va)) { dev_err(dev, "fail to remap shared memory\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 0a00763b9f28..2f689ac4ba3a 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -276,4 +276,6 @@ config FPGA_MGR_LATTICE_SYSCONFIG_SPI FPGA manager driver support for Lattice FPGAs programming over slave SPI sysCONFIG interface. +source "drivers/fpga/tests/Kconfig" + endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 72e554b4d2f7..352a2612623e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -55,3 +55,6 @@ obj-$(CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000) += dfl-n3000-nios.o # Drivers for FPGAs which implement DFL obj-$(CONFIG_FPGA_DFL_PCI) += dfl-pci.o + +# KUnit tests +obj-$(CONFIG_FPGA_KUNIT_TESTS) += tests/ diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c index ff3a646fd9e3..1fa2ccc321ab 100644 --- a/drivers/fpga/altera-fpga2sdram.c +++ b/drivers/fpga/altera-fpga2sdram.c @@ -27,7 +27,7 @@ #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/regmap.h> #define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80 diff --git a/drivers/fpga/altera-freeze-bridge.c b/drivers/fpga/altera-freeze-bridge.c index 445f4b011167..0c3fb8226908 100644 --- a/drivers/fpga/altera-freeze-bridge.c +++ b/drivers/fpga/altera-freeze-bridge.c @@ -7,8 +7,9 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/kernel.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> +#include <linux/platform_device.h> #include <linux/fpga/fpga-bridge.h> #define FREEZE_CSR_STATUS_OFFSET 0 @@ -198,13 +199,11 @@ static const struct fpga_bridge_ops altera_freeze_br_br_ops = { .enable_show = altera_freeze_br_enable_show, }; -#ifdef CONFIG_OF static const struct of_device_id altera_freeze_br_of_match[] = { { .compatible = "altr,freeze-bridge-controller", }, {}, }; MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match); -#endif static int altera_freeze_br_probe(struct platform_device *pdev) { @@ -213,14 +212,12 @@ static int altera_freeze_br_probe(struct platform_device *pdev) void __iomem *base_addr; struct altera_freeze_br_data *priv; struct fpga_bridge *br; - struct resource *res; u32 status, revision; if (!np) return -ENODEV; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base_addr = devm_ioremap_resource(dev, res); + base_addr = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base_addr)) return PTR_ERR(base_addr); @@ -270,7 +267,7 @@ static struct platform_driver altera_freeze_br_driver = { .remove = altera_freeze_br_remove, .driver = { .name = "altera_freeze_br", - .of_match_table = of_match_ptr(altera_freeze_br_of_match), + .of_match_table = altera_freeze_br_of_match, }, }; diff --git a/drivers/fpga/altera-pr-ip-core-plat.c b/drivers/fpga/altera-pr-ip-core-plat.c index b008a6b8d2d3..9dc263930007 100644 --- a/drivers/fpga/altera-pr-ip-core-plat.c +++ b/drivers/fpga/altera-pr-ip-core-plat.c @@ -9,19 +9,16 @@ */ #include <linux/fpga/altera-pr-ip-core.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> static int alt_pr_platform_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; void __iomem *reg_base; - struct resource *res; /* First mmio base is for register access */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - reg_base = devm_ioremap_resource(dev, res); - + reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(reg_base)) return PTR_ERR(reg_base); diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index bcb5d34b3b82..3dcf990bd261 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -19,6 +19,7 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/uaccess.h> +#include <linux/units.h> #include <linux/fpga-dfl.h> #include "dfl.h" @@ -231,19 +232,19 @@ static int thermal_hwmon_read(struct device *dev, enum hwmon_sensor_types type, switch (attr) { case hwmon_temp_input: v = readq(feature->ioaddr + FME_THERM_RDSENSOR_FMT1); - *val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * 1000); + *val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * MILLI); break; case hwmon_temp_max: v = readq(feature->ioaddr + FME_THERM_THRESHOLD); - *val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * 1000); + *val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * MILLI); break; case hwmon_temp_crit: v = readq(feature->ioaddr + FME_THERM_THRESHOLD); - *val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * 1000); + *val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * MILLI); break; case hwmon_temp_emergency: v = readq(feature->ioaddr + FME_THERM_THRESHOLD); - *val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * 1000); + *val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * MILLI); break; case hwmon_temp_max_alarm: v = readq(feature->ioaddr + FME_THERM_THRESHOLD); @@ -382,15 +383,15 @@ static int power_hwmon_read(struct device *dev, enum hwmon_sensor_types type, switch (attr) { case hwmon_power_input: v = readq(feature->ioaddr + FME_PWR_STATUS); - *val = (long)(FIELD_GET(PWR_CONSUMED, v) * 1000000); + *val = (long)(FIELD_GET(PWR_CONSUMED, v) * MICRO); break; case hwmon_power_max: v = readq(feature->ioaddr + FME_PWR_THRESHOLD); - *val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * 1000000); + *val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * MICRO); break; case hwmon_power_crit: v = readq(feature->ioaddr + FME_PWR_THRESHOLD); - *val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * 1000000); + *val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * MICRO); break; case hwmon_power_max_alarm: v = readq(feature->ioaddr + FME_PWR_THRESHOLD); @@ -415,7 +416,7 @@ static int power_hwmon_write(struct device *dev, enum hwmon_sensor_types type, int ret = 0; u64 v; - val = clamp_val(val / 1000000, 0, PWR_THRESHOLD_MAX); + val = clamp_val(val / MICRO, 0, PWR_THRESHOLD_MAX); mutex_lock(&pdata->lock); diff --git a/drivers/fpga/dfl-fme-mgr.c b/drivers/fpga/dfl-fme-mgr.c index af0785783b52..ab228d8837a0 100644 --- a/drivers/fpga/dfl-fme-mgr.c +++ b/drivers/fpga/dfl-fme-mgr.c @@ -280,7 +280,6 @@ static int fme_mgr_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct fme_mgr_priv *priv; struct fpga_manager *mgr; - struct resource *res; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -290,8 +289,7 @@ static int fme_mgr_probe(struct platform_device *pdev) priv->ioaddr = pdata->ioaddr; if (!priv->ioaddr) { - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->ioaddr = devm_ioremap_resource(dev, res); + priv->ioaddr = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->ioaddr)) return PTR_ERR(priv->ioaddr); } diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index 1bc04378118c..98b8fd16183e 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -156,19 +156,12 @@ static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec) static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info) { - u32 bir, offset, vndr_hdr, dfl_cnt, dfl_res; - int dfl_res_off, i, bars, voff = 0; + u32 bir, offset, dfl_cnt, dfl_res; + int dfl_res_off, i, bars, voff; resource_size_t start, len; - while ((voff = pci_find_next_ext_capability(pcidev, voff, PCI_EXT_CAP_ID_VNDR))) { - vndr_hdr = 0; - pci_read_config_dword(pcidev, voff + PCI_VNDR_HEADER, &vndr_hdr); - - if (PCI_VNDR_HEADER_ID(vndr_hdr) == PCI_VSEC_ID_INTEL_DFLS && - pcidev->vendor == PCI_VENDOR_ID_INTEL) - break; - } - + voff = pci_find_vsec_capability(pcidev, PCI_VENDOR_ID_INTEL, + PCI_VSEC_ID_INTEL_DFLS); if (!voff) { dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__); return -ENODEV; diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index a6c25dee9cc1..a024be2b84e2 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -14,7 +14,7 @@ #include <linux/spinlock.h> static DEFINE_IDA(fpga_bridge_ida); -static struct class *fpga_bridge_class; +static const struct class fpga_bridge_class; /* Lock for adding/removing bridges to linked lists*/ static DEFINE_SPINLOCK(bridge_list_lock); @@ -87,19 +87,20 @@ err_dev: /** * of_fpga_bridge_get - get an exclusive reference to an fpga bridge * - * @np: node pointer of an FPGA bridge - * @info: fpga image specific information + * @np: node pointer of an FPGA bridge. + * @info: fpga image specific information. * - * Return fpga_bridge struct if successful. - * Return -EBUSY if someone already has a reference to the bridge. - * Return -ENODEV if @np is not an FPGA Bridge. + * Return: + * * fpga_bridge struct pointer if successful. + * * -EBUSY if someone already has a reference to the bridge. + * * -ENODEV if @np is not an FPGA Bridge or can't take parent driver refcount. */ struct fpga_bridge *of_fpga_bridge_get(struct device_node *np, struct fpga_image_info *info) { struct device *dev; - dev = class_find_device_by_of_node(fpga_bridge_class, np); + dev = class_find_device_by_of_node(&fpga_bridge_class, np); if (!dev) return ERR_PTR(-ENODEV); @@ -126,7 +127,7 @@ struct fpga_bridge *fpga_bridge_get(struct device *dev, { struct device *bridge_dev; - bridge_dev = class_find_device(fpga_bridge_class, NULL, dev, + bridge_dev = class_find_device(&fpga_bridge_class, NULL, dev, fpga_bridge_dev_match); if (!bridge_dev) return ERR_PTR(-ENODEV); @@ -155,9 +156,9 @@ EXPORT_SYMBOL_GPL(fpga_bridge_put); * fpga_bridges_enable - enable bridges in a list * @bridge_list: list of FPGA bridges * - * Enable each bridge in the list. If list is empty, do nothing. + * Enable each bridge in the list. If list is empty, do nothing. * - * Return 0 for success or empty bridge list; return error code otherwise. + * Return: 0 for success or empty bridge list or an error code otherwise. */ int fpga_bridges_enable(struct list_head *bridge_list) { @@ -179,9 +180,9 @@ EXPORT_SYMBOL_GPL(fpga_bridges_enable); * * @bridge_list: list of FPGA bridges * - * Disable each bridge in the list. If list is empty, do nothing. + * Disable each bridge in the list. If list is empty, do nothing. * - * Return 0 for success or empty bridge list; return error code otherwise. + * Return: 0 for success or empty bridge list or an error code otherwise. */ int fpga_bridges_disable(struct list_head *bridge_list) { @@ -230,7 +231,7 @@ EXPORT_SYMBOL_GPL(fpga_bridges_put); * * Get an exclusive reference to the bridge and it to the list. * - * Return 0 for success, error code from of_fpga_bridge_get() otherwise. + * Return: 0 for success, error code from of_fpga_bridge_get() otherwise. */ int of_fpga_bridge_get_to_list(struct device_node *np, struct fpga_image_info *info, @@ -260,7 +261,7 @@ EXPORT_SYMBOL_GPL(of_fpga_bridge_get_to_list); * * Get an exclusive reference to the bridge and it to the list. * - * Return 0 for success, error code from fpga_bridge_get() otherwise. + * Return: 0 for success, error code from fpga_bridge_get() otherwise. */ int fpga_bridge_get_to_list(struct device *dev, struct fpga_image_info *info, @@ -359,7 +360,7 @@ fpga_bridge_register(struct device *parent, const char *name, bridge->priv = priv; bridge->dev.groups = br_ops->groups; - bridge->dev.class = fpga_bridge_class; + bridge->dev.class = &fpga_bridge_class; bridge->dev.parent = parent; bridge->dev.of_node = parent->of_node; bridge->dev.id = id; @@ -415,21 +416,20 @@ static void fpga_bridge_dev_release(struct device *dev) kfree(bridge); } +static const struct class fpga_bridge_class = { + .name = "fpga_bridge", + .dev_groups = fpga_bridge_groups, + .dev_release = fpga_bridge_dev_release, +}; + static int __init fpga_bridge_dev_init(void) { - fpga_bridge_class = class_create("fpga_bridge"); - if (IS_ERR(fpga_bridge_class)) - return PTR_ERR(fpga_bridge_class); - - fpga_bridge_class->dev_groups = fpga_bridge_groups; - fpga_bridge_class->dev_release = fpga_bridge_dev_release; - - return 0; + return class_register(&fpga_bridge_class); } static void __exit fpga_bridge_dev_exit(void) { - class_destroy(fpga_bridge_class); + class_unregister(&fpga_bridge_class); ida_destroy(&fpga_bridge_ida); } diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index eb583f86a0b9..06651389c592 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -19,7 +19,7 @@ #include <linux/highmem.h> static DEFINE_IDA(fpga_mgr_ida); -static struct class *fpga_mgr_class; +static const struct class fpga_mgr_class; struct fpga_mgr_devres { struct fpga_manager *mgr; @@ -693,7 +693,7 @@ static int fpga_mgr_dev_match(struct device *dev, const void *data) */ struct fpga_manager *fpga_mgr_get(struct device *dev) { - struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev, + struct device *mgr_dev = class_find_device(&fpga_mgr_class, NULL, dev, fpga_mgr_dev_match); if (!mgr_dev) return ERR_PTR(-ENODEV); @@ -713,7 +713,7 @@ struct fpga_manager *of_fpga_mgr_get(struct device_node *node) { struct device *dev; - dev = class_find_device_by_of_node(fpga_mgr_class, node); + dev = class_find_device_by_of_node(&fpga_mgr_class, node); if (!dev) return ERR_PTR(-ENODEV); @@ -809,7 +809,7 @@ fpga_mgr_register_full(struct device *parent, const struct fpga_manager_info *in mgr->priv = info->priv; mgr->compat_id = info->compat_id; - mgr->dev.class = fpga_mgr_class; + mgr->dev.class = &fpga_mgr_class; mgr->dev.groups = mops->groups; mgr->dev.parent = parent; mgr->dev.of_node = parent->of_node; @@ -967,23 +967,22 @@ static void fpga_mgr_dev_release(struct device *dev) kfree(mgr); } +static const struct class fpga_mgr_class = { + .name = "fpga_manager", + .dev_groups = fpga_mgr_groups, + .dev_release = fpga_mgr_dev_release, +}; + static int __init fpga_mgr_class_init(void) { pr_info("FPGA manager framework\n"); - fpga_mgr_class = class_create("fpga_manager"); - if (IS_ERR(fpga_mgr_class)) - return PTR_ERR(fpga_mgr_class); - - fpga_mgr_class->dev_groups = fpga_mgr_groups; - fpga_mgr_class->dev_release = fpga_mgr_dev_release; - - return 0; + return class_register(&fpga_mgr_class); } static void __exit fpga_mgr_class_exit(void) { - class_destroy(fpga_mgr_class); + class_unregister(&fpga_mgr_class); ida_destroy(&fpga_mgr_ida); } diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c index ccf6fdab1360..b364a929425c 100644 --- a/drivers/fpga/fpga-region.c +++ b/drivers/fpga/fpga-region.c @@ -16,7 +16,7 @@ #include <linux/spinlock.h> static DEFINE_IDA(fpga_region_ida); -static struct class *fpga_region_class; +static const struct class fpga_region_class; struct fpga_region * fpga_region_class_find(struct device *start, const void *data, @@ -24,7 +24,7 @@ fpga_region_class_find(struct device *start, const void *data, { struct device *dev; - dev = class_find_device(fpga_region_class, start, data, match); + dev = class_find_device(&fpga_region_class, start, data, match); if (!dev) return NULL; @@ -38,9 +38,10 @@ EXPORT_SYMBOL_GPL(fpga_region_class_find); * * Caller should call fpga_region_put() when done with region. * - * Return fpga_region struct if successful. - * Return -EBUSY if someone already has a reference to the region. - * Return -ENODEV if @np is not an FPGA Region. + * Return: + * * fpga_region struct if successful. + * * -EBUSY if someone already has a reference to the region. + * * -ENODEV if can't take parent driver module refcount. */ static struct fpga_region *fpga_region_get(struct fpga_region *region) { @@ -91,7 +92,7 @@ static void fpga_region_put(struct fpga_region *region) * The caller will need to call fpga_bridges_put() before attempting to * reprogram the region. * - * Return 0 for success or negative error code. + * Return: 0 for success or negative error code. */ int fpga_region_program_fpga(struct fpga_region *region) { @@ -216,7 +217,7 @@ fpga_region_register_full(struct device *parent, const struct fpga_region_info * mutex_init(®ion->mutex); INIT_LIST_HEAD(®ion->bridge_list); - region->dev.class = fpga_region_class; + region->dev.class = &fpga_region_class; region->dev.parent = parent; region->dev.of_node = parent->of_node; region->dev.id = id; @@ -287,25 +288,25 @@ static void fpga_region_dev_release(struct device *dev) kfree(region); } +static const struct class fpga_region_class = { + .name = "fpga_region", + .dev_groups = fpga_region_groups, + .dev_release = fpga_region_dev_release, +}; + /** - * fpga_region_init - init function for fpga_region class - * Creates the fpga_region class and registers a reconfig notifier. + * fpga_region_init - creates the fpga_region class. + * + * Return: 0 on success or ERR_PTR() on error. */ static int __init fpga_region_init(void) { - fpga_region_class = class_create("fpga_region"); - if (IS_ERR(fpga_region_class)) - return PTR_ERR(fpga_region_class); - - fpga_region_class->dev_groups = fpga_region_groups; - fpga_region_class->dev_release = fpga_region_dev_release; - - return 0; + return class_register(&fpga_region_class); } static void __exit fpga_region_exit(void) { - class_destroy(fpga_region_class); + class_unregister(&fpga_region_class); ida_destroy(&fpga_region_ida); } diff --git a/drivers/fpga/microchip-spi.c b/drivers/fpga/microchip-spi.c index d6070e7f5205..2a82c726d6e5 100644 --- a/drivers/fpga/microchip-spi.c +++ b/drivers/fpga/microchip-spi.c @@ -8,7 +8,7 @@ #include <linux/fpga/fpga-mgr.h> #include <linux/iopoll.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/spi/spi.h> #define MPF_SPI_ISC_ENABLE 0x0B diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c index ae82532fc127..a6affd83f275 100644 --- a/drivers/fpga/of-fpga-region.c +++ b/drivers/fpga/of-fpga-region.c @@ -12,7 +12,9 @@ #include <linux/kernel.h> #include <linux/list.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/of_platform.h> +#include <linux/platform_device.h> #include <linux/slab.h> #include <linux/spinlock.h> diff --git a/drivers/fpga/socfpga-a10.c b/drivers/fpga/socfpga-a10.c index ac8e89b8a5cc..cc4861e345c9 100644 --- a/drivers/fpga/socfpga-a10.c +++ b/drivers/fpga/socfpga-a10.c @@ -471,7 +471,6 @@ static int socfpga_a10_fpga_probe(struct platform_device *pdev) struct a10_fpga_priv *priv; void __iomem *reg_base; struct fpga_manager *mgr; - struct resource *res; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -479,14 +478,12 @@ static int socfpga_a10_fpga_probe(struct platform_device *pdev) return -ENOMEM; /* First mmio base is for register access */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - reg_base = devm_ioremap_resource(dev, res); + reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(reg_base)) return PTR_ERR(reg_base); /* Second mmio base is for writing FPGA image data */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - priv->fpga_data_addr = devm_ioremap_resource(dev, res); + priv->fpga_data_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(priv->fpga_data_addr)) return PTR_ERR(priv->fpga_data_addr); diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 7e0741f99696..723ea0ad3f09 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -545,20 +545,17 @@ static int socfpga_fpga_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct socfpga_fpga_priv *priv; struct fpga_manager *mgr; - struct resource *res; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->fpga_base_addr = devm_ioremap_resource(dev, res); + priv->fpga_base_addr = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->fpga_base_addr)) return PTR_ERR(priv->fpga_base_addr); - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - priv->fpga_data_addr = devm_ioremap_resource(dev, res); + priv->fpga_data_addr = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(priv->fpga_data_addr)) return PTR_ERR(priv->fpga_data_addr); diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index f7f01982a512..cacb9cc5757e 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -10,6 +10,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_platform.h> +#include <linux/platform_device.h> /* * FPGA programming requires a higher level of privilege (EL3), per the SoC diff --git a/drivers/fpga/tests/.kunitconfig b/drivers/fpga/tests/.kunitconfig new file mode 100644 index 000000000000..a1c2a2974c39 --- /dev/null +++ b/drivers/fpga/tests/.kunitconfig @@ -0,0 +1,5 @@ +CONFIG_KUNIT=y +CONFIG_FPGA=y +CONFIG_FPGA_REGION=y +CONFIG_FPGA_BRIDGE=y +CONFIG_FPGA_KUNIT_TESTS=y diff --git a/drivers/fpga/tests/Kconfig b/drivers/fpga/tests/Kconfig new file mode 100644 index 000000000000..e4a64815f16d --- /dev/null +++ b/drivers/fpga/tests/Kconfig @@ -0,0 +1,11 @@ +config FPGA_KUNIT_TESTS + tristate "KUnit test for the FPGA subsystem" if !KUNIT_ALL_TESTS + depends on FPGA && FPGA_REGION && FPGA_BRIDGE && KUNIT=y + default KUNIT_ALL_TESTS + help + This builds unit tests for the FPGA subsystem + + For more information on KUnit and unit tests in general, + please refer to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. diff --git a/drivers/fpga/tests/Makefile b/drivers/fpga/tests/Makefile new file mode 100644 index 000000000000..bb78215c645c --- /dev/null +++ b/drivers/fpga/tests/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for KUnit test suites for the FPGA subsystem +# + +obj-$(CONFIG_FPGA_KUNIT_TESTS) += fpga-mgr-test.o fpga-bridge-test.o fpga-region-test.o diff --git a/drivers/fpga/tests/fpga-bridge-test.c b/drivers/fpga/tests/fpga-bridge-test.c new file mode 100644 index 000000000000..1d258002cdd7 --- /dev/null +++ b/drivers/fpga/tests/fpga-bridge-test.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Bridge + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani <marpagan@redhat.com> + */ + +#include <kunit/test.h> +#include <linux/device.h> +#include <linux/fpga/fpga-bridge.h> +#include <linux/module.h> +#include <linux/types.h> + +struct bridge_stats { + bool enable; +}; + +struct bridge_ctx { + struct fpga_bridge *bridge; + struct platform_device *pdev; + struct bridge_stats stats; +}; + +static int op_enable_set(struct fpga_bridge *bridge, bool enable) +{ + struct bridge_stats *stats = bridge->priv; + + stats->enable = enable; + + return 0; +} + +/* + * Fake FPGA bridge that implements only the enable_set op to track + * the state. + */ +static const struct fpga_bridge_ops fake_bridge_ops = { + .enable_set = op_enable_set, +}; + +/** + * register_test_bridge() - Register a fake FPGA bridge for testing. + * @test: KUnit test context object. + * + * Return: Context of the newly registered FPGA bridge. + */ +static struct bridge_ctx *register_test_bridge(struct kunit *test) +{ + struct bridge_ctx *ctx; + + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->pdev = platform_device_register_simple("bridge_pdev", PLATFORM_DEVID_AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev); + + ctx->bridge = fpga_bridge_register(&ctx->pdev->dev, "Fake FPGA bridge", &fake_bridge_ops, + &ctx->stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); + + return ctx; +} + +static void unregister_test_bridge(struct bridge_ctx *ctx) +{ + fpga_bridge_unregister(ctx->bridge); + platform_device_unregister(ctx->pdev); +} + +static void fpga_bridge_test_get(struct kunit *test) +{ + struct bridge_ctx *ctx = test->priv; + struct fpga_bridge *bridge; + + bridge = fpga_bridge_get(&ctx->pdev->dev, NULL); + KUNIT_EXPECT_PTR_EQ(test, bridge, ctx->bridge); + + bridge = fpga_bridge_get(&ctx->pdev->dev, NULL); + KUNIT_EXPECT_EQ(test, PTR_ERR(bridge), -EBUSY); + + fpga_bridge_put(ctx->bridge); +} + +static void fpga_bridge_test_toggle(struct kunit *test) +{ + struct bridge_ctx *ctx = test->priv; + int ret; + + ret = fpga_bridge_disable(ctx->bridge); + KUNIT_EXPECT_EQ(test, ret, 0); + KUNIT_EXPECT_FALSE(test, ctx->stats.enable); + + ret = fpga_bridge_enable(ctx->bridge); + KUNIT_EXPECT_EQ(test, ret, 0); + KUNIT_EXPECT_TRUE(test, ctx->stats.enable); +} + +/* Test the functions for getting and controlling a list of bridges */ +static void fpga_bridge_test_get_put_list(struct kunit *test) +{ + struct list_head bridge_list; + struct bridge_ctx *ctx_0, *ctx_1; + int ret; + + ctx_0 = test->priv; + ctx_1 = register_test_bridge(test); + + INIT_LIST_HEAD(&bridge_list); + + /* Get bridge 0 and add it to the list */ + ret = fpga_bridge_get_to_list(&ctx_0->pdev->dev, NULL, &bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_PTR_EQ(test, ctx_0->bridge, + list_first_entry_or_null(&bridge_list, struct fpga_bridge, node)); + + /* Get bridge 1 and add it to the list */ + ret = fpga_bridge_get_to_list(&ctx_1->pdev->dev, NULL, &bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_PTR_EQ(test, ctx_1->bridge, + list_first_entry_or_null(&bridge_list, struct fpga_bridge, node)); + + /* Disable an then enable both bridges from the list */ + ret = fpga_bridges_disable(&bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_FALSE(test, ctx_0->stats.enable); + KUNIT_EXPECT_FALSE(test, ctx_1->stats.enable); + + ret = fpga_bridges_enable(&bridge_list); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx_0->stats.enable); + KUNIT_EXPECT_TRUE(test, ctx_1->stats.enable); + + /* Put and remove both bridges from the list */ + fpga_bridges_put(&bridge_list); + + KUNIT_EXPECT_TRUE(test, list_empty(&bridge_list)); + + unregister_test_bridge(ctx_1); +} + +static int fpga_bridge_test_init(struct kunit *test) +{ + test->priv = register_test_bridge(test); + + return 0; +} + +static void fpga_bridge_test_exit(struct kunit *test) +{ + unregister_test_bridge(test->priv); +} + +static struct kunit_case fpga_bridge_test_cases[] = { + KUNIT_CASE(fpga_bridge_test_get), + KUNIT_CASE(fpga_bridge_test_toggle), + KUNIT_CASE(fpga_bridge_test_get_put_list), + {} +}; + +static struct kunit_suite fpga_bridge_suite = { + .name = "fpga_bridge", + .init = fpga_bridge_test_init, + .exit = fpga_bridge_test_exit, + .test_cases = fpga_bridge_test_cases, +}; + +kunit_test_suite(fpga_bridge_suite); + +MODULE_LICENSE("GPL"); diff --git a/drivers/fpga/tests/fpga-mgr-test.c b/drivers/fpga/tests/fpga-mgr-test.c new file mode 100644 index 000000000000..6acec55b60ce --- /dev/null +++ b/drivers/fpga/tests/fpga-mgr-test.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Manager + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani <marpagan@redhat.com> + */ + +#include <kunit/test.h> +#include <linux/device.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/module.h> +#include <linux/scatterlist.h> +#include <linux/types.h> + +#define HEADER_FILL 'H' +#define IMAGE_FILL 'P' +#define IMAGE_BLOCK 1024 + +#define HEADER_SIZE IMAGE_BLOCK +#define IMAGE_SIZE (IMAGE_BLOCK * 4) + +struct mgr_stats { + bool header_match; + bool image_match; + u32 seq_num; + u32 op_parse_header_seq; + u32 op_write_init_seq; + u32 op_write_seq; + u32 op_write_sg_seq; + u32 op_write_complete_seq; + enum fpga_mgr_states op_parse_header_state; + enum fpga_mgr_states op_write_init_state; + enum fpga_mgr_states op_write_state; + enum fpga_mgr_states op_write_sg_state; + enum fpga_mgr_states op_write_complete_state; +}; + +struct mgr_ctx { + struct fpga_image_info *img_info; + struct fpga_manager *mgr; + struct platform_device *pdev; + struct mgr_stats stats; +}; + +/** + * init_test_buffer() - Allocate and initialize a test image in a buffer. + * @test: KUnit test context object. + * @count: image size in bytes. + * + * Return: pointer to the newly allocated image. + */ +static char *init_test_buffer(struct kunit *test, size_t count) +{ + char *buf; + + KUNIT_ASSERT_GE(test, count, HEADER_SIZE); + + buf = kunit_kzalloc(test, count, GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, buf); + + memset(buf, HEADER_FILL, HEADER_SIZE); + memset(buf + HEADER_SIZE, IMAGE_FILL, count - HEADER_SIZE); + + return buf; +} + +/* + * Check the image header. Do not return an error code if the image check fails + * since, in this case, it is a failure of the FPGA manager itself, not this + * op that tests it. + */ +static int op_parse_header(struct fpga_manager *mgr, struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct mgr_stats *stats = mgr->priv; + size_t i; + + stats->op_parse_header_state = mgr->state; + stats->op_parse_header_seq = stats->seq_num++; + + /* Set header_size and data_size for later */ + info->header_size = HEADER_SIZE; + info->data_size = info->count - HEADER_SIZE; + + stats->header_match = true; + for (i = 0; i < info->header_size; i++) { + if (buf[i] != HEADER_FILL) { + stats->header_match = false; + break; + } + } + + return 0; +} + +static int op_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct mgr_stats *stats = mgr->priv; + + stats->op_write_init_state = mgr->state; + stats->op_write_init_seq = stats->seq_num++; + + return 0; +} + +/* + * Check the image data. As with op_parse_header, do not return an error code + * if the image check fails. + */ +static int op_write(struct fpga_manager *mgr, const char *buf, size_t count) +{ + struct mgr_stats *stats = mgr->priv; + size_t i; + + stats->op_write_state = mgr->state; + stats->op_write_seq = stats->seq_num++; + + stats->image_match = true; + for (i = 0; i < count; i++) { + if (buf[i] != IMAGE_FILL) { + stats->image_match = false; + break; + } + } + + return 0; +} + +/* + * Check the image data, but first skip the header since write_sg will get + * the whole image in sg_table. As with op_parse_header, do not return an + * error code if the image check fails. + */ +static int op_write_sg(struct fpga_manager *mgr, struct sg_table *sgt) +{ + struct mgr_stats *stats = mgr->priv; + struct sg_mapping_iter miter; + char *img; + size_t i; + + stats->op_write_sg_state = mgr->state; + stats->op_write_sg_seq = stats->seq_num++; + + stats->image_match = true; + sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); + + if (!sg_miter_skip(&miter, HEADER_SIZE)) { + stats->image_match = false; + goto out; + } + + while (sg_miter_next(&miter)) { + img = miter.addr; + for (i = 0; i < miter.length; i++) { + if (img[i] != IMAGE_FILL) { + stats->image_match = false; + goto out; + } + } + } +out: + sg_miter_stop(&miter); + return 0; +} + +static int op_write_complete(struct fpga_manager *mgr, struct fpga_image_info *info) +{ + struct mgr_stats *stats = mgr->priv; + + stats->op_write_complete_state = mgr->state; + stats->op_write_complete_seq = stats->seq_num++; + + return 0; +} + +/* + * Fake FPGA manager that implements all ops required to check the programming + * sequence using a single contiguous buffer and a scatter gather table. + */ +static const struct fpga_manager_ops fake_mgr_ops = { + .skip_header = true, + .parse_header = op_parse_header, + .write_init = op_write_init, + .write = op_write, + .write_sg = op_write_sg, + .write_complete = op_write_complete, +}; + +static void fpga_mgr_test_get(struct kunit *test) +{ + struct mgr_ctx *ctx = test->priv; + struct fpga_manager *mgr; + + mgr = fpga_mgr_get(&ctx->pdev->dev); + KUNIT_EXPECT_PTR_EQ(test, mgr, ctx->mgr); + + fpga_mgr_put(ctx->mgr); +} + +static void fpga_mgr_test_lock(struct kunit *test) +{ + struct mgr_ctx *ctx = test->priv; + int ret; + + ret = fpga_mgr_lock(ctx->mgr); + KUNIT_EXPECT_EQ(test, ret, 0); + + ret = fpga_mgr_lock(ctx->mgr); + KUNIT_EXPECT_EQ(test, ret, -EBUSY); + + fpga_mgr_unlock(ctx->mgr); +} + +/* Check the programming sequence using an image in a buffer */ +static void fpga_mgr_test_img_load_buf(struct kunit *test) +{ + struct mgr_ctx *ctx = test->priv; + char *img_buf; + int ret; + + img_buf = init_test_buffer(test, IMAGE_SIZE); + + ctx->img_info->count = IMAGE_SIZE; + ctx->img_info->buf = img_buf; + + ret = fpga_mgr_load(ctx->mgr, ctx->img_info); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_state, FPGA_MGR_STATE_WRITE); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_seq, ctx->stats.op_parse_header_seq + 2); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3); +} + +/* Check the programming sequence using an image in a scatter gather table */ +static void fpga_mgr_test_img_load_sgt(struct kunit *test) +{ + struct mgr_ctx *ctx = test->priv; + struct sg_table *sgt; + char *img_buf; + int ret; + + img_buf = init_test_buffer(test, IMAGE_SIZE); + + sgt = kunit_kzalloc(test, sizeof(*sgt), GFP_KERNEL); + ret = sg_alloc_table(sgt, 1, GFP_KERNEL); + KUNIT_ASSERT_EQ(test, ret, 0); + sg_init_one(sgt->sgl, img_buf, IMAGE_SIZE); + + ctx->img_info->sgt = sgt; + + ret = fpga_mgr_load(ctx->mgr, ctx->img_info); + KUNIT_EXPECT_EQ(test, ret, 0); + + KUNIT_EXPECT_TRUE(test, ctx->stats.header_match); + KUNIT_EXPECT_TRUE(test, ctx->stats.image_match); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_parse_header_state, FPGA_MGR_STATE_PARSE_HEADER); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_state, FPGA_MGR_STATE_WRITE_INIT); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_state, FPGA_MGR_STATE_WRITE); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_state, FPGA_MGR_STATE_WRITE_COMPLETE); + + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_init_seq, ctx->stats.op_parse_header_seq + 1); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_sg_seq, ctx->stats.op_parse_header_seq + 2); + KUNIT_EXPECT_EQ(test, ctx->stats.op_write_complete_seq, ctx->stats.op_parse_header_seq + 3); + + sg_free_table(ctx->img_info->sgt); +} + +static int fpga_mgr_test_init(struct kunit *test) +{ + struct mgr_ctx *ctx; + + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->pdev); + + ctx->mgr = devm_fpga_mgr_register(&ctx->pdev->dev, "Fake FPGA Manager", &fake_mgr_ops, + &ctx->stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); + + ctx->img_info = fpga_image_info_alloc(&ctx->pdev->dev); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->img_info); + + test->priv = ctx; + + return 0; +} + +static void fpga_mgr_test_exit(struct kunit *test) +{ + struct mgr_ctx *ctx = test->priv; + + fpga_image_info_free(ctx->img_info); + platform_device_unregister(ctx->pdev); +} + +static struct kunit_case fpga_mgr_test_cases[] = { + KUNIT_CASE(fpga_mgr_test_get), + KUNIT_CASE(fpga_mgr_test_lock), + KUNIT_CASE(fpga_mgr_test_img_load_buf), + KUNIT_CASE(fpga_mgr_test_img_load_sgt), + {} +}; + +static struct kunit_suite fpga_mgr_suite = { + .name = "fpga_mgr", + .init = fpga_mgr_test_init, + .exit = fpga_mgr_test_exit, + .test_cases = fpga_mgr_test_cases, +}; + +kunit_test_suite(fpga_mgr_suite); + +MODULE_LICENSE("GPL"); diff --git a/drivers/fpga/tests/fpga-region-test.c b/drivers/fpga/tests/fpga-region-test.c new file mode 100644 index 000000000000..9f9d50ee7871 --- /dev/null +++ b/drivers/fpga/tests/fpga-region-test.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit test for the FPGA Region + * + * Copyright (C) 2023 Red Hat, Inc. + * + * Author: Marco Pagani <marpagan@redhat.com> + */ + +#include <kunit/test.h> +#include <linux/fpga/fpga-bridge.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/fpga/fpga-region.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +struct mgr_stats { + u32 write_count; +}; + +struct bridge_stats { + bool enable; + u32 cycles_count; +}; + +struct test_ctx { + struct fpga_manager *mgr; + struct platform_device *mgr_pdev; + struct fpga_bridge *bridge; + struct platform_device *bridge_pdev; + struct fpga_region *region; + struct platform_device *region_pdev; + struct bridge_stats bridge_stats; + struct mgr_stats mgr_stats; +}; + +static int op_write(struct fpga_manager *mgr, const char *buf, size_t count) +{ + struct mgr_stats *stats = mgr->priv; + + stats->write_count++; + + return 0; +} + +/* + * Fake FPGA manager that implements only the write op to count the number + * of programming cycles. The internals of the programming sequence are + * tested in the Manager suite since they are outside the responsibility + * of the Region. + */ +static const struct fpga_manager_ops fake_mgr_ops = { + .write = op_write, +}; + +static int op_enable_set(struct fpga_bridge *bridge, bool enable) +{ + struct bridge_stats *stats = bridge->priv; + + if (!stats->enable && enable) + stats->cycles_count++; + + stats->enable = enable; + + return 0; +} + +/* + * Fake FPGA bridge that implements only enable_set op to count the number + * of activation cycles. + */ +static const struct fpga_bridge_ops fake_bridge_ops = { + .enable_set = op_enable_set, +}; + +static int fake_region_get_bridges(struct fpga_region *region) +{ + struct fpga_bridge *bridge = region->priv; + + return fpga_bridge_get_to_list(bridge->dev.parent, region->info, ®ion->bridge_list); +} + +static int fake_region_match(struct device *dev, const void *data) +{ + return dev->parent == data; +} + +static void fpga_region_test_class_find(struct kunit *test) +{ + struct test_ctx *ctx = test->priv; + struct fpga_region *region; + + region = fpga_region_class_find(NULL, &ctx->region_pdev->dev, fake_region_match); + KUNIT_EXPECT_PTR_EQ(test, region, ctx->region); +} + +/* + * FPGA Region programming test. The Region must call get_bridges() to get + * and control the bridges, and then the Manager for the actual programming. + */ +static void fpga_region_test_program_fpga(struct kunit *test) +{ + struct test_ctx *ctx = test->priv; + struct fpga_image_info *img_info; + char img_buf[4]; + int ret; + + img_info = fpga_image_info_alloc(&ctx->mgr_pdev->dev); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, img_info); + + img_info->buf = img_buf; + img_info->count = sizeof(img_buf); + + ctx->region->info = img_info; + ret = fpga_region_program_fpga(ctx->region); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, 1, ctx->mgr_stats.write_count); + KUNIT_EXPECT_EQ(test, 1, ctx->bridge_stats.cycles_count); + + fpga_bridges_put(&ctx->region->bridge_list); + + ret = fpga_region_program_fpga(ctx->region); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, 2, ctx->mgr_stats.write_count); + KUNIT_EXPECT_EQ(test, 2, ctx->bridge_stats.cycles_count); + + fpga_bridges_put(&ctx->region->bridge_list); + + fpga_image_info_free(img_info); +} + +/* + * The configuration used in this test suite uses a single bridge to + * limit the code under test to a single unit. The functions used by the + * Region for getting and controlling bridges are tested (with a list of + * multiple bridges) in the Bridge suite. + */ +static int fpga_region_test_init(struct kunit *test) +{ + struct test_ctx *ctx; + struct fpga_region_info region_info = { 0 }; + + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ctx->mgr_pdev = platform_device_register_simple("mgr_pdev", PLATFORM_DEVID_AUTO, NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->mgr_pdev); + + ctx->mgr = devm_fpga_mgr_register(&ctx->mgr_pdev->dev, "Fake FPGA Manager", &fake_mgr_ops, + &ctx->mgr_stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->mgr)); + + ctx->bridge_pdev = platform_device_register_simple("bridge_pdev", PLATFORM_DEVID_AUTO, + NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->bridge_pdev); + + ctx->bridge = fpga_bridge_register(&ctx->bridge_pdev->dev, "Fake FPGA Bridge", + &fake_bridge_ops, &ctx->bridge_stats); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->bridge)); + + ctx->bridge_stats.enable = true; + + ctx->region_pdev = platform_device_register_simple("region_pdev", PLATFORM_DEVID_AUTO, + NULL, 0); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->region_pdev); + + region_info.mgr = ctx->mgr; + region_info.priv = ctx->bridge; + region_info.get_bridges = fake_region_get_bridges; + + ctx->region = fpga_region_register_full(&ctx->region_pdev->dev, ®ion_info); + KUNIT_ASSERT_FALSE(test, IS_ERR_OR_NULL(ctx->region)); + + test->priv = ctx; + + return 0; +} + +static void fpga_region_test_exit(struct kunit *test) +{ + struct test_ctx *ctx = test->priv; + + fpga_region_unregister(ctx->region); + platform_device_unregister(ctx->region_pdev); + + fpga_bridge_unregister(ctx->bridge); + platform_device_unregister(ctx->bridge_pdev); + + platform_device_unregister(ctx->mgr_pdev); +} + +static struct kunit_case fpga_region_test_cases[] = { + KUNIT_CASE(fpga_region_test_class_find), + KUNIT_CASE(fpga_region_test_program_fpga), + + {} +}; + +static struct kunit_suite fpga_region_suite = { + .name = "fpga_mgr", + .init = fpga_region_test_init, + .exit = fpga_region_test_exit, + .test_cases = fpga_region_test_cases, +}; + +kunit_test_suite(fpga_region_suite); + +MODULE_LICENSE("GPL"); diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c index 8e6e9c840d9d..4e1d2a4d3df4 100644 --- a/drivers/fpga/ts73xx-fpga.c +++ b/drivers/fpga/ts73xx-fpga.c @@ -103,7 +103,6 @@ static int ts73xx_fpga_probe(struct platform_device *pdev) struct device *kdev = &pdev->dev; struct ts73xx_fpga_priv *priv; struct fpga_manager *mgr; - struct resource *res; priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -111,8 +110,7 @@ static int ts73xx_fpga_probe(struct platform_device *pdev) priv->dev = kdev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->io_base = devm_ioremap_resource(kdev, res); + priv->io_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->io_base)) return PTR_ERR(priv->io_base); diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c index b76d85449b8f..208d9560f56d 100644 --- a/drivers/fpga/xilinx-pr-decoupler.c +++ b/drivers/fpga/xilinx-pr-decoupler.c @@ -108,7 +108,6 @@ static int xlnx_pr_decoupler_probe(struct platform_device *pdev) struct xlnx_pr_decoupler_data *priv; struct fpga_bridge *br; int err; - struct resource *res; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -122,8 +121,7 @@ static int xlnx_pr_decoupler_probe(struct platform_device *pdev) priv->ipconfig = match->data; } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->io_base = devm_ioremap_resource(&pdev->dev, res); + priv->io_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->io_base)) return PTR_ERR(priv->io_base); diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index f8214cae9b6e..96611d424a10 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -555,7 +555,6 @@ static int zynq_fpga_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct zynq_fpga_priv *priv; struct fpga_manager *mgr; - struct resource *res; int err; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -563,8 +562,7 @@ static int zynq_fpga_probe(struct platform_device *pdev) return -ENOMEM; spin_lock_init(&priv->dma_lock); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->io_base = devm_ioremap_resource(dev, res); + priv->io_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->io_base)) return PTR_ERR(priv->io_base); diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index e6668a869913..79a31593618a 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -62,6 +62,15 @@ config FSI_MASTER_ASPEED Enable it for your BMC kernel in an OpenPower or IBM Power system. +config FSI_MASTER_I2CR + tristate "IBM I2C Responder virtual FSI master" + depends on I2C + help + This option enables a virtual FSI master in order to access a CFAM + behind an IBM I2C Responder (I2CR) chip. The I2CR is an I2C device + that translates I2C commands to CFAM or SCOM operations, effectively + implementing an FSI master and bus. + config FSI_SCOM tristate "SCOM FSI client device driver" help @@ -85,4 +94,12 @@ config FSI_OCC provide the raw sensor data as well as perform thermal and power management on the system. +config I2CR_SCOM + tristate "IBM I2C Responder SCOM driver" + depends on FSI_MASTER_I2CR + help + This option enables an I2C Responder based SCOM device driver. The + I2CR has the capability to directly perform SCOM operations instead + of using the FSI2PIB engine. + endif diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile index da218a1ad8e1..5550aa15e0b1 100644 --- a/drivers/fsi/Makefile +++ b/drivers/fsi/Makefile @@ -4,7 +4,9 @@ obj-$(CONFIG_FSI) += fsi-core.o obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o obj-$(CONFIG_FSI_MASTER_ASPEED) += fsi-master-aspeed.o obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o +obj-$(CONFIG_FSI_MASTER_I2CR) += fsi-master-i2cr.o obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o obj-$(CONFIG_FSI_SCOM) += fsi-scom.o obj-$(CONFIG_FSI_SBEFIFO) += fsi-sbefifo.o obj-$(CONFIG_FSI_OCC) += fsi-occ.o +obj-$(CONFIG_I2CR_SCOM) += i2cr-scom.o diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 0b927c9f4267..097d5a780264 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -16,6 +16,8 @@ #include <linux/idr.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> #include <linux/slab.h> #include <linux/bitops.h> #include <linux/cdev.h> @@ -23,6 +25,10 @@ #include <linux/uaccess.h> #include "fsi-master.h" +#include "fsi-slave.h" + +#define CREATE_TRACE_POINTS +#include <trace/events/fsi.h> #define FSI_SLAVE_CONF_NEXT_MASK GENMASK(31, 31) #define FSI_SLAVE_CONF_SLOTS_MASK GENMASK(23, 16) @@ -78,26 +84,6 @@ static const int engine_page_size = 0x400; static DEFINE_IDA(master_ida); -struct fsi_slave { - struct device dev; - struct fsi_master *master; - struct cdev cdev; - int cdev_idx; - int id; /* FSI address */ - int link; /* FSI link# */ - u32 cfam_id; - int chip_id; - uint32_t size; /* size of slave address space */ - u8 t_send_delay; - u8 t_echo_delay; -}; - -#define CREATE_TRACE_POINTS -#include <trace/events/fsi.h> - -#define to_fsi_master(d) container_of(d, struct fsi_master, dev) -#define to_fsi_slave(d) container_of(d, struct fsi_slave, dev) - static const int slave_retries = 2; static int discard_errors; @@ -415,28 +401,18 @@ EXPORT_SYMBOL_GPL(fsi_slave_release_range); static bool fsi_device_node_matches(struct device *dev, struct device_node *np, uint32_t addr, uint32_t size) { - unsigned int len, na, ns; - const __be32 *prop; - uint32_t psize; - - na = of_n_addr_cells(np); - ns = of_n_size_cells(np); - - if (na != 1 || ns != 1) - return false; + u64 paddr, psize; - prop = of_get_property(np, "reg", &len); - if (!prop || len != 8) + if (of_property_read_reg(np, 0, &paddr, &psize)) return false; - if (of_read_number(prop, 1) != addr) + if (paddr != addr) return false; - psize = of_read_number(prop + 1, 1); if (psize != size) { dev_warn(dev, - "node %s matches probed address, but not size (got 0x%x, expected 0x%x)", - of_node_full_name(np), psize, size); + "node %pOF matches probed address, but not size (got 0x%llx, expected 0x%x)", + np, psize, size); } return true; @@ -653,24 +629,12 @@ static void fsi_slave_release(struct device *dev) static bool fsi_slave_node_matches(struct device_node *np, int link, uint8_t id) { - unsigned int len, na, ns; - const __be32 *prop; - - na = of_n_addr_cells(np); - ns = of_n_size_cells(np); - - /* Ensure we have the correct format for addresses and sizes in - * reg properties - */ - if (na != 2 || ns != 0) - return false; + u64 addr; - prop = of_get_property(np, "reg", &len); - if (!prop || len != 8) + if (of_property_read_reg(np, 0, &addr, NULL)) return false; - return (of_read_number(prop, 1) == link) && - (of_read_number(prop + 1, 1) == id); + return addr == (((u64)link << 32) | id); } /* Find a matching node for the slave at (link, id). Returns NULL if none @@ -949,9 +913,13 @@ static int __fsi_get_new_minor(struct fsi_slave *slave, enum fsi_dev_type type, /* Check if we qualify for legacy numbering */ if (cid >= 0 && cid < 16 && type < 4) { - /* Try reserving the legacy number */ - id = (cid << 4) | type; - id = ida_simple_get(&fsi_minor_ida, id, id + 1, GFP_KERNEL); + /* + * Try reserving the legacy number, which has 0 - 0x3f reserved + * in the ida range. cid goes up to 0xf and type contains two + * bits, so construct the id with the below two bit shift. + */ + id = (cid << 2) | type; + id = ida_alloc_range(&fsi_minor_ida, id, id, GFP_KERNEL); if (id >= 0) { *out_index = fsi_adjust_index(cid); *out_dev = fsi_base_dev + id; @@ -962,8 +930,8 @@ static int __fsi_get_new_minor(struct fsi_slave *slave, enum fsi_dev_type type, return id; /* Fallback to non-legacy allocation */ } - id = ida_simple_get(&fsi_minor_ida, FSI_CHAR_LEGACY_TOP, - FSI_CHAR_MAX_DEVICES, GFP_KERNEL); + id = ida_alloc_range(&fsi_minor_ida, FSI_CHAR_LEGACY_TOP, + FSI_CHAR_MAX_DEVICES - 1, GFP_KERNEL); if (id < 0) return id; *out_index = fsi_adjust_index(id); @@ -971,16 +939,42 @@ static int __fsi_get_new_minor(struct fsi_slave *slave, enum fsi_dev_type type, return 0; } +static const char *const fsi_dev_type_names[] = { + "cfam", + "sbefifo", + "scom", + "occ", +}; + int fsi_get_new_minor(struct fsi_device *fdev, enum fsi_dev_type type, dev_t *out_dev, int *out_index) { + if (fdev->dev.of_node) { + int aid = of_alias_get_id(fdev->dev.of_node, fsi_dev_type_names[type]); + + if (aid >= 0) { + /* Use the same scheme as the legacy numbers. */ + int id = (aid << 2) | type; + + id = ida_alloc_range(&fsi_minor_ida, id, id, GFP_KERNEL); + if (id >= 0) { + *out_index = aid; + *out_dev = fsi_base_dev + id; + return 0; + } + + if (id != -ENOSPC) + return id; + } + } + return __fsi_get_new_minor(fdev->slave, type, out_dev, out_index); } EXPORT_SYMBOL_GPL(fsi_get_new_minor); void fsi_free_minor(dev_t dev) { - ida_simple_remove(&fsi_minor_ida, MINOR(dev)); + ida_free(&fsi_minor_ida, MINOR(dev)); } EXPORT_SYMBOL_GPL(fsi_free_minor); @@ -1210,6 +1204,7 @@ static int fsi_master_scan(struct fsi_master *master) { int link, rc; + trace_fsi_master_scan(master, true); for (link = 0; link < master->n_links; link++) { rc = fsi_master_link_enable(master, link); if (rc) { @@ -1251,6 +1246,7 @@ static int fsi_master_remove_slave(struct device *dev, void *arg) static void fsi_master_unscan(struct fsi_master *master) { + trace_fsi_master_scan(master, false); device_for_each_child(&master->dev, NULL, fsi_master_remove_slave); } @@ -1313,41 +1309,53 @@ int fsi_master_register(struct fsi_master *master) struct device_node *np; mutex_init(&master->scan_lock); - master->idx = ida_simple_get(&master_ida, 0, INT_MAX, GFP_KERNEL); + + /* Alloc the requested index if it's non-zero */ + if (master->idx) { + master->idx = ida_alloc_range(&master_ida, master->idx, + master->idx, GFP_KERNEL); + } else { + master->idx = ida_alloc(&master_ida, GFP_KERNEL); + } + if (master->idx < 0) return master->idx; - dev_set_name(&master->dev, "fsi%d", master->idx); + if (!dev_name(&master->dev)) + dev_set_name(&master->dev, "fsi%d", master->idx); + master->dev.class = &fsi_master_class; + mutex_lock(&master->scan_lock); rc = device_register(&master->dev); if (rc) { - ida_simple_remove(&master_ida, master->idx); - return rc; + ida_free(&master_ida, master->idx); + goto out; } np = dev_of_node(&master->dev); if (!of_property_read_bool(np, "no-scan-on-init")) { - mutex_lock(&master->scan_lock); fsi_master_scan(master); - mutex_unlock(&master->scan_lock); } - - return 0; +out: + mutex_unlock(&master->scan_lock); + return rc; } EXPORT_SYMBOL_GPL(fsi_master_register); void fsi_master_unregister(struct fsi_master *master) { - if (master->idx >= 0) { - ida_simple_remove(&master_ida, master->idx); - master->idx = -1; - } + int idx = master->idx; + + trace_fsi_master_unregister(master); mutex_lock(&master->scan_lock); fsi_master_unscan(master); + master->n_links = 0; mutex_unlock(&master->scan_lock); + device_unregister(&master->dev); + ida_free(&master_ida, idx); } EXPORT_SYMBOL_GPL(fsi_master_unregister); @@ -1366,8 +1374,14 @@ static int fsi_bus_match(struct device *dev, struct device_driver *drv) if (id->engine_type != fsi_dev->engine_type) continue; if (id->version == FSI_VERSION_ANY || - id->version == fsi_dev->version) - return 1; + id->version == fsi_dev->version) { + if (drv->of_match_table) { + if (of_driver_match_device(dev, drv)) + return 1; + } else { + return 1; + } + } } return 0; diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c index 7cec1772820d..f0a19cd451a0 100644 --- a/drivers/fsi/fsi-master-aspeed.c +++ b/drivers/fsi/fsi-master-aspeed.c @@ -376,7 +376,7 @@ static int aspeed_master_break(struct fsi_master *master, int link) static void aspeed_master_release(struct device *dev) { struct fsi_master_aspeed *aspeed = - to_fsi_master_aspeed(dev_to_fsi_master(dev)); + to_fsi_master_aspeed(to_fsi_master(dev)); kfree(aspeed); } @@ -454,6 +454,8 @@ static ssize_t cfam_reset_store(struct device *dev, struct device_attribute *att gpiod_set_value(aspeed->cfam_reset_gpio, 1); usleep_range(900, 1000); gpiod_set_value(aspeed->cfam_reset_gpio, 0); + usleep_range(900, 1000); + opb_writel(aspeed, ctrl_base + FSI_MRESP0, cpu_to_be32(FSI_MRESP_RST_ALL_MASTER)); mutex_unlock(&aspeed->lock); trace_fsi_master_aspeed_cfam_reset(false); diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c index 5f608ef8b53c..812dfa9a9140 100644 --- a/drivers/fsi/fsi-master-ast-cf.c +++ b/drivers/fsi/fsi-master-ast-cf.c @@ -1133,7 +1133,7 @@ static int fsi_master_acf_gpio_request(void *data) /* Note: This doesn't require holding out mutex */ - /* Write reqest */ + /* Write request */ iowrite8(ARB_ARM_REQ, master->sram + ARB_REG); /* @@ -1190,7 +1190,7 @@ static int fsi_master_acf_gpio_release(void *data) static void fsi_master_acf_release(struct device *dev) { - struct fsi_master_acf *master = to_fsi_master_acf(dev_to_fsi_master(dev)); + struct fsi_master_acf *master = to_fsi_master_acf(to_fsi_master(dev)); /* Cleanup, stop coprocessor */ mutex_lock(&master->lock); @@ -1441,3 +1441,4 @@ static struct platform_driver fsi_master_acf = { module_platform_driver(fsi_master_acf); MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(FW_FILE_NAME); diff --git a/drivers/fsi/fsi-master-gpio.c b/drivers/fsi/fsi-master-gpio.c index 7d5f29b4b595..ed03da4f2447 100644 --- a/drivers/fsi/fsi-master-gpio.c +++ b/drivers/fsi/fsi-master-gpio.c @@ -761,7 +761,7 @@ static DEVICE_ATTR(external_mode, 0664, static void fsi_master_gpio_release(struct device *dev) { - struct fsi_master_gpio *master = to_fsi_master_gpio(dev_to_fsi_master(dev)); + struct fsi_master_gpio *master = to_fsi_master_gpio(to_fsi_master(dev)); of_node_put(dev_of_node(master->dev)); diff --git a/drivers/fsi/fsi-master-hub.c b/drivers/fsi/fsi-master-hub.c index 01f0a796111e..6d8b6e8854e5 100644 --- a/drivers/fsi/fsi-master-hub.c +++ b/drivers/fsi/fsi-master-hub.c @@ -105,7 +105,7 @@ static int hub_master_link_enable(struct fsi_master *master, int link, static void hub_master_release(struct device *dev) { - struct fsi_master_hub *hub = to_fsi_master_hub(dev_to_fsi_master(dev)); + struct fsi_master_hub *hub = to_fsi_master_hub(to_fsi_master(dev)); kfree(hub); } diff --git a/drivers/fsi/fsi-master-i2cr.c b/drivers/fsi/fsi-master-i2cr.c new file mode 100644 index 000000000000..40f1f4d231e5 --- /dev/null +++ b/drivers/fsi/fsi-master-i2cr.c @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) IBM Corporation 2023 */ + +#include <linux/device.h> +#include <linux/fsi.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/mutex.h> + +#include "fsi-master-i2cr.h" + +#define CREATE_TRACE_POINTS +#include <trace/events/fsi_master_i2cr.h> + +#define I2CR_ADDRESS_CFAM(a) ((a) >> 2) +#define I2CR_INITIAL_PARITY true + +#define I2CR_STATUS_CMD 0x60002 +#define I2CR_STATUS_ERR BIT_ULL(61) +#define I2CR_ERROR_CMD 0x60004 +#define I2CR_LOG_CMD 0x60008 + +static const u8 i2cr_cfam[] = { + 0xc0, 0x02, 0x0d, 0xa6, + 0x80, 0x01, 0x10, 0x02, + 0x80, 0x01, 0x10, 0x02, + 0x80, 0x01, 0x10, 0x02, + 0x80, 0x01, 0x80, 0x52, + 0x80, 0x01, 0x10, 0x02, + 0x80, 0x01, 0x10, 0x02, + 0x80, 0x01, 0x10, 0x02, + 0x80, 0x01, 0x10, 0x02, + 0x80, 0x01, 0x22, 0x2d, + 0x00, 0x00, 0x00, 0x00, + 0xde, 0xad, 0xc0, 0xde +}; + +static bool i2cr_check_parity32(u32 v, bool parity) +{ + u32 i; + + for (i = 0; i < 32; ++i) { + if (v & (1u << i)) + parity = !parity; + } + + return parity; +} + +static bool i2cr_check_parity64(u64 v) +{ + u32 i; + bool parity = I2CR_INITIAL_PARITY; + + for (i = 0; i < 64; ++i) { + if (v & (1llu << i)) + parity = !parity; + } + + return parity; +} + +static u32 i2cr_get_command(u32 address, bool parity) +{ + address <<= 1; + + if (i2cr_check_parity32(address, parity)) + address |= 1; + + return address; +} + +static int i2cr_transfer(struct i2c_client *client, u32 command, u64 *data) +{ + struct i2c_msg msgs[2]; + int ret; + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = sizeof(command); + msgs[0].buf = (__u8 *)&command; + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = sizeof(*data); + msgs[1].buf = (__u8 *)data; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret == 2) + return 0; + + trace_i2cr_i2c_error(client, command, ret); + + if (ret < 0) + return ret; + + return -EIO; +} + +static int i2cr_check_status(struct i2c_client *client) +{ + u64 status; + int ret; + + ret = i2cr_transfer(client, I2CR_STATUS_CMD, &status); + if (ret) + return ret; + + if (status & I2CR_STATUS_ERR) { + u32 buf[3] = { 0, 0, 0 }; + u64 error; + u64 log; + + i2cr_transfer(client, I2CR_ERROR_CMD, &error); + i2cr_transfer(client, I2CR_LOG_CMD, &log); + + trace_i2cr_status_error(client, status, error, log); + + buf[0] = I2CR_STATUS_CMD; + i2c_master_send(client, (const char *)buf, sizeof(buf)); + + buf[0] = I2CR_ERROR_CMD; + i2c_master_send(client, (const char *)buf, sizeof(buf)); + + buf[0] = I2CR_LOG_CMD; + i2c_master_send(client, (const char *)buf, sizeof(buf)); + + dev_err(&client->dev, "status:%016llx error:%016llx log:%016llx\n", status, error, + log); + return -EREMOTEIO; + } + + trace_i2cr_status(client, status); + return 0; +} + +int fsi_master_i2cr_read(struct fsi_master_i2cr *i2cr, u32 addr, u64 *data) +{ + u32 command = i2cr_get_command(addr, I2CR_INITIAL_PARITY); + int ret; + + mutex_lock(&i2cr->lock); + + ret = i2cr_transfer(i2cr->client, command, data); + if (ret) + goto unlock; + + ret = i2cr_check_status(i2cr->client); + if (ret) + goto unlock; + + trace_i2cr_read(i2cr->client, command, data); + +unlock: + mutex_unlock(&i2cr->lock); + return ret; +} +EXPORT_SYMBOL_GPL(fsi_master_i2cr_read); + +int fsi_master_i2cr_write(struct fsi_master_i2cr *i2cr, u32 addr, u64 data) +{ + u32 buf[3] = { 0 }; + int ret; + + buf[0] = i2cr_get_command(addr, i2cr_check_parity64(data)); + memcpy(&buf[1], &data, sizeof(data)); + + mutex_lock(&i2cr->lock); + + ret = i2c_master_send(i2cr->client, (const char *)buf, sizeof(buf)); + if (ret == sizeof(buf)) { + ret = i2cr_check_status(i2cr->client); + if (!ret) + trace_i2cr_write(i2cr->client, buf[0], data); + } else { + trace_i2cr_i2c_error(i2cr->client, buf[0], ret); + + if (ret >= 0) + ret = -EIO; + } + + mutex_unlock(&i2cr->lock); + return ret; +} +EXPORT_SYMBOL_GPL(fsi_master_i2cr_write); + +static int i2cr_read(struct fsi_master *master, int link, uint8_t id, uint32_t addr, void *val, + size_t size) +{ + struct fsi_master_i2cr *i2cr = container_of(master, struct fsi_master_i2cr, master); + u64 data; + size_t i; + int ret; + + if (link || id || (addr & 0xffff0000) || !(size == 1 || size == 2 || size == 4)) + return -EINVAL; + + /* + * The I2CR doesn't have CFAM or FSI slave address space - only the + * engines. In order for this to work with the FSI core, we need to + * emulate at minimum the CFAM config table so that the appropriate + * engines are discovered. + */ + if (addr < 0xc00) { + if (addr > sizeof(i2cr_cfam) - 4) + addr = (addr & 0x3) + (sizeof(i2cr_cfam) - 4); + + memcpy(val, &i2cr_cfam[addr], size); + return 0; + } + + ret = fsi_master_i2cr_read(i2cr, I2CR_ADDRESS_CFAM(addr), &data); + if (ret) + return ret; + + /* + * FSI core expects up to 4 bytes BE back, while I2CR replied with LE + * bytes on the wire. + */ + for (i = 0; i < size; ++i) + ((u8 *)val)[i] = ((u8 *)&data)[7 - i]; + + return 0; +} + +static int i2cr_write(struct fsi_master *master, int link, uint8_t id, uint32_t addr, + const void *val, size_t size) +{ + struct fsi_master_i2cr *i2cr = container_of(master, struct fsi_master_i2cr, master); + u64 data = 0; + size_t i; + + if (link || id || (addr & 0xffff0000) || !(size == 1 || size == 2 || size == 4)) + return -EINVAL; + + /* I2CR writes to CFAM or FSI slave address are a successful no-op. */ + if (addr < 0xc00) + return 0; + + /* + * FSI core passes up to 4 bytes BE, while the I2CR expects LE bytes on + * the wire. + */ + for (i = 0; i < size; ++i) + ((u8 *)&data)[7 - i] = ((u8 *)val)[i]; + + return fsi_master_i2cr_write(i2cr, I2CR_ADDRESS_CFAM(addr), data); +} + +static void i2cr_release(struct device *dev) +{ + struct fsi_master_i2cr *i2cr = to_fsi_master_i2cr(to_fsi_master(dev)); + + of_node_put(dev->of_node); + + kfree(i2cr); +} + +static int i2cr_probe(struct i2c_client *client) +{ + struct fsi_master_i2cr *i2cr; + int ret; + + i2cr = kzalloc(sizeof(*i2cr), GFP_KERNEL); + if (!i2cr) + return -ENOMEM; + + /* Only one I2CR on any given I2C bus (fixed I2C device address) */ + i2cr->master.idx = client->adapter->nr; + dev_set_name(&i2cr->master.dev, "i2cr%d", i2cr->master.idx); + i2cr->master.dev.parent = &client->dev; + i2cr->master.dev.of_node = of_node_get(dev_of_node(&client->dev)); + i2cr->master.dev.release = i2cr_release; + + i2cr->master.n_links = 1; + i2cr->master.read = i2cr_read; + i2cr->master.write = i2cr_write; + + mutex_init(&i2cr->lock); + i2cr->client = client; + + ret = fsi_master_register(&i2cr->master); + if (ret) + return ret; + + i2c_set_clientdata(client, i2cr); + return 0; +} + +static void i2cr_remove(struct i2c_client *client) +{ + struct fsi_master_i2cr *i2cr = i2c_get_clientdata(client); + + fsi_master_unregister(&i2cr->master); +} + +static const struct of_device_id i2cr_ids[] = { + { .compatible = "ibm,i2cr-fsi-master" }, + { } +}; +MODULE_DEVICE_TABLE(of, i2cr_ids); + +static struct i2c_driver i2cr_driver = { + .probe = i2cr_probe, + .remove = i2cr_remove, + .driver = { + .name = "fsi-master-i2cr", + .of_match_table = i2cr_ids, + }, +}; + +module_i2c_driver(i2cr_driver) + +MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>"); +MODULE_DESCRIPTION("IBM I2C Responder virtual FSI master driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/fsi/fsi-master-i2cr.h b/drivers/fsi/fsi-master-i2cr.h new file mode 100644 index 000000000000..96636bf28cac --- /dev/null +++ b/drivers/fsi/fsi-master-i2cr.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) IBM Corporation 2023 */ + +#ifndef DRIVERS_FSI_MASTER_I2CR_H +#define DRIVERS_FSI_MASTER_I2CR_H + +#include <linux/i2c.h> +#include <linux/mutex.h> + +#include "fsi-master.h" + +struct i2c_client; + +struct fsi_master_i2cr { + struct fsi_master master; + struct mutex lock; /* protect HW access */ + struct i2c_client *client; +}; + +#define to_fsi_master_i2cr(m) container_of(m, struct fsi_master_i2cr, master) + +int fsi_master_i2cr_read(struct fsi_master_i2cr *i2cr, u32 addr, u64 *data); +int fsi_master_i2cr_write(struct fsi_master_i2cr *i2cr, u32 addr, u64 data); + +static inline bool is_fsi_master_i2cr(struct fsi_master *master) +{ + if (master->dev.parent && master->dev.parent->type == &i2c_client_type) + return true; + + return false; +} + +#endif /* DRIVERS_FSI_MASTER_I2CR_H */ diff --git a/drivers/fsi/fsi-master.h b/drivers/fsi/fsi-master.h index 4762315a46ba..967622c1cabf 100644 --- a/drivers/fsi/fsi-master.h +++ b/drivers/fsi/fsi-master.h @@ -136,7 +136,7 @@ struct fsi_master { u8 t_send_delay, u8 t_echo_delay); }; -#define dev_to_fsi_master(d) container_of(d, struct fsi_master, dev) +#define to_fsi_master(d) container_of(d, struct fsi_master, dev) /** * fsi_master registration & lifetime: the fsi_master_register() and diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c index abdd37d5507f..da35ca9e84a6 100644 --- a/drivers/fsi/fsi-occ.c +++ b/drivers/fsi/fsi-occ.c @@ -15,7 +15,7 @@ #include <linux/mutex.h> #include <linux/fsi-occ.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/sched.h> #include <linux/slab.h> diff --git a/drivers/fsi/fsi-sbefifo.c b/drivers/fsi/fsi-sbefifo.c index 9912b7a6a4b9..0a98517f3959 100644 --- a/drivers/fsi/fsi-sbefifo.c +++ b/drivers/fsi/fsi-sbefifo.c @@ -22,8 +22,8 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/of_platform.h> +#include <linux/platform_device.h> #include <linux/sched.h> #include <linux/slab.h> #include <linux/uaccess.h> @@ -81,7 +81,7 @@ enum sbe_state { - SBE_STATE_UNKNOWN = 0x0, // Unkown, initial state + SBE_STATE_UNKNOWN = 0x0, // Unknown, initial state SBE_STATE_IPLING = 0x1, // IPL'ing - autonomous mode (transient) SBE_STATE_ISTEP = 0x2, // ISTEP - Running IPL by steps (transient) SBE_STATE_MPIPL = 0x3, // MPIPL @@ -127,6 +127,7 @@ struct sbefifo { bool dead; bool async_ffdc; bool timed_out; + u32 timeout_in_cmd_ms; u32 timeout_start_rsp_ms; }; @@ -136,6 +137,7 @@ struct sbefifo_user { void *cmd_page; void *pending_cmd; size_t pending_len; + u32 cmd_timeout_ms; u32 read_timeout_ms; }; @@ -508,7 +510,7 @@ static int sbefifo_send_command(struct sbefifo *sbefifo, rc = sbefifo_wait(sbefifo, true, &status, timeout); if (rc < 0) return rc; - timeout = msecs_to_jiffies(SBEFIFO_TIMEOUT_IN_CMD); + timeout = msecs_to_jiffies(sbefifo->timeout_in_cmd_ms); vacant = sbefifo_vacant(status); len = chunk = min(vacant, remaining); @@ -730,7 +732,7 @@ static int __sbefifo_submit(struct sbefifo *sbefifo, * @response: The output response buffer * @resp_len: In: Response buffer size, Out: Response size * - * This will perform the entire operation. If the reponse buffer + * This will perform the entire operation. If the response buffer * overflows, returns -EOVERFLOW */ int sbefifo_submit(struct device *dev, const __be32 *command, size_t cmd_len, @@ -802,6 +804,7 @@ static int sbefifo_user_open(struct inode *inode, struct file *file) return -ENOMEM; } mutex_init(&user->file_lock); + user->cmd_timeout_ms = SBEFIFO_TIMEOUT_IN_CMD; user->read_timeout_ms = SBEFIFO_TIMEOUT_START_RSP; return 0; @@ -845,9 +848,11 @@ static ssize_t sbefifo_user_read(struct file *file, char __user *buf, rc = mutex_lock_interruptible(&sbefifo->lock); if (rc) goto bail; + sbefifo->timeout_in_cmd_ms = user->cmd_timeout_ms; sbefifo->timeout_start_rsp_ms = user->read_timeout_ms; rc = __sbefifo_submit(sbefifo, user->pending_cmd, cmd_len, &resp_iter); sbefifo->timeout_start_rsp_ms = SBEFIFO_TIMEOUT_START_RSP; + sbefifo->timeout_in_cmd_ms = SBEFIFO_TIMEOUT_IN_CMD; mutex_unlock(&sbefifo->lock); if (rc < 0) goto bail; @@ -937,7 +942,7 @@ static int sbefifo_user_release(struct inode *inode, struct file *file) return 0; } -static int sbefifo_read_timeout(struct sbefifo_user *user, void __user *argp) +static int sbefifo_cmd_timeout(struct sbefifo_user *user, void __user *argp) { struct device *dev = &user->sbefifo->dev; u32 timeout; @@ -946,18 +951,32 @@ static int sbefifo_read_timeout(struct sbefifo_user *user, void __user *argp) return -EFAULT; if (timeout == 0) { - user->read_timeout_ms = SBEFIFO_TIMEOUT_START_RSP; - dev_dbg(dev, "Timeout reset to %d\n", user->read_timeout_ms); + user->cmd_timeout_ms = SBEFIFO_TIMEOUT_IN_CMD; + dev_dbg(dev, "Command timeout reset to %us\n", user->cmd_timeout_ms / 1000); return 0; } - if (timeout < 10 || timeout > 120) - return -EINVAL; + user->cmd_timeout_ms = timeout * 1000; /* user timeout is in sec */ + dev_dbg(dev, "Command timeout set to %us\n", timeout); + return 0; +} - user->read_timeout_ms = timeout * 1000; /* user timeout is in sec */ +static int sbefifo_read_timeout(struct sbefifo_user *user, void __user *argp) +{ + struct device *dev = &user->sbefifo->dev; + u32 timeout; - dev_dbg(dev, "Timeout set to %d\n", user->read_timeout_ms); + if (get_user(timeout, (__u32 __user *)argp)) + return -EFAULT; + if (timeout == 0) { + user->read_timeout_ms = SBEFIFO_TIMEOUT_START_RSP; + dev_dbg(dev, "Timeout reset to %us\n", user->read_timeout_ms / 1000); + return 0; + } + + user->read_timeout_ms = timeout * 1000; /* user timeout is in sec */ + dev_dbg(dev, "Timeout set to %us\n", timeout); return 0; } @@ -971,6 +990,9 @@ static long sbefifo_user_ioctl(struct file *file, unsigned int cmd, unsigned lon mutex_lock(&user->file_lock); switch (cmd) { + case FSI_SBEFIFO_CMD_TIMEOUT_SECONDS: + rc = sbefifo_cmd_timeout(user, (void __user *)arg); + break; case FSI_SBEFIFO_READ_TIMEOUT_SECONDS: rc = sbefifo_read_timeout(user, (void __user *)arg); break; @@ -1025,16 +1047,9 @@ static int sbefifo_probe(struct device *dev) sbefifo->fsi_dev = fsi_dev; dev_set_drvdata(dev, sbefifo); mutex_init(&sbefifo->lock); + sbefifo->timeout_in_cmd_ms = SBEFIFO_TIMEOUT_IN_CMD; sbefifo->timeout_start_rsp_ms = SBEFIFO_TIMEOUT_START_RSP; - /* - * Try cleaning up the FIFO. If this fails, we still register the - * driver and will try cleaning things up again on the next access. - */ - rc = sbefifo_cleanup_hw(sbefifo); - if (rc && rc != -ESHUTDOWN) - dev_err(dev, "Initial HW cleanup failed, will retry later\n"); - /* Create chardev for userspace access */ sbefifo->dev.type = &fsi_cdev_type; sbefifo->dev.parent = dev; diff --git a/drivers/fsi/fsi-scom.c b/drivers/fsi/fsi-scom.c index bcb756dc9866..61dbda9dbe2b 100644 --- a/drivers/fsi/fsi-scom.c +++ b/drivers/fsi/fsi-scom.c @@ -10,6 +10,7 @@ #include <linux/cdev.h> #include <linux/delay.h> #include <linux/fs.h> +#include <linux/mod_devicetable.h> #include <linux/uaccess.h> #include <linux/slab.h> #include <linux/list.h> @@ -587,6 +588,12 @@ static int scom_remove(struct device *dev) return 0; } +static const struct of_device_id scom_of_ids[] = { + { .compatible = "ibm,fsi2pib" }, + { } +}; +MODULE_DEVICE_TABLE(of, scom_of_ids); + static const struct fsi_device_id scom_ids[] = { { .engine_type = FSI_ENGID_SCOM, @@ -600,6 +607,7 @@ static struct fsi_driver scom_drv = { .drv = { .name = "scom", .bus = &fsi_bus_type, + .of_match_table = scom_of_ids, .probe = scom_probe, .remove = scom_remove, } diff --git a/drivers/fsi/fsi-slave.h b/drivers/fsi/fsi-slave.h new file mode 100644 index 000000000000..1d63a585829d --- /dev/null +++ b/drivers/fsi/fsi-slave.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) IBM Corporation 2023 */ + +#ifndef DRIVERS_FSI_SLAVE_H +#define DRIVERS_FSI_SLAVE_H + +#include <linux/cdev.h> +#include <linux/device.h> + +struct fsi_master; + +struct fsi_slave { + struct device dev; + struct fsi_master *master; + struct cdev cdev; + int cdev_idx; + int id; /* FSI address */ + int link; /* FSI link# */ + u32 cfam_id; + int chip_id; + uint32_t size; /* size of slave address space */ + u8 t_send_delay; + u8 t_echo_delay; +}; + +#define to_fsi_slave(d) container_of(d, struct fsi_slave, dev) + +#endif /* DRIVERS_FSI_SLAVE_H */ diff --git a/drivers/fsi/i2cr-scom.c b/drivers/fsi/i2cr-scom.c new file mode 100644 index 000000000000..cb7e02213032 --- /dev/null +++ b/drivers/fsi/i2cr-scom.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) IBM Corporation 2023 */ + +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/fs.h> +#include <linux/fsi.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> + +#include "fsi-master-i2cr.h" +#include "fsi-slave.h" + +struct i2cr_scom { + struct device dev; + struct cdev cdev; + struct fsi_master_i2cr *i2cr; +}; + +static loff_t i2cr_scom_llseek(struct file *file, loff_t offset, int whence) +{ + switch (whence) { + case SEEK_CUR: + break; + case SEEK_SET: + file->f_pos = offset; + break; + default: + return -EINVAL; + } + + return offset; +} + +static ssize_t i2cr_scom_read(struct file *filep, char __user *buf, size_t len, loff_t *offset) +{ + struct i2cr_scom *scom = filep->private_data; + u64 data; + int ret; + + if (len != sizeof(data)) + return -EINVAL; + + ret = fsi_master_i2cr_read(scom->i2cr, (u32)*offset, &data); + if (ret) + return ret; + + ret = copy_to_user(buf, &data, len); + if (ret) + return ret; + + return len; +} + +static ssize_t i2cr_scom_write(struct file *filep, const char __user *buf, size_t len, + loff_t *offset) +{ + struct i2cr_scom *scom = filep->private_data; + u64 data; + int ret; + + if (len != sizeof(data)) + return -EINVAL; + + ret = copy_from_user(&data, buf, len); + if (ret) + return ret; + + ret = fsi_master_i2cr_write(scom->i2cr, (u32)*offset, data); + if (ret) + return ret; + + return len; +} + +static const struct file_operations i2cr_scom_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .llseek = i2cr_scom_llseek, + .read = i2cr_scom_read, + .write = i2cr_scom_write, +}; + +static int i2cr_scom_probe(struct device *dev) +{ + struct fsi_device *fsi_dev = to_fsi_dev(dev); + struct i2cr_scom *scom; + int didx; + int ret; + + if (!is_fsi_master_i2cr(fsi_dev->slave->master)) + return -ENODEV; + + scom = devm_kzalloc(dev, sizeof(*scom), GFP_KERNEL); + if (!scom) + return -ENOMEM; + + scom->i2cr = to_fsi_master_i2cr(fsi_dev->slave->master); + dev_set_drvdata(dev, scom); + + scom->dev.type = &fsi_cdev_type; + scom->dev.parent = dev; + device_initialize(&scom->dev); + + ret = fsi_get_new_minor(fsi_dev, fsi_dev_scom, &scom->dev.devt, &didx); + if (ret) + return ret; + + dev_set_name(&scom->dev, "scom%d", didx); + cdev_init(&scom->cdev, &i2cr_scom_fops); + ret = cdev_device_add(&scom->cdev, &scom->dev); + if (ret) + fsi_free_minor(scom->dev.devt); + + return ret; +} + +static int i2cr_scom_remove(struct device *dev) +{ + struct i2cr_scom *scom = dev_get_drvdata(dev); + + cdev_device_del(&scom->cdev, &scom->dev); + fsi_free_minor(scom->dev.devt); + + return 0; +} + +static const struct of_device_id i2cr_scom_of_ids[] = { + { .compatible = "ibm,i2cr-scom" }, + { } +}; +MODULE_DEVICE_TABLE(of, i2cr_scom_of_ids); + +static const struct fsi_device_id i2cr_scom_ids[] = { + { 0x5, FSI_VERSION_ANY }, + { } +}; + +static struct fsi_driver i2cr_scom_driver = { + .id_table = i2cr_scom_ids, + .drv = { + .name = "i2cr_scom", + .bus = &fsi_bus_type, + .of_match_table = i2cr_scom_of_ids, + .probe = i2cr_scom_probe, + .remove = i2cr_scom_remove, + } +}; + +module_fsi_driver(i2cr_scom_driver); + +MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>"); +MODULE_DESCRIPTION("IBM I2C Responder SCOM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c index e5b65a382772..a812c15948d9 100644 --- a/drivers/hwmon/peci/cputemp.c +++ b/drivers/hwmon/peci/cputemp.c @@ -363,6 +363,7 @@ static int init_core_mask(struct peci_cputemp *priv) switch (peci_dev->info.model) { case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_ICELAKE_D: + case INTEL_FAM6_SAPPHIRERAPIDS_X: ret = peci_ep_pci_local_read(peci_dev, 0, reg->bus, reg->dev, reg->func, reg->offset + 4, &data); if (ret) @@ -531,6 +532,13 @@ static struct resolved_cores_reg resolved_cores_reg_icx = { .offset = 0xd0, }; +static struct resolved_cores_reg resolved_cores_reg_spr = { + .bus = 31, + .dev = 30, + .func = 6, + .offset = 0x80, +}; + static const struct cpu_info cpu_hsx = { .reg = &resolved_cores_reg_hsx, .min_peci_revision = 0x33, @@ -549,6 +557,12 @@ static const struct cpu_info cpu_icx = { .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree, }; +static const struct cpu_info cpu_spr = { + .reg = &resolved_cores_reg_spr, + .min_peci_revision = 0x40, + .thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree, +}; + static const struct auxiliary_device_id peci_cputemp_ids[] = { { .name = "peci_cpu.cputemp.hsx", @@ -574,6 +588,10 @@ static const struct auxiliary_device_id peci_cputemp_ids[] = { .name = "peci_cpu.cputemp.icxd", .driver_data = (kernel_ulong_t)&cpu_icx, }, + { + .name = "peci_cpu.cputemp.spr", + .driver_data = (kernel_ulong_t)&cpu_spr, + }, { } }; MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids); diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c index ce89da3937a0..5ca4d04e4b14 100644 --- a/drivers/hwmon/peci/dimmtemp.c +++ b/drivers/hwmon/peci/dimmtemp.c @@ -30,6 +30,8 @@ #define DIMM_IDX_MAX_ON_ICX 2 #define CHAN_RANK_MAX_ON_ICXD 4 #define DIMM_IDX_MAX_ON_ICXD 2 +#define CHAN_RANK_MAX_ON_SPR 8 +#define DIMM_IDX_MAX_ON_SPR 2 #define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX @@ -534,6 +536,43 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u return 0; } +static int +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) +{ + u32 reg_val; + u64 offset; + int ret; + u8 dev; + + ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd4, ®_val); + if (ret || !(reg_val & BIT(31))) + return -ENODATA; /* Use default or previous value */ + + ret = peci_ep_pci_local_read(priv->peci_dev, 0, 30, 0, 2, 0xd0, ®_val); + if (ret) + return -ENODATA; /* Use default or previous value */ + + /* + * Device 26, Offset 219a8: IMC 0 channel 0 -> rank 0 + * Device 26, Offset 299a8: IMC 0 channel 1 -> rank 1 + * Device 27, Offset 219a8: IMC 1 channel 0 -> rank 2 + * Device 27, Offset 299a8: IMC 1 channel 1 -> rank 3 + * Device 28, Offset 219a8: IMC 2 channel 0 -> rank 4 + * Device 28, Offset 299a8: IMC 2 channel 1 -> rank 5 + * Device 29, Offset 219a8: IMC 3 channel 0 -> rank 6 + * Device 29, Offset 299a8: IMC 3 channel 1 -> rank 7 + */ + dev = 26 + chan_rank / 2; + offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000; + + ret = peci_mmio_read(priv->peci_dev, 0, GET_CPU_SEG(reg_val), GET_CPU_BUS(reg_val), + dev, 0, offset, data); + if (ret) + return ret; + + return 0; +} + static const struct dimm_info dimm_hsx = { .chan_rank_max = CHAN_RANK_MAX_ON_HSX, .dimm_idx_max = DIMM_IDX_MAX_ON_HSX, @@ -576,6 +615,13 @@ static const struct dimm_info dimm_icxd = { .read_thresholds = &read_thresholds_icx, }; +static const struct dimm_info dimm_spr = { + .chan_rank_max = CHAN_RANK_MAX_ON_SPR, + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR, + .min_peci_revision = 0x40, + .read_thresholds = &read_thresholds_spr, +}; + static const struct auxiliary_device_id peci_dimmtemp_ids[] = { { .name = "peci_cpu.dimmtemp.hsx", @@ -601,6 +647,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = { .name = "peci_cpu.dimmtemp.icxd", .driver_data = (kernel_ulong_t)&dimm_icxd, }, + { + .name = "peci_cpu.dimmtemp.spr", + .driver_data = (kernel_ulong_t)&dimm_spr, + }, { } }; MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids); diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 118fcf27854d..9fabe00a40d6 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -17,7 +17,7 @@ #include <linux/mutex.h> #include <linux/clk.h> #include <linux/coresight.h> -#include <linux/of_platform.h> +#include <linux/property.h> #include <linux/delay.h> #include <linux/pm_runtime.h> diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index 7023ff70cc28..3999d0a2cb60 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -22,7 +22,7 @@ #include "coresight-priv.h" #include "coresight-cti.h" -/** +/* * CTI devices can be associated with a PE, or be connected to CoreSight * hardware. We have a list of all CTIs irrespective of CPU bound or * otherwise. diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtracing/coresight/coresight-dummy.c index 8035120b70b3..e4deafae7bc2 100644 --- a/drivers/hwtracing/coresight/coresight-dummy.c +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -147,17 +147,7 @@ static struct platform_driver dummy_driver = { }, }; -static int __init dummy_init(void) -{ - return platform_driver_register(&dummy_driver); -} -module_init(dummy_init); - -static void __exit dummy_exit(void) -{ - platform_driver_unregister(&dummy_driver); -} -module_exit(dummy_exit); +module_platform_driver(dummy_driver); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("CoreSight dummy driver"); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c index d2ea903231b2..c302072b293a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -40,7 +40,7 @@ * Invalid offsets will result in fail code return and feature load failure. * * @drvdata: driver data to map into. - * @reg: register to map. + * @reg_csdev: register to map. * @offset: device offset for the register */ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, @@ -132,7 +132,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, * etm4_cfg_load_feature - load a feature into a device instance. * * @csdev: An ETMv4 CoreSight device. - * @feat: The feature to be loaded. + * @feat_csdev: The feature to be loaded. * * The function will load a feature instance into the device, checking that * the register definitions are valid for the device. diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7e307022303a..77b0271ce6eb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -3,6 +3,7 @@ * Copyright (c) 2014, The Linux Foundation. All rights reserved. */ +#include <linux/acpi.h> #include <linux/bitops.h> #include <linux/kernel.h> #include <linux/moduleparam.h> @@ -30,6 +31,7 @@ #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/property.h> +#include <linux/clk/clk-conf.h> #include <asm/barrier.h> #include <asm/sections.h> @@ -66,7 +68,6 @@ static u64 etm4_get_access_type(struct etmv4_config *config); static enum cpuhp_state hp_online; struct etm4_init_arg { - unsigned int pid; struct device *dev; struct csdev_access *csa; }; @@ -370,9 +371,17 @@ static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) } static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, - unsigned int id) + struct csdev_access *csa) { - if (etm4_hisi_match_pid(id)) + /* + * TRCPIDR* registers are not required for ETMs with system + * instructions. They must be identified by the MIDR+REVIDRs. + * Skip the TRCPID checks for now. + */ + if (!csa->io_mem) + return; + + if (etm4_hisi_match_pid(coresight_get_pid(csa))) set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features); } #else @@ -385,7 +394,7 @@ static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) } static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, - unsigned int id) + struct csdev_access *csa) { } #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */ @@ -1066,11 +1075,21 @@ static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, return true; } +static bool is_devtype_cpu_trace(void __iomem *base) +{ + u32 devtype = readl(base + TRCDEVTYPE); + + return (devtype == CS_DEVTYPE_PE_TRACE); +} + static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH); + if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base)) + return false; + /* * All ETMs must implement TRCDEVARCH to indicate that * the component is an ETMv4. Even though TRCIDR1 also @@ -1161,7 +1180,7 @@ static void etm4_init_arch_data(void *info) etm4_os_unlock_csa(drvdata, csa); etm4_cs_unlock(drvdata, csa); - etm4_check_arch_features(drvdata, init_arg->pid); + etm4_check_arch_features(drvdata, csa); /* find all capabilities of the tracing unit */ etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); @@ -2044,19 +2063,16 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) return 0; } -static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) +static int etm4_probe(struct device *dev) { - struct etmv4_drvdata *drvdata; + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); struct csdev_access access = { 0 }; struct etm4_init_arg init_arg = { 0 }; struct etm4_init_arg *delayed; - drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); - if (!drvdata) + if (WARN_ON(!drvdata)) return -ENOMEM; - dev_set_drvdata(dev, drvdata); - if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) pm_save_enable = coresight_loses_context_with_cpu(dev) ? PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; @@ -2068,8 +2084,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) return -ENOMEM; } - drvdata->base = base; - spin_lock_init(&drvdata->spinlock); drvdata->cpu = coresight_get_cpu(dev); @@ -2078,7 +2092,6 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) init_arg.dev = dev; init_arg.csa = &access; - init_arg.pid = etm_pid; /* * Serialize against CPUHP callbacks to avoid race condition @@ -2108,6 +2121,7 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) { + struct etmv4_drvdata *drvdata; void __iomem *base; struct device *dev = &adev->dev; struct resource *res = &adev->res; @@ -2118,7 +2132,13 @@ static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) if (IS_ERR(base)) return PTR_ERR(base); - ret = etm4_probe(dev, base, id->id); + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->base = base; + dev_set_drvdata(dev, drvdata); + ret = etm4_probe(dev); if (!ret) pm_runtime_put(&adev->dev); @@ -2127,18 +2147,32 @@ static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) static int etm4_probe_platform_dev(struct platform_device *pdev) { + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct etmv4_drvdata *drvdata; int ret; + drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev); + if (IS_ERR(drvdata->pclk)) + return -ENODEV; + + if (res) { + drvdata->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(drvdata->base)) { + clk_put(drvdata->pclk); + return PTR_ERR(drvdata->base); + } + } + + dev_set_drvdata(&pdev->dev, drvdata); pm_runtime_get_noresume(&pdev->dev); pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); - /* - * System register based devices could match the - * HW by reading appropriate registers on the HW - * and thus we could skip the PID. - */ - ret = etm4_probe(&pdev->dev, NULL, 0); + ret = etm4_probe(&pdev->dev); pm_runtime_put(&pdev->dev); return ret; @@ -2178,7 +2212,7 @@ static struct amba_cs_uci_id uci_id_etm4[] = { /* ETMv4 UCI data */ .devarch = ETM_DEVARCH_ETMv4x_ARCH, .devarch_mask = ETM_DEVARCH_ID_MASK, - .devtype = 0x00000013, + .devtype = CS_DEVTYPE_PE_TRACE, } }; @@ -2234,6 +2268,10 @@ static int __exit etm4_remove_platform_dev(struct platform_device *pdev) if (drvdata) etm4_remove_dev(drvdata); pm_runtime_disable(&pdev->dev); + + if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) + clk_put(drvdata->pclk); + return 0; } @@ -2278,19 +2316,55 @@ static struct amba_driver etm4x_amba_driver = { .id_table = etm4_ids, }; +#ifdef CONFIG_PM +static int etm4_runtime_suspend(struct device *dev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata->pclk && !IS_ERR(drvdata->pclk)) + clk_disable_unprepare(drvdata->pclk); + + return 0; +} + +static int etm4_runtime_resume(struct device *dev) +{ + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata->pclk && !IS_ERR(drvdata->pclk)) + clk_prepare_enable(drvdata->pclk); + + return 0; +} +#endif + +static const struct dev_pm_ops etm4_dev_pm_ops = { + SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL) +}; + static const struct of_device_id etm4_sysreg_match[] = { { .compatible = "arm,coresight-etm4x-sysreg" }, { .compatible = "arm,embedded-trace-extension" }, {} }; +#ifdef CONFIG_ACPI +static const struct acpi_device_id etm4x_acpi_ids[] = { + {"ARMHC500", 0}, /* ARM CoreSight ETM4x */ + {} +}; +MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids); +#endif + static struct platform_driver etm4_platform_driver = { .probe = etm4_probe_platform_dev, .remove = etm4_remove_platform_dev, .driver = { .name = "coresight-etm4x", .of_match_table = etm4_sysreg_match, + .acpi_match_table = ACPI_PTR(etm4x_acpi_ids), .suppress_bind_attrs = true, + .pm = &etm4_dev_pm_ops, }, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 27c8a9901868..20e2e4cb7614 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -701,6 +701,8 @@ #define ETM_DEVARCH_ETE_ARCH \ (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT) +#define CS_DEVTYPE_PE_TRACE 0x00000013 + #define TRCSTATR_IDLE_BIT 0 #define TRCSTATR_PMSTABLE_BIT 1 #define ETM_DEFAULT_ADDR_COMP 0 @@ -944,6 +946,7 @@ struct etmv4_save_state { /** * struct etm4_drvdata - specifics associated to an ETM component + * @pclk APB clock if present, otherwise NULL * @base: Memory mapped base address for this component. * @csdev: Component vitals needed by the framework. * @spinlock: Only one at a time pls. @@ -1009,6 +1012,7 @@ struct etmv4_save_state { * @arch_features: Bitmap of arch features of etmv4 devices. */ struct etmv4_drvdata { + struct clk *pclk; void __iomem *base; struct coresight_device *csdev; spinlock_t spinlock; diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c index 3e2e135cb8f6..9d550f5697fa 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -9,9 +9,7 @@ #include <linux/slab.h> #include <linux/clk.h> #include <linux/of.h> -#include <linux/of_address.h> #include <linux/of_graph.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/amba/bus.h> #include <linux/coresight.h> @@ -494,19 +492,18 @@ static inline bool acpi_validate_dsd_graph(const union acpi_object *graph) /* acpi_get_dsd_graph - Find the _DSD Graph property for the given device. */ static const union acpi_object * -acpi_get_dsd_graph(struct acpi_device *adev) +acpi_get_dsd_graph(struct acpi_device *adev, struct acpi_buffer *buf) { int i; - struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER }; acpi_status status; const union acpi_object *dsd; status = acpi_evaluate_object_typed(adev->handle, "_DSD", NULL, - &buf, ACPI_TYPE_PACKAGE); + buf, ACPI_TYPE_PACKAGE); if (ACPI_FAILURE(status)) return NULL; - dsd = buf.pointer; + dsd = buf->pointer; /* * _DSD property consists tuples { Prop_UUID, Package() } @@ -557,12 +554,12 @@ acpi_validate_coresight_graph(const union acpi_object *cs_graph) * returns NULL. */ static const union acpi_object * -acpi_get_coresight_graph(struct acpi_device *adev) +acpi_get_coresight_graph(struct acpi_device *adev, struct acpi_buffer *buf) { const union acpi_object *graph_list, *graph; int i, nr_graphs; - graph_list = acpi_get_dsd_graph(adev); + graph_list = acpi_get_dsd_graph(adev, buf); if (!graph_list) return graph_list; @@ -663,18 +660,24 @@ static int acpi_coresight_parse_graph(struct device *dev, struct acpi_device *adev, struct coresight_platform_data *pdata) { + int ret = 0; int i, nlinks; const union acpi_object *graph; struct coresight_connection conn, zero_conn = {}; struct coresight_connection *new_conn; + struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER, NULL }; - graph = acpi_get_coresight_graph(adev); + graph = acpi_get_coresight_graph(adev, &buf); + /* + * There are no graph connections, which is fine for some components. + * e.g., ETE + */ if (!graph) - return -ENOENT; + goto free; nlinks = graph->package.elements[2].integer.value; if (!nlinks) - return 0; + goto free; for (i = 0; i < nlinks; i++) { const union acpi_object *link = &graph->package.elements[3 + i]; @@ -682,17 +685,28 @@ static int acpi_coresight_parse_graph(struct device *dev, conn = zero_conn; dir = acpi_coresight_parse_link(adev, link, &conn); - if (dir < 0) - return dir; + if (dir < 0) { + ret = dir; + goto free; + } if (dir == ACPI_CORESIGHT_LINK_MASTER) { new_conn = coresight_add_out_conn(dev, pdata, &conn); - if (IS_ERR(new_conn)) - return PTR_ERR(new_conn); + if (IS_ERR(new_conn)) { + ret = PTR_ERR(new_conn); + goto free; + } } } - return 0; +free: + /* + * When ACPI fails to alloc a buffer, it will free the buffer + * created via ACPI_ALLOCATE_BUFFER and set to NULL. + * ACPI_FREE can handle NULL pointers, so free it directly. + */ + ACPI_FREE(buf.pointer); + return ret; } /* diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 79d8c64eac49..7406b65e2cdd 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -452,7 +452,7 @@ static int tmc_set_etf_buffer(struct coresight_device *csdev, return -EINVAL; /* wrap head around to the amount of space we have */ - head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); + head = handle->head & (((unsigned long)buf->nr_pages << PAGE_SHIFT) - 1); /* find the page to write to */ buf->cur = head / PAGE_SIZE; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 766325de0e29..66dc5f97a009 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -45,7 +45,8 @@ struct etr_perf_buffer { }; /* Convert the perf index to an offset within the ETR buffer */ -#define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT)) +#define PERF_IDX2OFF(idx, buf) \ + ((idx) % ((unsigned long)(buf)->nr_pages << PAGE_SHIFT)) /* Lower limit for ETR hardware buffer */ #define TMC_ETR_PERF_MIN_BUF_SIZE SZ_1M @@ -1267,7 +1268,7 @@ alloc_etr_buf(struct tmc_drvdata *drvdata, struct perf_event *event, * than the size requested via sysfs. */ if ((nr_pages << PAGE_SHIFT) > drvdata->size) { - etr_buf = tmc_alloc_etr_buf(drvdata, (nr_pages << PAGE_SHIFT), + etr_buf = tmc_alloc_etr_buf(drvdata, ((ssize_t)nr_pages << PAGE_SHIFT), 0, node, NULL); if (!IS_ERR(etr_buf)) goto done; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index b97da39652d2..0ee48c5ba764 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -325,7 +325,7 @@ ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, static inline unsigned long tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) { - return sg_table->data_pages.nr_pages << PAGE_SHIFT; + return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT; } struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c index 7720619909d6..e20c1c6acc73 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -1225,6 +1225,16 @@ static void arm_trbe_enable_cpu(void *info) enable_percpu_irq(drvdata->irq, IRQ_TYPE_NONE); } +static void arm_trbe_disable_cpu(void *info) +{ + struct trbe_drvdata *drvdata = info; + struct trbe_cpudata *cpudata = this_cpu_ptr(drvdata->cpudata); + + disable_percpu_irq(drvdata->irq); + trbe_reset_local(cpudata); +} + + static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cpu) { struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); @@ -1244,10 +1254,13 @@ static void arm_trbe_register_coresight_cpu(struct trbe_drvdata *drvdata, int cp if (!desc.name) goto cpu_clear; + desc.pdata = coresight_get_platform_data(dev); + if (IS_ERR(desc.pdata)) + goto cpu_clear; + desc.type = CORESIGHT_DEV_TYPE_SINK; desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM; desc.ops = &arm_trbe_cs_ops; - desc.pdata = dev_get_platdata(dev); desc.groups = arm_trbe_groups; desc.dev = dev; trbe_csdev = coresight_register(&desc); @@ -1326,18 +1339,12 @@ cpu_clear: cpumask_clear_cpu(cpu, &drvdata->supported_cpus); } -static void arm_trbe_remove_coresight_cpu(void *info) +static void arm_trbe_remove_coresight_cpu(struct trbe_drvdata *drvdata, int cpu) { - int cpu = smp_processor_id(); - struct trbe_drvdata *drvdata = info; - struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); struct coresight_device *trbe_csdev = coresight_get_percpu_sink(cpu); - disable_percpu_irq(drvdata->irq); - trbe_reset_local(cpudata); if (trbe_csdev) { coresight_unregister(trbe_csdev); - cpudata->drvdata = NULL; coresight_set_percpu_sink(cpu, NULL); } } @@ -1366,8 +1373,10 @@ static int arm_trbe_remove_coresight(struct trbe_drvdata *drvdata) { int cpu; - for_each_cpu(cpu, &drvdata->supported_cpus) - smp_call_function_single(cpu, arm_trbe_remove_coresight_cpu, drvdata, 1); + for_each_cpu(cpu, &drvdata->supported_cpus) { + smp_call_function_single(cpu, arm_trbe_disable_cpu, drvdata, 1); + arm_trbe_remove_coresight_cpu(drvdata, cpu); + } free_percpu(drvdata->cpudata); return 0; } @@ -1406,12 +1415,8 @@ static int arm_trbe_cpu_teardown(unsigned int cpu, struct hlist_node *node) { struct trbe_drvdata *drvdata = hlist_entry_safe(node, struct trbe_drvdata, hotplug_node); - if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) { - struct trbe_cpudata *cpudata = per_cpu_ptr(drvdata->cpudata, cpu); - - disable_percpu_irq(drvdata->irq); - trbe_reset_local(cpudata); - } + if (cpumask_test_cpu(cpu, &drvdata->supported_cpus)) + arm_trbe_disable_cpu(drvdata); return 0; } @@ -1479,7 +1484,6 @@ static void arm_trbe_remove_irq(struct trbe_drvdata *drvdata) static int arm_trbe_device_probe(struct platform_device *pdev) { - struct coresight_platform_data *pdata; struct trbe_drvdata *drvdata; struct device *dev = &pdev->dev; int ret; @@ -1494,12 +1498,7 @@ static int arm_trbe_device_probe(struct platform_device *pdev) if (!drvdata) return -ENOMEM; - pdata = coresight_get_platform_data(dev); - if (IS_ERR(pdata)) - return PTR_ERR(pdata); - dev_set_drvdata(dev, drvdata); - dev->platform_data = pdata; drvdata->pdev = pdev; ret = arm_trbe_probe_irq(pdev, drvdata); if (ret) diff --git a/drivers/hwtracing/coresight/coresight-trbe.h b/drivers/hwtracing/coresight/coresight-trbe.h index 77cbb5c63878..e915e749be55 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.h +++ b/drivers/hwtracing/coresight/coresight-trbe.h @@ -23,7 +23,7 @@ static inline bool is_trbe_available(void) unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0, ID_AA64DFR0_EL1_TraceBuffer_SHIFT); - return trbe >= 0b0001; + return trbe >= ID_AA64DFR0_EL1_TraceBuffer_IMP; } static inline bool is_trbe_enabled(void) diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c index ba081b6d2435..49ea1b0f7489 100644 --- a/drivers/hwtracing/ptt/hisi_ptt.c +++ b/drivers/hwtracing/ptt/hisi_ptt.c @@ -618,13 +618,13 @@ static int hisi_ptt_notifier_call(struct notifier_block *nb, unsigned long actio if (!root_port) return 0; - port_devid = PCI_DEVID(root_port->bus->number, root_port->devfn); + port_devid = pci_dev_id(root_port); if (port_devid < hisi_ptt->lower_bdf || port_devid > hisi_ptt->upper_bdf) return 0; info.is_port = pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT; - info.devid = PCI_DEVID(pdev->bus->number, pdev->devfn); + info.devid = pci_dev_id(pdev); switch (action) { case BUS_NOTIFY_ADD_DEVICE: @@ -664,7 +664,7 @@ static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data) if (!root_port) return 0; - port_devid = PCI_DEVID(root_port->bus->number, root_port->devfn); + port_devid = pci_dev_id(root_port); if (port_devid < hisi_ptt->lower_bdf || port_devid > hisi_ptt->upper_bdf) return 0; @@ -674,7 +674,7 @@ static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data) * should be partial initialized and users would know which filter fails * through the log. Other functions of PTT device are still available. */ - filter = hisi_ptt_alloc_add_filter(hisi_ptt, PCI_DEVID(pdev->bus->number, pdev->devfn), + filter = hisi_ptt_alloc_add_filter(hisi_ptt, pci_dev_id(pdev), pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT); if (!filter) return -ENOMEM; diff --git a/drivers/iio/accel/adxl313_i2c.c b/drivers/iio/accel/adxl313_i2c.c index 524327ea3663..a4cf0cf2c5aa 100644 --- a/drivers/iio/accel/adxl313_i2c.c +++ b/drivers/iio/accel/adxl313_i2c.c @@ -40,8 +40,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = { static const struct i2c_device_id adxl313_i2c_id[] = { { .name = "adxl312", .driver_data = (kernel_ulong_t)&adxl31x_chip_info[ADXL312] }, - { .name = "adxl313", .driver_data = (kernel_ulong_t)&adxl31x_chip_info[ADXL312] }, - { .name = "adxl314", .driver_data = (kernel_ulong_t)&adxl31x_chip_info[ADXL312] }, + { .name = "adxl313", .driver_data = (kernel_ulong_t)&adxl31x_chip_info[ADXL313] }, + { .name = "adxl314", .driver_data = (kernel_ulong_t)&adxl31x_chip_info[ADXL314] }, { } }; @@ -65,9 +65,7 @@ static int adxl313_i2c_probe(struct i2c_client *client) * Retrieves device specific data as a pointer to a * adxl313_chip_info structure */ - chip_data = device_get_match_data(&client->dev); - if (!chip_data) - chip_data = (const struct adxl313_chip_info *)i2c_match_id(adxl313_i2c_id, client)->driver_data; + chip_data = i2c_get_match_data(client); regmap = devm_regmap_init_i2c(client, &adxl31x_i2c_regmap_config[chip_data->type]); diff --git a/drivers/iio/accel/adxl355_i2c.c b/drivers/iio/accel/adxl355_i2c.c index d5beea61479d..32398cde9608 100644 --- a/drivers/iio/accel/adxl355_i2c.c +++ b/drivers/iio/accel/adxl355_i2c.c @@ -24,19 +24,10 @@ static int adxl355_i2c_probe(struct i2c_client *client) { struct regmap *regmap; const struct adxl355_chip_info *chip_data; - const struct i2c_device_id *adxl355; - chip_data = device_get_match_data(&client->dev); - if (!chip_data) { - adxl355 = to_i2c_driver(client->dev.driver)->id_table; - if (!adxl355) - return -EINVAL; - - chip_data = (void *)i2c_match_id(adxl355, client)->driver_data; - - if (!chip_data) - return -EINVAL; - } + chip_data = i2c_get_match_data(client); + if (!chip_data) + return -ENODEV; regmap = devm_regmap_init_i2c(client, &adxl355_i2c_regmap_config); if (IS_ERR(regmap)) { diff --git a/drivers/iio/accel/adxl372_spi.c b/drivers/iio/accel/adxl372_spi.c index 2bd267a22f29..75a88f16c6c9 100644 --- a/drivers/iio/accel/adxl372_spi.c +++ b/drivers/iio/accel/adxl372_spi.c @@ -8,7 +8,6 @@ #include <linux/module.h> #include <linux/regmap.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/spi/spi.h> #include "adxl372.h" diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c index e8ab0d249351..13439f52d26d 100644 --- a/drivers/iio/accel/bma180.c +++ b/drivers/iio/accel/bma180.c @@ -16,7 +16,6 @@ #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/delay.h> -#include <linux/of_device.h> #include <linux/of.h> #include <linux/bitops.h> #include <linux/regulator/consumer.h> diff --git a/drivers/iio/accel/da280.c b/drivers/iio/accel/da280.c index 2f27a5ded94c..572bfe9694b0 100644 --- a/drivers/iio/accel/da280.c +++ b/drivers/iio/accel/da280.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * IIO driver for the MiraMEMS DA280 3-axis accelerometer and + * IIO driver for the MiraMEMS DA217 and DA280 3-axis accelerometer and * IIO driver for the MiraMEMS DA226 2-axis accelerometer * * Copyright (c) 2016 Hans de Goede <hdegoede@redhat.com> @@ -23,7 +23,7 @@ #define DA280_MODE_ENABLE 0x1e #define DA280_MODE_DISABLE 0x9e -enum da280_chipset { da226, da280 }; +enum da280_chipset { da217, da226, da280 }; /* * a value of + or -4096 corresponds to + or - 1G @@ -134,7 +134,10 @@ static int da280_probe(struct i2c_client *client) chip = id->driver_data; } - if (chip == da226) { + if (chip == da217) { + indio_dev->name = "da217"; + indio_dev->num_channels = 3; + } else if (chip == da226) { indio_dev->name = "da226"; indio_dev->num_channels = 2; } else { @@ -166,12 +169,14 @@ static int da280_resume(struct device *dev) static DEFINE_SIMPLE_DEV_PM_OPS(da280_pm_ops, da280_suspend, da280_resume); static const struct acpi_device_id da280_acpi_match[] = { + {"NSA2513", da217}, {"MIRAACC", da280}, {}, }; MODULE_DEVICE_TABLE(acpi, da280_acpi_match); static const struct i2c_device_id da280_i2c_id[] = { + { "da217", da217 }, { "da226", da226 }, { "da280", da280 }, {} diff --git a/drivers/iio/accel/kxsd9-spi.c b/drivers/iio/accel/kxsd9-spi.c index 07f14a9f22c7..1719a9f1d90a 100644 --- a/drivers/iio/accel/kxsd9-spi.c +++ b/drivers/iio/accel/kxsd9-spi.c @@ -2,7 +2,6 @@ #include <linux/device.h> #include <linux/kernel.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/spi/spi.h> #include <linux/module.h> #include <linux/slab.h> diff --git a/drivers/iio/accel/mma8452.c b/drivers/iio/accel/mma8452.c index 6e7399e72221..f42a88711486 100644 --- a/drivers/iio/accel/mma8452.c +++ b/drivers/iio/accel/mma8452.c @@ -28,7 +28,7 @@ #include <linux/iio/triggered_buffer.h> #include <linux/iio/events.h> #include <linux/delay.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/of_irq.h> #include <linux/pm_runtime.h> #include <linux/regulator/consumer.h> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index dc14bde31ac1..517b3db114b8 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1116,7 +1116,7 @@ config STMPE_ADC built-in ADC block (stmpe811). config SUN4I_GPADC - tristate "Support for the Allwinner SoCs GPADC" + tristate "Allwinner A10/A13/A31 and similar GPADCs driver" depends on IIO depends on MFD_SUN4I_GPADC || MACH_SUN8I depends on THERMAL || !THERMAL_OF @@ -1134,6 +1134,16 @@ config SUN4I_GPADC To compile this driver as a module, choose M here: the module will be called sun4i-gpadc-iio. +config SUN20I_GPADC + tristate "Allwinner D1/T113s/T507/R329 and similar GPADCs driver" + depends on ARCH_SUNXI || COMPILE_TEST + help + Say yes here to build support for Allwinner (D1, T113, T507 and R329) + SoCs GPADC. This ADC provides up to 16 channels. + + To compile this driver as a module, choose M here: the module will be + called sun20i-gpadc-iio. + config TI_ADC081C tristate "Texas Instruments ADC081C/ADC101C/ADC121C family" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index eb6e891790fb..2facf979327d 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -96,6 +96,7 @@ obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o obj-$(CONFIG_SPEAR_ADC) += spear_adc.o obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o +obj-$(CONFIG_SUN20I_GPADC) += sun20i-gpadc-iio.o obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o obj-$(CONFIG_STM32_DFSDM_CORE) += stm32-dfsdm-core.o diff --git a/drivers/iio/adc/ab8500-gpadc.c b/drivers/iio/adc/ab8500-gpadc.c index 4fa2126a354b..3b1bdd0b531d 100644 --- a/drivers/iio/adc/ab8500-gpadc.c +++ b/drivers/iio/adc/ab8500-gpadc.c @@ -1099,14 +1099,12 @@ static int ab8500_gpadc_probe(struct platform_device *pdev) gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END"); if (gpadc->irq_sw < 0) - return dev_err_probe(dev, gpadc->irq_sw, - "failed to get platform sw_conv_end irq\n"); + return gpadc->irq_sw; if (is_ab8500(gpadc->ab8500)) { gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END"); if (gpadc->irq_hw < 0) - return dev_err_probe(dev, gpadc->irq_hw, - "failed to get platform hw_conv_end irq\n"); + return gpadc->irq_hw; } else { gpadc->irq_hw = 0; } diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 050a2fbf5c49..b9b206fcd748 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include <linux/kfifo.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/regulator/consumer.h> #include <linux/spi/spi.h> diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index 7bc3ebfe8081..69d1103b9508 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -16,7 +16,7 @@ #include <linux/err.h> #include <linux/sched.h> #include <linux/delay.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> @@ -402,8 +402,8 @@ static int ad7192_setup(struct iio_dev *indio_dev, struct device_node *np) id &= AD7192_ID_MASK; if (id != st->chip_info->chip_id) - dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", - id); + dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X != 0x%X)\n", + id, st->chip_info->chip_id); st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | AD7192_MODE_CLKSRC(st->clock_sel) | @@ -561,9 +561,8 @@ static ssize_t ad7192_show_filter_avail(struct device *dev, ad7192_get_available_filter_freq(st, freq_avail); for (i = 0; i < ARRAY_SIZE(freq_avail); i++) - len += scnprintf(buf + len, PAGE_SIZE - len, - "%d.%d ", freq_avail[i] / 1000, - freq_avail[i] % 1000); + len += sysfs_emit_at(buf, len, "%d.%03d ", freq_avail[i] / 1000, + freq_avail[i] % 1000); buf[len - 1] = '\n'; @@ -972,11 +971,6 @@ static void ad7192_reg_disable(void *reg) regulator_disable(reg); } -static void ad7192_clk_disable(void *clk) -{ - clk_disable_unprepare(clk); -} - static int ad7192_probe(struct spi_device *spi) { struct ad7192_state *st; @@ -1036,7 +1030,9 @@ static int ad7192_probe(struct spi_device *spi) else indio_dev->info = &ad7192_info; - ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); + ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); + if (ret) + return ret; ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); if (ret) @@ -1044,7 +1040,7 @@ static int ad7192_probe(struct spi_device *spi) st->fclk = AD7192_INT_FREQ_MHZ; - st->mclk = devm_clk_get_optional(&spi->dev, "mclk"); + st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk"); if (IS_ERR(st->mclk)) return PTR_ERR(st->mclk); @@ -1052,15 +1048,6 @@ static int ad7192_probe(struct spi_device *spi) if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || st->clock_sel == AD7192_CLK_EXT_MCLK2) { - ret = clk_prepare_enable(st->mclk); - if (ret < 0) - return ret; - - ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable, - st->mclk); - if (ret) - return ret; - st->fclk = clk_get_rate(st->mclk); if (!ad7192_valid_external_frequency(st->fclk)) { dev_err(&spi->dev, diff --git a/drivers/iio/adc/ad9467.c b/drivers/iio/adc/ad9467.c index 0621cf59d614..39eccc28debe 100644 --- a/drivers/iio/adc/ad9467.c +++ b/drivers/iio/adc/ad9467.c @@ -13,7 +13,7 @@ #include <linux/err.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/iio/iio.h> diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c index e8a8ea4140f1..aff0532a974a 100644 --- a/drivers/iio/adc/adi-axi-adc.c +++ b/drivers/iio/adc/adi-axi-adc.c @@ -11,8 +11,9 @@ #include <linux/io.h> #include <linux/delay.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> +#include <linux/property.h> #include <linux/slab.h> #include <linux/iio/iio.h> diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c index 366e252ebeb0..de6650f9c4b1 100644 --- a/drivers/iio/adc/at91_adc.c +++ b/drivers/iio/adc/at91_adc.c @@ -16,7 +16,6 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/sched.h> #include <linux/slab.h> diff --git a/drivers/iio/adc/bcm_iproc_adc.c b/drivers/iio/adc/bcm_iproc_adc.c index 44e1e53ada72..0d6885413a7e 100644 --- a/drivers/iio/adc/bcm_iproc_adc.c +++ b/drivers/iio/adc/bcm_iproc_adc.c @@ -540,8 +540,8 @@ static int iproc_adc_probe(struct platform_device *pdev) } adc_priv->irqno = platform_get_irq(pdev, 0); - if (adc_priv->irqno <= 0) - return -ENODEV; + if (adc_priv->irqno < 0) + return adc_priv->irqno; ret = regmap_update_bits(adc_priv->regmap, IPROC_REGCTL2, IPROC_ADC_AUXIN_SCAN_ENA, 0); diff --git a/drivers/iio/adc/cc10001_adc.c b/drivers/iio/adc/cc10001_adc.c index 2cde4b44fc6e..a432342348ab 100644 --- a/drivers/iio/adc/cc10001_adc.c +++ b/drivers/iio/adc/cc10001_adc.c @@ -9,7 +9,6 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <linux/slab.h> diff --git a/drivers/iio/adc/imx7d_adc.c b/drivers/iio/adc/imx7d_adc.c index 22da81bac97f..828d3fea6d43 100644 --- a/drivers/iio/adc/imx7d_adc.c +++ b/drivers/iio/adc/imx7d_adc.c @@ -496,7 +496,7 @@ static int imx7d_adc_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) - return dev_err_probe(dev, irq, "Failed getting irq\n"); + return irq; info->clk = devm_clk_get(dev, "adc"); if (IS_ERR(info->clk)) diff --git a/drivers/iio/adc/ina2xx-adc.c b/drivers/iio/adc/ina2xx-adc.c index aea83f369437..9e52207352fb 100644 --- a/drivers/iio/adc/ina2xx-adc.c +++ b/drivers/iio/adc/ina2xx-adc.c @@ -28,7 +28,7 @@ #include <linux/iio/sysfs.h> #include <linux/kthread.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/regmap.h> #include <linux/sched/task.h> #include <linux/util_macros.h> diff --git a/drivers/iio/adc/lpc32xx_adc.c b/drivers/iio/adc/lpc32xx_adc.c index 732c924a976d..e34ed7dacd89 100644 --- a/drivers/iio/adc/lpc32xx_adc.c +++ b/drivers/iio/adc/lpc32xx_adc.c @@ -176,8 +176,8 @@ static int lpc32xx_adc_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -ENXIO; + if (irq < 0) + return irq; retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0, LPC32XXAD_NAME, st); diff --git a/drivers/iio/adc/men_z188_adc.c b/drivers/iio/adc/men_z188_adc.c index adc5ceaef8c9..198c7e68e0cf 100644 --- a/drivers/iio/adc/men_z188_adc.c +++ b/drivers/iio/adc/men_z188_adc.c @@ -161,7 +161,6 @@ MODULE_DEVICE_TABLE(mcb, men_z188_ids); static struct mcb_driver men_z188_driver = { .driver = { .name = "z188-adc", - .owner = THIS_MODULE, }, .probe = men_z188_probe, .remove = men_z188_remove, diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index eb78a6f17fd0..320e3e7e3d4d 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -17,7 +17,6 @@ #include <linux/interrupt.h> #include <linux/of.h> #include <linux/of_irq.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> @@ -156,6 +155,10 @@ */ #define MESON_SAR_ADC_REG11 0x2c #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) + #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6) + #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5) + #define MESON_SAR_ADC_REG11_EOC BIT(1) + #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0) #define MESON_SAR_ADC_REG13 0x34 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8) @@ -163,6 +166,7 @@ #define MESON_SAR_ADC_MAX_FIFO_SIZE 32 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */ #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6 +#define MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL 7 #define MESON_SAR_ADC_TEMP_OFFSET 27 /* temperature sensor calibration information in eFuse */ @@ -202,29 +206,22 @@ .datasheet_name = "TEMP_SENSOR", \ } -static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { - MESON_SAR_ADC_CHAN(0), - MESON_SAR_ADC_CHAN(1), - MESON_SAR_ADC_CHAN(2), - MESON_SAR_ADC_CHAN(3), - MESON_SAR_ADC_CHAN(4), - MESON_SAR_ADC_CHAN(5), - MESON_SAR_ADC_CHAN(6), - MESON_SAR_ADC_CHAN(7), - IIO_CHAN_SOFT_TIMESTAMP(8), -}; +#define MESON_SAR_ADC_MUX(_chan, _sel) { \ + .type = IIO_VOLTAGE, \ + .channel = _chan, \ + .indexed = 1, \ + .address = MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \ + BIT(IIO_CHAN_INFO_CALIBSCALE), \ + .datasheet_name = "SAR_ADC_MUX_"#_sel, \ +} -static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = { - MESON_SAR_ADC_CHAN(0), - MESON_SAR_ADC_CHAN(1), - MESON_SAR_ADC_CHAN(2), - MESON_SAR_ADC_CHAN(3), - MESON_SAR_ADC_CHAN(4), - MESON_SAR_ADC_CHAN(5), - MESON_SAR_ADC_CHAN(6), - MESON_SAR_ADC_CHAN(7), - MESON_SAR_ADC_TEMP_CHAN(8), - IIO_CHAN_SOFT_TIMESTAMP(9), +enum meson_sar_adc_vref_sel { + VREF_CALIBATION_VOLTAGE = 0, + VREF_VDDA = 1, }; enum meson_sar_adc_avg_mode { @@ -249,6 +246,72 @@ enum meson_sar_adc_chan7_mux_sel { CHAN7_MUX_CH7_INPUT = 0x7, }; +enum meson_sar_adc_channel_index { + NUM_CHAN_0, + NUM_CHAN_1, + NUM_CHAN_2, + NUM_CHAN_3, + NUM_CHAN_4, + NUM_CHAN_5, + NUM_CHAN_6, + NUM_CHAN_7, + NUM_CHAN_TEMP, + NUM_MUX_0_VSS, + NUM_MUX_1_VDD_DIV4, + NUM_MUX_2_VDD_DIV2, + NUM_MUX_3_VDD_MUL3_DIV4, + NUM_MUX_4_VDD, +}; + +static enum meson_sar_adc_chan7_mux_sel chan7_mux_values[] = { + CHAN7_MUX_VSS, + CHAN7_MUX_VDD_DIV4, + CHAN7_MUX_VDD_DIV2, + CHAN7_MUX_VDD_MUL3_DIV4, + CHAN7_MUX_VDD, +}; + +static const char * const chan7_mux_names[] = { + [CHAN7_MUX_VSS] = "gnd", + [CHAN7_MUX_VDD_DIV4] = "0.25vdd", + [CHAN7_MUX_VDD_DIV2] = "0.5vdd", + [CHAN7_MUX_VDD_MUL3_DIV4] = "0.75vdd", + [CHAN7_MUX_VDD] = "vdd", +}; + +static const struct iio_chan_spec meson_sar_adc_iio_channels[] = { + MESON_SAR_ADC_CHAN(NUM_CHAN_0), + MESON_SAR_ADC_CHAN(NUM_CHAN_1), + MESON_SAR_ADC_CHAN(NUM_CHAN_2), + MESON_SAR_ADC_CHAN(NUM_CHAN_3), + MESON_SAR_ADC_CHAN(NUM_CHAN_4), + MESON_SAR_ADC_CHAN(NUM_CHAN_5), + MESON_SAR_ADC_CHAN(NUM_CHAN_6), + MESON_SAR_ADC_CHAN(NUM_CHAN_7), + MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0), + MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1), + MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2), + MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3), + MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4), +}; + +static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = { + MESON_SAR_ADC_CHAN(NUM_CHAN_0), + MESON_SAR_ADC_CHAN(NUM_CHAN_1), + MESON_SAR_ADC_CHAN(NUM_CHAN_2), + MESON_SAR_ADC_CHAN(NUM_CHAN_3), + MESON_SAR_ADC_CHAN(NUM_CHAN_4), + MESON_SAR_ADC_CHAN(NUM_CHAN_5), + MESON_SAR_ADC_CHAN(NUM_CHAN_6), + MESON_SAR_ADC_CHAN(NUM_CHAN_7), + MESON_SAR_ADC_TEMP_CHAN(NUM_CHAN_TEMP), + MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0), + MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1), + MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2), + MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3), + MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4), +}; + struct meson_sar_adc_param { bool has_bl30_integration; unsigned long clock_rate; @@ -258,6 +321,13 @@ struct meson_sar_adc_param { u8 temperature_trimming_bits; unsigned int temperature_multiplier; unsigned int temperature_divider; + u8 disable_ring_counter; + bool has_reg11; + bool has_vref_select; + u8 vref_select; + u8 cmv_select; + u8 adc_eoc; + enum meson_sar_adc_vref_sel vref_volatge; }; struct meson_sar_adc_data { @@ -285,6 +355,7 @@ struct meson_sar_adc_priv { bool temperature_sensor_calibrated; u8 temperature_sensor_coefficient; u16 temperature_sensor_adc_val; + enum meson_sar_adc_chan7_mux_sel chan7_mux_sel; }; static const struct regmap_config meson_sar_adc_regmap_config_gxbb = { @@ -301,6 +372,17 @@ static const struct regmap_config meson_sar_adc_regmap_config_meson8 = { .max_register = MESON_SAR_ADC_DELTA_10, }; +static const struct iio_chan_spec * +find_channel_by_num(struct iio_dev *indio_dev, int num) +{ + int i; + + for (i = 0; i < indio_dev->num_channels; i++) + if (indio_dev->channels[i].channel == num) + return &indio_dev->channels[i]; + return NULL; +} + static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); @@ -338,6 +420,21 @@ static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev) 1, 10000); } +static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, + enum meson_sar_adc_chan7_mux_sel sel) +{ + struct meson_sar_adc_priv *priv = iio_priv(indio_dev); + u32 regval; + + regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, + MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); + + usleep_range(10, 20); + + priv->chan7_mux_sel = sel; +} + static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, int *val) @@ -431,20 +528,16 @@ static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev, regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval); - } -} - -static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev, - enum meson_sar_adc_chan7_mux_sel sel) -{ - struct meson_sar_adc_priv *priv = iio_priv(indio_dev); - u32 regval; - - regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel); - regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, - MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval); + } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) { + enum meson_sar_adc_chan7_mux_sel sel; - usleep_range(10, 20); + if (chan->channel == NUM_CHAN_7) + sel = CHAN7_MUX_CH7_INPUT; + else + sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS]; + if (sel != priv->chan7_mux_sel) + meson_sar_adc_set_chan7_mux(indio_dev, sel); + } } static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev) @@ -821,6 +914,22 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, regval); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW); + + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW); + + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW); + + regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW, + MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW); + /* * set up the input channel muxes in MESON_SAR_ADC_AUX_SW * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable @@ -873,6 +982,35 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) MESON_SAR_ADC_DELTA_10_TS_REVE0, 0); } + regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN, + priv->param->disable_ring_counter); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, + MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN, + regval); + + if (priv->param->has_reg11) { + regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, + MESON_SAR_ADC_REG11_EOC, regval); + + if (priv->param->has_vref_select) { + regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL, + priv->param->vref_select); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, + MESON_SAR_ADC_REG11_VREF_SEL, regval); + } + + regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE, + priv->param->vref_volatge); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, + MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval); + + regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL, + priv->param->cmv_select); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, + MESON_SAR_ADC_REG11_CMV_SEL, regval); + } + ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); if (ret) return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n"); @@ -1006,7 +1144,8 @@ static int meson_sar_adc_calib(struct iio_dev *indio_dev) meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4); usleep_range(10, 20); ret = meson_sar_adc_get_sample(indio_dev, - &indio_dev->channels[7], + find_channel_by_num(indio_dev, + NUM_MUX_1_VDD_DIV4), MEAN_AVERAGING, EIGHT_SAMPLES, &value0); if (ret < 0) goto out; @@ -1014,7 +1153,8 @@ static int meson_sar_adc_calib(struct iio_dev *indio_dev) meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4); usleep_range(10, 20); ret = meson_sar_adc_get_sample(indio_dev, - &indio_dev->channels[7], + find_channel_by_num(indio_dev, + NUM_MUX_3_VDD_MUL3_DIV4), MEAN_AVERAGING, EIGHT_SAMPLES, &value1); if (ret < 0) goto out; @@ -1035,8 +1175,23 @@ out: return ret; } +static int read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + char *label) +{ + if (chan->type == IIO_TEMP) + return sprintf(label, "temp-sensor\n"); + if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS) + return sprintf(label, "%s\n", + chan7_mux_names[chan->channel - NUM_MUX_0_VSS]); + if (chan->type == IIO_VOLTAGE) + return sprintf(label, "channel-%d\n", chan->channel); + return 0; +} + static const struct iio_info meson_sar_adc_iio_info = { .read_raw = meson_sar_adc_iio_info_read_raw, + .read_label = read_label, }; static const struct meson_sar_adc_param meson_sar_adc_meson8_param = { @@ -1067,6 +1222,9 @@ static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = { .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 10, + .has_reg11 = true, + .vref_volatge = 1, + .cmv_select = 1, }; static const struct meson_sar_adc_param meson_sar_adc_gxl_param = { @@ -1075,6 +1233,10 @@ static const struct meson_sar_adc_param meson_sar_adc_gxl_param = { .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, + .disable_ring_counter = 1, + .has_reg11 = true, + .vref_volatge = 1, + .cmv_select = 1, }; static const struct meson_sar_adc_param meson_sar_adc_g12a_param = { @@ -1083,6 +1245,11 @@ static const struct meson_sar_adc_param meson_sar_adc_g12a_param = { .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, + .disable_ring_counter = 1, + .has_reg11 = true, + .adc_eoc = 1, + .has_vref_select = true, + .vref_select = VREF_VDDA, }; static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { diff --git a/drivers/iio/adc/npcm_adc.c b/drivers/iio/adc/npcm_adc.c index ba4cd8f49f66..3d9207c160eb 100644 --- a/drivers/iio/adc/npcm_adc.c +++ b/drivers/iio/adc/npcm_adc.c @@ -244,8 +244,8 @@ static int npcm_adc_probe(struct platform_device *pdev) info->adc_sample_hz = clk_get_rate(info->adc_clk) / ((div + 1) * 2); irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - ret = -EINVAL; + if (irq < 0) { + ret = irq; goto err_disable_clk; } diff --git a/drivers/iio/adc/palmas_gpadc.c b/drivers/iio/adc/palmas_gpadc.c index 27b2632c1037..e202ea18af10 100644 --- a/drivers/iio/adc/palmas_gpadc.c +++ b/drivers/iio/adc/palmas_gpadc.c @@ -18,7 +18,6 @@ #include <linux/mfd/palmas.h> #include <linux/completion.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/iio/events.h> #include <linux/iio/iio.h> #include <linux/iio/machine.h> @@ -916,8 +915,7 @@ static int palmas_gpadc_probe(struct platform_device *pdev) adc->irq_auto_0 = platform_get_irq(pdev, 1); if (adc->irq_auto_0 < 0) - return dev_err_probe(adc->dev, adc->irq_auto_0, - "get auto0 irq failed\n"); + return adc->irq_auto_0; ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_0, NULL, palmas_gpadc_irq_auto, IRQF_ONESHOT, @@ -929,8 +927,7 @@ static int palmas_gpadc_probe(struct platform_device *pdev) adc->irq_auto_1 = platform_get_irq(pdev, 2); if (adc->irq_auto_1 < 0) - return dev_err_probe(adc->dev, adc->irq_auto_1, - "get auto1 irq failed\n"); + return adc->irq_auto_1; ret = devm_request_threaded_irq(&pdev->dev, adc->irq_auto_1, NULL, palmas_gpadc_irq_auto, IRQF_ONESHOT, diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index 0a4fd3a46113..b6b612d733ff 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -555,6 +555,8 @@ static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = { SCALE_HW_CALIB_PM5_SMB_TEMP) [ADC5_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_100k_pu", 0, SCALE_HW_CALIB_THERM_100K_PULLUP) + [ADC5_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_100k_pu", 0, + SCALE_HW_CALIB_THERM_100K_PULLUP) [ADC5_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_100k_pu", 0, SCALE_HW_CALIB_THERM_100K_PULLUP) [ADC5_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_100k_pu", 0, diff --git a/drivers/iio/adc/qcom-spmi-iadc.c b/drivers/iio/adc/qcom-spmi-iadc.c index acbda6636dc5..7fb8b2499a1d 100644 --- a/drivers/iio/adc/qcom-spmi-iadc.c +++ b/drivers/iio/adc/qcom-spmi-iadc.c @@ -13,7 +13,6 @@ #include <linux/mutex.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index 4b011f7eddec..dd94667a623b 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -11,7 +11,6 @@ #include <linux/interrupt.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/clk.h> #include <linux/completion.h> #include <linux/delay.h> @@ -467,7 +466,7 @@ static int rockchip_saradc_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) - return dev_err_probe(&pdev->dev, irq, "failed to get irq\n"); + return irq; ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr, 0, dev_name(&pdev->dev), info); diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index ff1fc329bb9b..b4a2e057d80f 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -7,7 +7,6 @@ #include <linux/mutex.h> #include <linux/nvmem-consumer.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> diff --git a/drivers/iio/adc/spear_adc.c b/drivers/iio/adc/spear_adc.c index d93e580b3dc5..ad54ef798109 100644 --- a/drivers/iio/adc/spear_adc.c +++ b/drivers/iio/adc/spear_adc.c @@ -310,8 +310,8 @@ static int spear_adc_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - ret = -EINVAL; + if (irq < 0) { + ret = irq; goto errout2; } diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index 48f02dcc81c1..2f082006550f 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -18,6 +18,8 @@ #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> @@ -723,8 +725,7 @@ static int stm32_adc_probe(struct platform_device *pdev) priv->nb_adc_max = priv->cfg->num_adcs; spin_lock_init(&priv->common.lock); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->common.base = devm_ioremap_resource(&pdev->dev, res); + priv->common.base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->common.base)) return PTR_ERR(priv->common.base); priv->common.phys_base = res->start; diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c index a428bdb567d5..b5cc43d12b6f 100644 --- a/drivers/iio/adc/stm32-dfsdm-adc.c +++ b/drivers/iio/adc/stm32-dfsdm-adc.c @@ -19,7 +19,8 @@ #include <linux/iio/triggered_buffer.h> #include <linux/interrupt.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/iio/adc/stm32-dfsdm-core.c b/drivers/iio/adc/stm32-dfsdm-core.c index 0362df285a57..0f6ebb3061a0 100644 --- a/drivers/iio/adc/stm32-dfsdm-core.c +++ b/drivers/iio/adc/stm32-dfsdm-core.c @@ -12,8 +12,10 @@ #include <linux/iio/sysfs.h> #include <linux/interrupt.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/of_platform.h> #include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/iio/adc/stmpe-adc.c b/drivers/iio/adc/stmpe-adc.c index 67518e460e05..8e56def1c9e5 100644 --- a/drivers/iio/adc/stmpe-adc.c +++ b/drivers/iio/adc/stmpe-adc.c @@ -14,7 +14,7 @@ #include <linux/kernel.h> #include <linux/mfd/stmpe.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/device.h> diff --git a/drivers/iio/adc/sun20i-gpadc-iio.c b/drivers/iio/adc/sun20i-gpadc-iio.c new file mode 100644 index 000000000000..6a893d484cf7 --- /dev/null +++ b/drivers/iio/adc/sun20i-gpadc-iio.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GPADC driver for sunxi platforms (D1, T113-S3 and R329) + * Copyright (c) 2023 Maksim Kiselev <bigunclemax@gmail.com> + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/reset.h> + +#include <linux/iio/iio.h> + +#define SUN20I_GPADC_DRIVER_NAME "sun20i-gpadc" + +/* Register map definition */ +#define SUN20I_GPADC_SR 0x00 +#define SUN20I_GPADC_CTRL 0x04 +#define SUN20I_GPADC_CS_EN 0x08 +#define SUN20I_GPADC_FIFO_INTC 0x0c +#define SUN20I_GPADC_FIFO_INTS 0x10 +#define SUN20I_GPADC_FIFO_DATA 0X14 +#define SUN20I_GPADC_CB_DATA 0X18 +#define SUN20I_GPADC_DATAL_INTC 0x20 +#define SUN20I_GPADC_DATAH_INTC 0x24 +#define SUN20I_GPADC_DATA_INTC 0x28 +#define SUN20I_GPADC_DATAL_INTS 0x30 +#define SUN20I_GPADC_DATAH_INTS 0x34 +#define SUN20I_GPADC_DATA_INTS 0x38 +#define SUN20I_GPADC_CH_CMP_DATA(x) (0x40 + (x) * 4) +#define SUN20I_GPADC_CH_DATA(x) (0x80 + (x) * 4) + +#define SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK BIT(23) +#define SUN20I_GPADC_CTRL_WORK_MODE_MASK GENMASK(19, 18) +#define SUN20I_GPADC_CTRL_ADC_EN_MASK BIT(16) +#define SUN20I_GPADC_CS_EN_ADC_CH(x) BIT(x) +#define SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(x) BIT(x) + +#define SUN20I_GPADC_WORK_MODE_SINGLE 0 + +struct sun20i_gpadc_iio { + void __iomem *regs; + struct completion completion; + int last_channel; + /* + * Lock to protect the device state during a potential concurrent + * read access from userspace. Reading a raw value requires a sequence + * of register writes, then a wait for a completion callback, + * and finally a register read, during which userspace could issue + * another read request. This lock protects a read access from + * ocurring before another one has finished. + */ + struct mutex lock; +}; + +static int sun20i_gpadc_adc_read(struct sun20i_gpadc_iio *info, + struct iio_chan_spec const *chan, int *val) +{ + u32 ctrl; + int ret = IIO_VAL_INT; + + mutex_lock(&info->lock); + + reinit_completion(&info->completion); + + if (info->last_channel != chan->channel) { + info->last_channel = chan->channel; + + /* enable the analog input channel */ + writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel), + info->regs + SUN20I_GPADC_CS_EN); + + /* enable the data irq for input channel */ + writel(SUN20I_GPADC_DATA_INTC_CH_DATA_IRQ_EN(chan->channel), + info->regs + SUN20I_GPADC_DATA_INTC); + } + + /* enable the ADC function */ + ctrl = readl(info->regs + SUN20I_GPADC_CTRL); + ctrl |= FIELD_PREP(SUN20I_GPADC_CTRL_ADC_EN_MASK, 1); + writel(ctrl, info->regs + SUN20I_GPADC_CTRL); + + /* + * According to the datasheet maximum acquire time(TACQ) can be + * (65535+1)/24Mhz and conversion time(CONV_TIME) is always constant + * and equal to 14/24Mhz, so (TACQ+CONV_TIME) <= 2.73125ms. + * A 10ms delay should be enough to make sure an interrupt occurs in + * normal conditions. If it doesn't occur, then there is a timeout. + */ + if (!wait_for_completion_timeout(&info->completion, msecs_to_jiffies(10))) { + ret = -ETIMEDOUT; + goto err_unlock; + } + + /* read the ADC data */ + *val = readl(info->regs + SUN20I_GPADC_CH_DATA(chan->channel)); + +err_unlock: + mutex_unlock(&info->lock); + + return ret; +} + +static int sun20i_gpadc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct sun20i_gpadc_iio *info = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + return sun20i_gpadc_adc_read(info, chan, val); + case IIO_CHAN_INFO_SCALE: + /* value in mv = 1800mV / 4096 raw */ + *val = 1800; + *val2 = 12; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static irqreturn_t sun20i_gpadc_irq_handler(int irq, void *data) +{ + struct sun20i_gpadc_iio *info = data; + + /* clear data interrupt status register */ + writel(GENMASK(31, 0), info->regs + SUN20I_GPADC_DATA_INTS); + + complete(&info->completion); + + return IRQ_HANDLED; +} + +static const struct iio_info sun20i_gpadc_iio_info = { + .read_raw = sun20i_gpadc_read_raw, +}; + +static void sun20i_gpadc_reset_assert(void *data) +{ + struct reset_control *rst = data; + + reset_control_assert(rst); +} + +static int sun20i_gpadc_alloc_channels(struct iio_dev *indio_dev, + struct device *dev) +{ + unsigned int channel; + int num_channels, i, ret; + struct iio_chan_spec *channels; + struct fwnode_handle *node; + + num_channels = device_get_child_node_count(dev); + if (num_channels == 0) + return dev_err_probe(dev, -ENODEV, "no channel children\n"); + + channels = devm_kcalloc(dev, num_channels, sizeof(*channels), + GFP_KERNEL); + if (!channels) + return -ENOMEM; + + i = 0; + device_for_each_child_node(dev, node) { + ret = fwnode_property_read_u32(node, "reg", &channel); + if (ret) { + fwnode_handle_put(node); + return dev_err_probe(dev, ret, "invalid channel number\n"); + } + + channels[i].type = IIO_VOLTAGE; + channels[i].indexed = 1; + channels[i].channel = channel; + channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW); + channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); + + i++; + } + + indio_dev->channels = channels; + indio_dev->num_channels = num_channels; + + return 0; +} + +static int sun20i_gpadc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct iio_dev *indio_dev; + struct sun20i_gpadc_iio *info; + struct reset_control *rst; + struct clk *clk; + int irq; + int ret; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*info)); + if (!indio_dev) + return -ENOMEM; + + info = iio_priv(indio_dev); + info->last_channel = -1; + + mutex_init(&info->lock); + init_completion(&info->completion); + + ret = sun20i_gpadc_alloc_channels(indio_dev, dev); + if (ret) + return ret; + + indio_dev->info = &sun20i_gpadc_iio_info; + indio_dev->name = SUN20I_GPADC_DRIVER_NAME; + + info->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(info->regs)) + return PTR_ERR(info->regs); + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n"); + + rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n"); + + ret = reset_control_deassert(rst); + if (ret) + return dev_err_probe(dev, ret, "failed to deassert reset\n"); + + ret = devm_add_action_or_reset(dev, sun20i_gpadc_reset_assert, rst); + if (ret) + return ret; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, sun20i_gpadc_irq_handler, 0, + dev_name(dev), info); + if (ret) + return dev_err_probe(dev, ret, "failed requesting irq %d\n", irq); + + writel(FIELD_PREP(SUN20I_GPADC_CTRL_ADC_AUTOCALI_EN_MASK, 1) | + FIELD_PREP(SUN20I_GPADC_CTRL_WORK_MODE_MASK, SUN20I_GPADC_WORK_MODE_SINGLE), + info->regs + SUN20I_GPADC_CTRL); + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return dev_err_probe(dev, ret, "could not register the device\n"); + + return 0; +} + +static const struct of_device_id sun20i_gpadc_of_id[] = { + { .compatible = "allwinner,sun20i-d1-gpadc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id); + +static struct platform_driver sun20i_gpadc_driver = { + .driver = { + .name = SUN20I_GPADC_DRIVER_NAME, + .of_match_table = sun20i_gpadc_of_id, + }, + .probe = sun20i_gpadc_probe, +}; +module_platform_driver(sun20i_gpadc_driver); + +MODULE_DESCRIPTION("ADC driver for sunxi platforms"); +MODULE_AUTHOR("Maksim Kiselev <bigunclemax@gmail.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c index a5322550c422..25bba96367a8 100644 --- a/drivers/iio/adc/sun4i-gpadc-iio.c +++ b/drivers/iio/adc/sun4i-gpadc-iio.c @@ -24,7 +24,6 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> diff --git a/drivers/iio/adc/ti-lmp92064.c b/drivers/iio/adc/ti-lmp92064.c index c30ed824924f..84ba5c4a0eea 100644 --- a/drivers/iio/adc/ti-lmp92064.c +++ b/drivers/iio/adc/ti-lmp92064.c @@ -16,7 +16,10 @@ #include <linux/spi/spi.h> #include <linux/iio/iio.h> +#include <linux/iio/buffer.h> #include <linux/iio/driver.h> +#include <linux/iio/triggered_buffer.h> +#include <linux/iio/trigger_consumer.h> #define TI_LMP92064_REG_CONFIG_A 0x0000 #define TI_LMP92064_REG_CONFIG_B 0x0001 @@ -91,6 +94,12 @@ static const struct iio_chan_spec lmp92064_adc_channels[] = { .address = TI_LMP92064_CHAN_INC, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .scan_index = TI_LMP92064_CHAN_INC, + .scan_type = { + .sign = 'u', + .realbits = 12, + .storagebits = 16, + }, .datasheet_name = "INC", }, { @@ -98,8 +107,20 @@ static const struct iio_chan_spec lmp92064_adc_channels[] = { .address = TI_LMP92064_CHAN_INV, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .scan_index = TI_LMP92064_CHAN_INV, + .scan_type = { + .sign = 'u', + .realbits = 12, + .storagebits = 16, + }, .datasheet_name = "INV", }, + IIO_CHAN_SOFT_TIMESTAMP(2), +}; + +static const unsigned long lmp92064_scan_masks[] = { + BIT(TI_LMP92064_CHAN_INC) | BIT(TI_LMP92064_CHAN_INV), + 0 }; static int lmp92064_read_meas(struct lmp92064_adc_priv *priv, u16 *res) @@ -171,6 +192,32 @@ static int lmp92064_read_raw(struct iio_dev *indio_dev, } } +static irqreturn_t lmp92064_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct lmp92064_adc_priv *priv = iio_priv(indio_dev); + struct { + u16 values[2]; + int64_t timestamp __aligned(8); + } data; + int ret; + + memset(&data, 0, sizeof(data)); + + ret = lmp92064_read_meas(priv, data.values); + if (ret) + goto err; + + iio_push_to_buffers_with_timestamp(indio_dev, &data, + iio_get_time_ns(indio_dev)); + +err: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + static int lmp92064_reset(struct lmp92064_adc_priv *priv, struct gpio_desc *gpio_reset) { @@ -301,6 +348,12 @@ static int lmp92064_adc_probe(struct spi_device *spi) indio_dev->channels = lmp92064_adc_channels; indio_dev->num_channels = ARRAY_SIZE(lmp92064_adc_channels); indio_dev->info = &lmp92064_adc_info; + indio_dev->available_scan_masks = lmp92064_scan_masks; + + ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, + lmp92064_trigger_handler, NULL); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup buffered read\n"); return devm_iio_device_register(dev, indio_dev); } diff --git a/drivers/iio/adc/ti_am335x_adc.c b/drivers/iio/adc/ti_am335x_adc.c index 642c5c4895e3..8db7a01cb5fb 100644 --- a/drivers/iio/adc/ti_am335x_adc.c +++ b/drivers/iio/adc/ti_am335x_adc.c @@ -14,7 +14,6 @@ #include <linux/io.h> #include <linux/iio/iio.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/iio/machine.h> #include <linux/iio/driver.h> #include <linux/iopoll.h> diff --git a/drivers/iio/amplifiers/Kconfig b/drivers/iio/amplifiers/Kconfig index f217a2a1e958..b54fe01734b0 100644 --- a/drivers/iio/amplifiers/Kconfig +++ b/drivers/iio/amplifiers/Kconfig @@ -18,6 +18,7 @@ config AD8366 AD8366 Dual-Digital Variable Gain Amplifier (VGA) ADA4961 BiCMOS RF Digital Gain Amplifier (DGA) ADL5240 Digitally controlled variable gain amplifier (VGA) + HMC792A 0.25 dB LSB GaAs MMIC 6-Bit Digital Attenuator HMC1119 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator To compile this driver as a module, choose M here: the diff --git a/drivers/iio/amplifiers/ad8366.c b/drivers/iio/amplifiers/ad8366.c index 8d8c8ea94258..31564afb13a2 100644 --- a/drivers/iio/amplifiers/ad8366.c +++ b/drivers/iio/amplifiers/ad8366.c @@ -5,6 +5,7 @@ * AD8366 Dual-Digital Variable Gain Amplifier (VGA) * ADA4961 BiCMOS RF Digital Gain Amplifier (DGA) * ADL5240 Digitally controlled variable gain amplifier (VGA) + * HMC792A 0.25 dB LSB GaAs MMIC 6-Bit Digital Attenuator * HMC1119 0.25 dB LSB, 7-Bit, Silicon Digital Attenuator * * Copyright 2012-2019 Analog Devices Inc. @@ -28,6 +29,7 @@ enum ad8366_type { ID_AD8366, ID_ADA4961, ID_ADL5240, + ID_HMC792, ID_HMC1119, }; @@ -64,6 +66,10 @@ static struct ad8366_info ad8366_infos[] = { .gain_min = -11500, .gain_max = 20000, }, + [ID_HMC792] = { + .gain_min = -15750, + .gain_max = 0, + }, [ID_HMC1119] = { .gain_min = -31750, .gain_max = 0, @@ -90,6 +96,7 @@ static int ad8366_write(struct iio_dev *indio_dev, case ID_ADL5240: st->data[0] = (ch_a & 0x3F); break; + case ID_HMC792: case ID_HMC1119: st->data[0] = ch_a; break; @@ -127,6 +134,9 @@ static int ad8366_read_raw(struct iio_dev *indio_dev, case ID_ADL5240: gain = 20000 - 31500 + code * 500; break; + case ID_HMC792: + gain = -1 * code * 500; + break; case ID_HMC1119: gain = -1 * code * 250; break; @@ -176,6 +186,9 @@ static int ad8366_write_raw(struct iio_dev *indio_dev, case ID_ADL5240: code = ((gain - 500 - 20000) / 500) & 0x3F; break; + case ID_HMC792: + code = (abs(gain) / 500) & 0x3F; + break; case ID_HMC1119: code = (abs(gain) / 250) & 0x7F; break; @@ -261,6 +274,7 @@ static int ad8366_probe(struct spi_device *spi) break; case ID_ADA4961: case ID_ADL5240: + case ID_HMC792: case ID_HMC1119: st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(st->reset_gpio)) { @@ -314,6 +328,7 @@ static const struct spi_device_id ad8366_id[] = { {"ad8366", ID_AD8366}, {"ada4961", ID_ADA4961}, {"adl5240", ID_ADL5240}, + {"hmc792a", ID_HMC792}, {"hmc1119", ID_HMC1119}, {} }; diff --git a/drivers/iio/cdc/ad7150.c b/drivers/iio/cdc/ad7150.c index d656d2f12755..4c03b9e834b8 100644 --- a/drivers/iio/cdc/ad7150.c +++ b/drivers/iio/cdc/ad7150.c @@ -541,6 +541,7 @@ static int ad7150_probe(struct i2c_client *client) const struct i2c_device_id *id = i2c_client_get_device_id(client); struct ad7150_chip_info *chip; struct iio_dev *indio_dev; + bool use_irq = true; int ret; indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip)); @@ -561,14 +562,13 @@ static int ad7150_probe(struct i2c_client *client) chip->interrupts[0] = fwnode_irq_get(dev_fwnode(&client->dev), 0); if (chip->interrupts[0] < 0) - return chip->interrupts[0]; - if (id->driver_data == AD7150) { + use_irq = false; + else if (id->driver_data == AD7150) { chip->interrupts[1] = fwnode_irq_get(dev_fwnode(&client->dev), 1); if (chip->interrupts[1] < 0) - return chip->interrupts[1]; + use_irq = false; } - if (chip->interrupts[0] && - (id->driver_data == AD7151 || chip->interrupts[1])) { + if (use_irq) { irq_set_status_flags(chip->interrupts[0], IRQ_NOAUTOEN); ret = devm_request_threaded_irq(&client->dev, chip->interrupts[0], diff --git a/drivers/iio/chemical/scd4x.c b/drivers/iio/chemical/scd4x.c index a4f22d926400..ca6b20270711 100644 --- a/drivers/iio/chemical/scd4x.c +++ b/drivers/iio/chemical/scd4x.c @@ -36,6 +36,8 @@ #define SCD4X_WRITE_BUF_SIZE 5 #define SCD4X_FRC_MIN_PPM 0 #define SCD4X_FRC_MAX_PPM 2000 +#define SCD4X_PRESSURE_COMP_MIN_MBAR 700 +#define SCD4X_PRESSURE_COMP_MAX_MBAR 1200 #define SCD4X_READY_MASK 0x01 /*Commands SCD4X*/ @@ -45,6 +47,8 @@ enum scd4x_cmd { CMD_STOP_MEAS = 0x3f86, CMD_SET_TEMP_OFFSET = 0x241d, CMD_GET_TEMP_OFFSET = 0x2318, + CMD_SET_AMB_PRESSURE = 0xe000, + CMD_GET_AMB_PRESSURE = 0xe000, CMD_FRC = 0x362f, CMD_SET_ASC = 0x2416, CMD_GET_ASC = 0x2313, @@ -137,7 +141,8 @@ static int scd4x_read(struct scd4x_state *state, enum scd4x_cmd cmd, * Measurement needs to be stopped before sending commands. * Except for reading measurement and data ready command. */ - if ((cmd != CMD_GET_DATA_READY) && (cmd != CMD_READ_MEAS)) { + if ((cmd != CMD_GET_DATA_READY) && (cmd != CMD_READ_MEAS) && + (cmd != CMD_GET_AMB_PRESSURE)) { ret = scd4x_send_command(state, CMD_STOP_MEAS); if (ret) return ret; @@ -166,7 +171,8 @@ static int scd4x_read(struct scd4x_state *state, enum scd4x_cmd cmd, } /* start measurement */ - if ((cmd != CMD_GET_DATA_READY) && (cmd != CMD_READ_MEAS)) { + if ((cmd != CMD_GET_DATA_READY) && (cmd != CMD_READ_MEAS) && + (cmd != CMD_GET_AMB_PRESSURE)) { ret = scd4x_send_command(state, CMD_START_MEAS); if (ret) return ret; @@ -188,9 +194,11 @@ static int scd4x_write(struct scd4x_state *state, enum scd4x_cmd cmd, uint16_t a buf[4] = crc; /* measurement needs to be stopped before sending commands */ - ret = scd4x_send_command(state, CMD_STOP_MEAS); - if (ret) - return ret; + if (cmd != CMD_SET_AMB_PRESSURE) { + ret = scd4x_send_command(state, CMD_STOP_MEAS); + if (ret) + return ret; + } /* execution time */ msleep_interruptible(500); @@ -200,7 +208,7 @@ static int scd4x_write(struct scd4x_state *state, enum scd4x_cmd cmd, uint16_t a return ret; /* start measurement, except for forced calibration command */ - if (cmd != CMD_FRC) { + if ((cmd != CMD_FRC) && (cmd != CMD_SET_AMB_PRESSURE)) { ret = scd4x_send_command(state, CMD_START_MEAS); if (ret) return ret; @@ -338,6 +346,18 @@ static int scd4x_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: + if (chan->output) { + mutex_lock(&state->lock); + ret = scd4x_read(state, CMD_GET_AMB_PRESSURE, &tmp, sizeof(tmp)); + mutex_unlock(&state->lock); + + if (ret) + return ret; + + *val = be16_to_cpu(tmp); + return IIO_VAL_INT; + } + ret = iio_device_claim_direct_mode(indio_dev); if (ret) return ret; @@ -386,6 +406,25 @@ static int scd4x_read_raw(struct iio_dev *indio_dev, } } +static const int scd4x_pressure_calibbias_available[] = { + SCD4X_PRESSURE_COMP_MIN_MBAR, 1, SCD4X_PRESSURE_COMP_MAX_MBAR, +}; + +static int scd4x_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_RAW: + *vals = scd4x_pressure_calibbias_available; + *type = IIO_VAL_INT; + + return IIO_AVAIL_RANGE; + } + + return -EINVAL; +} + + static int scd4x_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { @@ -399,6 +438,21 @@ static int scd4x_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const mutex_unlock(&state->lock); return ret; + case IIO_CHAN_INFO_RAW: + switch (chan->type) { + case IIO_PRESSURE: + if (val < SCD4X_PRESSURE_COMP_MIN_MBAR || + val > SCD4X_PRESSURE_COMP_MAX_MBAR) + return -EINVAL; + + mutex_lock(&state->lock); + ret = scd4x_write(state, CMD_SET_AMB_PRESSURE, val); + mutex_unlock(&state->lock); + + return ret; + default: + return -EINVAL; + } default: return -EINVAL; } @@ -503,10 +557,23 @@ static const struct iio_info scd4x_info = { .attrs = &scd4x_attr_group, .read_raw = scd4x_read_raw, .write_raw = scd4x_write_raw, + .read_avail = scd4x_read_avail, }; static const struct iio_chan_spec scd4x_channels[] = { { + /* + * this channel is special in a sense we are pretending that + * sensor is able to change measurement chamber pressure but in + * fact we're just setting pressure compensation value + */ + .type = IIO_PRESSURE, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), + .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW), + .output = 1, + .scan_index = -1, + }, + { .type = IIO_CONCENTRATION, .channel2 = IIO_MOD_CO2, .modified = 1, diff --git a/drivers/iio/common/Kconfig b/drivers/iio/common/Kconfig index 0334b4954773..1ccb5ccf3706 100644 --- a/drivers/iio/common/Kconfig +++ b/drivers/iio/common/Kconfig @@ -5,6 +5,7 @@ source "drivers/iio/common/cros_ec_sensors/Kconfig" source "drivers/iio/common/hid-sensors/Kconfig" +source "drivers/iio/common/inv_sensors/Kconfig" source "drivers/iio/common/ms_sensors/Kconfig" source "drivers/iio/common/scmi_sensors/Kconfig" source "drivers/iio/common/ssp_sensors/Kconfig" diff --git a/drivers/iio/common/Makefile b/drivers/iio/common/Makefile index fad40e1e1718..d3e952239a62 100644 --- a/drivers/iio/common/Makefile +++ b/drivers/iio/common/Makefile @@ -10,6 +10,7 @@ # When adding new entries keep the list in alphabetical order obj-y += cros_ec_sensors/ obj-y += hid-sensors/ +obj-y += inv_sensors/ obj-y += ms_sensors/ obj-y += scmi_sensors/ obj-y += ssp_sensors/ diff --git a/drivers/iio/common/inv_sensors/Kconfig b/drivers/iio/common/inv_sensors/Kconfig new file mode 100644 index 000000000000..28815fb43157 --- /dev/null +++ b/drivers/iio/common/inv_sensors/Kconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# TDK-InvenSense sensors common library +# + +config IIO_INV_SENSORS_TIMESTAMP + tristate diff --git a/drivers/iio/common/inv_sensors/Makefile b/drivers/iio/common/inv_sensors/Makefile new file mode 100644 index 000000000000..dcf39f249112 --- /dev/null +++ b/drivers/iio/common/inv_sensors/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for TDK-InvenSense sensors module. +# + +obj-$(CONFIG_IIO_INV_SENSORS_TIMESTAMP) += inv_sensors_timestamp.o diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_timestamp.c b/drivers/iio/common/inv_sensors/inv_sensors_timestamp.c index 37cbf08acb3a..03823ee57f59 100644 --- a/drivers/iio/imu/inv_icm42600/inv_icm42600_timestamp.c +++ b/drivers/iio/common/inv_sensors/inv_sensors_timestamp.c @@ -3,25 +3,23 @@ * Copyright (C) 2020 Invensense, Inc. */ +#include <linux/errno.h> #include <linux/kernel.h> -#include <linux/regmap.h> #include <linux/math64.h> +#include <linux/module.h> -#include "inv_icm42600.h" -#include "inv_icm42600_timestamp.h" +#include <linux/iio/common/inv_sensors_timestamp.h> -/* internal chip period is 32kHz, 31250ns */ -#define INV_ICM42600_TIMESTAMP_PERIOD 31250 -/* allow a jitter of +/- 2% */ -#define INV_ICM42600_TIMESTAMP_JITTER 2 -/* compute min and max periods accepted */ -#define INV_ICM42600_TIMESTAMP_MIN_PERIOD(_p) \ - (((_p) * (100 - INV_ICM42600_TIMESTAMP_JITTER)) / 100) -#define INV_ICM42600_TIMESTAMP_MAX_PERIOD(_p) \ - (((_p) * (100 + INV_ICM42600_TIMESTAMP_JITTER)) / 100) +/* compute jitter, min and max following jitter in per mille */ +#define INV_SENSORS_TIMESTAMP_JITTER(_val, _jitter) \ + (div_s64((_val) * (_jitter), 1000)) +#define INV_SENSORS_TIMESTAMP_MIN(_val, _jitter) \ + (((_val) * (1000 - (_jitter))) / 1000) +#define INV_SENSORS_TIMESTAMP_MAX(_val, _jitter) \ + (((_val) * (1000 + (_jitter))) / 1000) /* Add a new value inside an accumulator and update the estimate value */ -static void inv_update_acc(struct inv_icm42600_timestamp_acc *acc, uint32_t val) +static void inv_update_acc(struct inv_sensors_timestamp_acc *acc, uint32_t val) { uint64_t sum = 0; size_t i; @@ -40,65 +38,57 @@ static void inv_update_acc(struct inv_icm42600_timestamp_acc *acc, uint32_t val) acc->val = div_u64(sum, i); } -void inv_icm42600_timestamp_init(struct inv_icm42600_timestamp *ts, - uint32_t period) +void inv_sensors_timestamp_init(struct inv_sensors_timestamp *ts, + const struct inv_sensors_timestamp_chip *chip) { - /* initial odr for sensor after reset is 1kHz */ - const uint32_t default_period = 1000000; + memset(ts, 0, sizeof(*ts)); + + /* save chip parameters and compute min and max clock period */ + ts->chip = *chip; + ts->min_period = INV_SENSORS_TIMESTAMP_MIN(chip->clock_period, chip->jitter); + ts->max_period = INV_SENSORS_TIMESTAMP_MAX(chip->clock_period, chip->jitter); /* current multiplier and period values after reset */ - ts->mult = default_period / INV_ICM42600_TIMESTAMP_PERIOD; - ts->period = default_period; - /* new set multiplier is the one from chip initialization */ - ts->new_mult = period / INV_ICM42600_TIMESTAMP_PERIOD; + ts->mult = chip->init_period / chip->clock_period; + ts->period = chip->init_period; /* use theoretical value for chip period */ - inv_update_acc(&ts->chip_period, INV_ICM42600_TIMESTAMP_PERIOD); + inv_update_acc(&ts->chip_period, chip->clock_period); } +EXPORT_SYMBOL_NS_GPL(inv_sensors_timestamp_init, IIO_INV_SENSORS_TIMESTAMP); -int inv_icm42600_timestamp_setup(struct inv_icm42600_state *st) -{ - unsigned int val; - - /* enable timestamp register */ - val = INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN | - INV_ICM42600_TMST_CONFIG_TMST_EN; - return regmap_update_bits(st->map, INV_ICM42600_REG_TMST_CONFIG, - INV_ICM42600_TMST_CONFIG_MASK, val); -} - -int inv_icm42600_timestamp_update_odr(struct inv_icm42600_timestamp *ts, - uint32_t period, bool fifo) +int inv_sensors_timestamp_update_odr(struct inv_sensors_timestamp *ts, + uint32_t period, bool fifo) { /* when FIFO is on, prevent odr change if one is already pending */ if (fifo && ts->new_mult != 0) return -EAGAIN; - ts->new_mult = period / INV_ICM42600_TIMESTAMP_PERIOD; + ts->new_mult = period / ts->chip.clock_period; return 0; } +EXPORT_SYMBOL_NS_GPL(inv_sensors_timestamp_update_odr, IIO_INV_SENSORS_TIMESTAMP); -static bool inv_validate_period(uint32_t period, uint32_t mult) +static bool inv_validate_period(struct inv_sensors_timestamp *ts, uint32_t period, uint32_t mult) { - const uint32_t chip_period = INV_ICM42600_TIMESTAMP_PERIOD; uint32_t period_min, period_max; /* check that period is acceptable */ - period_min = INV_ICM42600_TIMESTAMP_MIN_PERIOD(chip_period) * mult; - period_max = INV_ICM42600_TIMESTAMP_MAX_PERIOD(chip_period) * mult; + period_min = ts->min_period * mult; + period_max = ts->max_period * mult; if (period > period_min && period < period_max) return true; else return false; } -static bool inv_update_chip_period(struct inv_icm42600_timestamp *ts, - uint32_t mult, uint32_t period) +static bool inv_update_chip_period(struct inv_sensors_timestamp *ts, + uint32_t mult, uint32_t period) { uint32_t new_chip_period; - if (!inv_validate_period(period, mult)) + if (!inv_validate_period(ts, period, mult)) return false; /* update chip internal period estimation */ @@ -109,7 +99,7 @@ static bool inv_update_chip_period(struct inv_icm42600_timestamp *ts, return true; } -static void inv_align_timestamp_it(struct inv_icm42600_timestamp *ts) +static void inv_align_timestamp_it(struct inv_sensors_timestamp *ts) { int64_t delta, jitter; int64_t adjust; @@ -118,7 +108,7 @@ static void inv_align_timestamp_it(struct inv_icm42600_timestamp *ts) delta = ts->it.lo - ts->timestamp; /* adjust timestamp while respecting jitter */ - jitter = div_s64((int64_t)ts->period * INV_ICM42600_TIMESTAMP_JITTER, 100); + jitter = INV_SENSORS_TIMESTAMP_JITTER((int64_t)ts->period, ts->chip.jitter); if (delta > jitter) adjust = jitter; else if (delta < -jitter) @@ -129,13 +119,13 @@ static void inv_align_timestamp_it(struct inv_icm42600_timestamp *ts) ts->timestamp += adjust; } -void inv_icm42600_timestamp_interrupt(struct inv_icm42600_timestamp *ts, +void inv_sensors_timestamp_interrupt(struct inv_sensors_timestamp *ts, uint32_t fifo_period, size_t fifo_nb, size_t sensor_nb, int64_t timestamp) { - struct inv_icm42600_timestamp_interval *it; + struct inv_sensors_timestamp_interval *it; int64_t delta, interval; - const uint32_t fifo_mult = fifo_period / INV_ICM42600_TIMESTAMP_PERIOD; + const uint32_t fifo_mult = fifo_period / ts->chip.clock_period; uint32_t period = ts->period; bool valid = false; @@ -165,10 +155,11 @@ void inv_icm42600_timestamp_interrupt(struct inv_icm42600_timestamp *ts, if (valid) inv_align_timestamp_it(ts); } +EXPORT_SYMBOL_NS_GPL(inv_sensors_timestamp_interrupt, IIO_INV_SENSORS_TIMESTAMP); -void inv_icm42600_timestamp_apply_odr(struct inv_icm42600_timestamp *ts, - uint32_t fifo_period, size_t fifo_nb, - unsigned int fifo_no) +void inv_sensors_timestamp_apply_odr(struct inv_sensors_timestamp *ts, + uint32_t fifo_period, size_t fifo_nb, + unsigned int fifo_no) { int64_t interval; uint32_t fifo_mult; @@ -189,10 +180,15 @@ void inv_icm42600_timestamp_apply_odr(struct inv_icm42600_timestamp *ts, */ if (ts->timestamp != 0) { /* compute measured fifo period */ - fifo_mult = fifo_period / INV_ICM42600_TIMESTAMP_PERIOD; + fifo_mult = fifo_period / ts->chip.clock_period; fifo_period = fifo_mult * ts->chip_period.val; /* computes time interval between interrupt and this sample */ interval = (int64_t)(fifo_nb - fifo_no) * (int64_t)fifo_period; ts->timestamp = ts->it.up - interval; } } +EXPORT_SYMBOL_NS_GPL(inv_sensors_timestamp_apply_odr, IIO_INV_SENSORS_TIMESTAMP); + +MODULE_AUTHOR("InvenSense, Inc."); +MODULE_DESCRIPTION("InvenSense sensors timestamp module"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 3acd9c3f388e..93b8be183de6 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -389,6 +389,17 @@ config MCP4725 To compile this driver as a module, choose M here: the module will be called mcp4725. +config MCP4728 + tristate "MCP4728 DAC driver" + depends on I2C + help + Say Y here if you want to build a driver for the Microchip + MCP4728 quad channel, 12-bit digital-to-analog converter (DAC) + with I2C interface. + + To compile this driver as a module, choose M here: the module + will be called mcp4728. + config MCP4922 tristate "MCP4902, MCP4912, MCP4922 DAC driver" depends on SPI diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index addd97a78838..5b2bac900d5a 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MAX517) += max517.o obj-$(CONFIG_MAX5522) += max5522.o obj-$(CONFIG_MAX5821) += max5821.o obj-$(CONFIG_MCP4725) += mcp4725.o +obj-$(CONFIG_MCP4728) += mcp4728.o obj-$(CONFIG_MCP4922) += mcp4922.o obj-$(CONFIG_STM32_DAC_CORE) += stm32-dac-core.o obj-$(CONFIG_STM32_DAC) += stm32-dac.o diff --git a/drivers/iio/dac/mcp4728.c b/drivers/iio/dac/mcp4728.c new file mode 100644 index 000000000000..5113f67ddc31 --- /dev/null +++ b/drivers/iio/dac/mcp4728.c @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Support for Microchip MCP4728 + * + * Copyright (C) 2023 Andrea Collamati <andrea.collamati@gmail.com> + * + * Based on mcp4725 by Peter Meerwald <pmeerw@pmeerw.net> + * + * Driver for the Microchip I2C 12-bit digital-to-analog quad channels + * converter (DAC). + * + * (7-bit I2C slave address 0x60, the three LSBs can be configured in + * hardware) + */ + +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/iio/iio.h> +#include <linux/iio/sysfs.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/property.h> +#include <linux/regulator/consumer.h> + +#define MCP4728_RESOLUTION 12 +#define MCP4728_N_CHANNELS 4 + +#define MCP4728_CMD_MASK GENMASK(7, 3) +#define MCP4728_CHSEL_MASK GENMASK(2, 1) +#define MCP4728_UDAC_MASK BIT(0) + +#define MCP4728_VREF_MASK BIT(7) +#define MCP4728_PDMODE_MASK GENMASK(6, 5) +#define MCP4728_GAIN_MASK BIT(4) + +#define MCP4728_DAC_H_MASK GENMASK(3, 0) +#define MCP4728_DAC_L_MASK GENMASK(7, 0) + +#define MCP4728_RDY_MASK BIT(7) + +#define MCP4728_MW_CMD 0x08 /* Multiwrite Command */ +#define MCP4728_SW_CMD 0x0A /* Sequential Write Command with EEPROM */ + +#define MCP4728_READ_RESPONSE_LEN (MCP4728_N_CHANNELS * 3 * 2) +#define MCP4728_WRITE_EEPROM_LEN (1 + MCP4728_N_CHANNELS * 2) + +enum vref_mode { + MCP4728_VREF_EXTERNAL_VDD = 0, + MCP4728_VREF_INTERNAL_2048mV = 1, +}; + +enum gain_mode { + MCP4728_GAIN_X1 = 0, + MCP4728_GAIN_X2 = 1, +}; + +enum iio_powerdown_mode { + MCP4728_IIO_1K, + MCP4728_IIO_100K, + MCP4728_IIO_500K, +}; + +struct mcp4728_channel_data { + enum vref_mode ref_mode; + enum iio_powerdown_mode pd_mode; + enum gain_mode g_mode; + u16 dac_value; +}; + +/* MCP4728 Full Scale Ranges + * the device available ranges are + * - VREF = VDD FSR = from 0.0V to VDD + * - VREF = Internal Gain = 1 FSR = from 0.0V to VREF + * - VREF = Internal Gain = 2 FSR = from 0.0V to 2*VREF + */ +enum mcp4728_scale { + MCP4728_SCALE_VDD, + MCP4728_SCALE_VINT_NO_GAIN, + MCP4728_SCALE_VINT_GAIN_X2, + MCP4728_N_SCALES +}; + +struct mcp4728_data { + struct i2c_client *client; + struct regulator *vdd_reg; + bool powerdown; + int scales_avail[MCP4728_N_SCALES * 2]; + struct mcp4728_channel_data chdata[MCP4728_N_CHANNELS]; +}; + +#define MCP4728_CHAN(chan) { \ + .type = IIO_VOLTAGE, \ + .output = 1, \ + .indexed = 1, \ + .channel = chan, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ + .ext_info = mcp4728_ext_info, \ +} + +static int mcp4728_suspend(struct device *dev); +static int mcp4728_resume(struct device *dev); + +static ssize_t mcp4728_store_eeprom(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct mcp4728_data *data = iio_priv(indio_dev); + u8 outbuf[MCP4728_WRITE_EEPROM_LEN]; + int tries = 20; + u8 inbuf[3]; + bool state; + int ret; + unsigned int i; + + ret = kstrtobool(buf, &state); + if (ret < 0) + return ret; + + if (!state) + return 0; + + outbuf[0] = FIELD_PREP(MCP4728_CMD_MASK, MCP4728_SW_CMD); + + for (i = 0; i < MCP4728_N_CHANNELS; i++) { + struct mcp4728_channel_data *ch = &data->chdata[i]; + int offset = 1 + i * 2; + + outbuf[offset] = FIELD_PREP(MCP4728_VREF_MASK, ch->ref_mode); + + if (data->powerdown) { + u8 mcp4728_pd_mode = ch->pd_mode + 1; + + outbuf[offset] |= FIELD_PREP(MCP4728_PDMODE_MASK, + mcp4728_pd_mode); + } + + outbuf[offset] |= FIELD_PREP(MCP4728_GAIN_MASK, ch->g_mode); + outbuf[offset] |= + FIELD_PREP(MCP4728_DAC_H_MASK, ch->dac_value >> 8); + outbuf[offset + 1] = + FIELD_PREP(MCP4728_DAC_L_MASK, ch->dac_value); + } + + ret = i2c_master_send(data->client, outbuf, MCP4728_WRITE_EEPROM_LEN); + if (ret < 0) + return ret; + else if (ret != MCP4728_WRITE_EEPROM_LEN) + return -EIO; + + /* wait RDY signal for write complete, takes up to 50ms */ + while (tries--) { + msleep(20); + ret = i2c_master_recv(data->client, inbuf, 3); + if (ret < 0) + return ret; + else if (ret != 3) + return -EIO; + + if (FIELD_GET(MCP4728_RDY_MASK, inbuf[0])) + break; + } + + if (tries < 0) { + dev_err(&data->client->dev, "%s failed, incomplete\n", + __func__); + return -EIO; + } + return len; +} + +static IIO_DEVICE_ATTR(store_eeprom, 0200, NULL, mcp4728_store_eeprom, 0); + +static struct attribute *mcp4728_attributes[] = { + &iio_dev_attr_store_eeprom.dev_attr.attr, + NULL, +}; + +static const struct attribute_group mcp4728_attribute_group = { + .attrs = mcp4728_attributes, +}; + +static int mcp4728_program_channel_cfg(int channel, struct iio_dev *indio_dev) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + struct mcp4728_channel_data *ch = &data->chdata[channel]; + u8 outbuf[3]; + int ret; + + outbuf[0] = FIELD_PREP(MCP4728_CMD_MASK, MCP4728_MW_CMD); + outbuf[0] |= FIELD_PREP(MCP4728_CHSEL_MASK, channel); + outbuf[0] |= FIELD_PREP(MCP4728_UDAC_MASK, 0); + + outbuf[1] = FIELD_PREP(MCP4728_VREF_MASK, ch->ref_mode); + + if (data->powerdown) + outbuf[1] |= FIELD_PREP(MCP4728_PDMODE_MASK, ch->pd_mode + 1); + + outbuf[1] |= FIELD_PREP(MCP4728_GAIN_MASK, ch->g_mode); + outbuf[1] |= FIELD_PREP(MCP4728_DAC_H_MASK, ch->dac_value >> 8); + outbuf[2] = FIELD_PREP(MCP4728_DAC_L_MASK, ch->dac_value); + + ret = i2c_master_send(data->client, outbuf, 3); + if (ret < 0) + return ret; + else if (ret != 3) + return -EIO; + + return 0; +} + +static const char *const mcp4728_powerdown_modes[] = { "1kohm_to_gnd", + "100kohm_to_gnd", + "500kohm_to_gnd" }; + +static int mcp4728_get_powerdown_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + + return data->chdata[chan->channel].pd_mode; +} + +static int mcp4728_set_powerdown_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + + data->chdata[chan->channel].pd_mode = mode; + + return 0; +} + +static ssize_t mcp4728_read_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + + return sysfs_emit(buf, "%d\n", data->powerdown); +} + +static ssize_t mcp4728_write_powerdown(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + bool state; + int ret; + + ret = kstrtobool(buf, &state); + if (ret) + return ret; + + if (state) + ret = mcp4728_suspend(&data->client->dev); + else + ret = mcp4728_resume(&data->client->dev); + + if (ret < 0) + return ret; + + return len; +} + +static const struct iio_enum mcp4728_powerdown_mode_enum = { + .items = mcp4728_powerdown_modes, + .num_items = ARRAY_SIZE(mcp4728_powerdown_modes), + .get = mcp4728_get_powerdown_mode, + .set = mcp4728_set_powerdown_mode, +}; + +static const struct iio_chan_spec_ext_info mcp4728_ext_info[] = { + { + .name = "powerdown", + .read = mcp4728_read_powerdown, + .write = mcp4728_write_powerdown, + .shared = IIO_SEPARATE, + }, + IIO_ENUM("powerdown_mode", IIO_SEPARATE, &mcp4728_powerdown_mode_enum), + IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, + &mcp4728_powerdown_mode_enum), + {}, +}; + +static const struct iio_chan_spec mcp4728_channels[MCP4728_N_CHANNELS] = { + MCP4728_CHAN(0), + MCP4728_CHAN(1), + MCP4728_CHAN(2), + MCP4728_CHAN(3), +}; + +static void mcp4728_get_scale_avail(enum mcp4728_scale scale, + struct mcp4728_data *data, int *val, + int *val2) +{ + *val = data->scales_avail[scale * 2]; + *val2 = data->scales_avail[scale * 2 + 1]; +} + +static void mcp4728_get_scale(int channel, struct mcp4728_data *data, int *val, + int *val2) +{ + int ref_mode = data->chdata[channel].ref_mode; + int g_mode = data->chdata[channel].g_mode; + + if (ref_mode == MCP4728_VREF_EXTERNAL_VDD) { + mcp4728_get_scale_avail(MCP4728_SCALE_VDD, data, val, val2); + } else { + if (g_mode == MCP4728_GAIN_X1) { + mcp4728_get_scale_avail(MCP4728_SCALE_VINT_NO_GAIN, + data, val, val2); + } else { + mcp4728_get_scale_avail(MCP4728_SCALE_VINT_GAIN_X2, + data, val, val2); + } + } +} + +static int mcp4728_find_matching_scale(struct mcp4728_data *data, int val, + int val2) +{ + for (int i = 0; i < MCP4728_N_SCALES; i++) { + if (data->scales_avail[i * 2] == val && + data->scales_avail[i * 2 + 1] == val2) + return i; + } + return -EINVAL; +} + +static int mcp4728_set_scale(int channel, struct mcp4728_data *data, int val, + int val2) +{ + int scale = mcp4728_find_matching_scale(data, val, val2); + + if (scale < 0) + return scale; + + switch (scale) { + case MCP4728_SCALE_VDD: + data->chdata[channel].ref_mode = MCP4728_VREF_EXTERNAL_VDD; + return 0; + case MCP4728_SCALE_VINT_NO_GAIN: + data->chdata[channel].ref_mode = MCP4728_VREF_INTERNAL_2048mV; + data->chdata[channel].g_mode = MCP4728_GAIN_X1; + return 0; + case MCP4728_SCALE_VINT_GAIN_X2: + data->chdata[channel].ref_mode = MCP4728_VREF_INTERNAL_2048mV; + data->chdata[channel].g_mode = MCP4728_GAIN_X2; + return 0; + default: + return -EINVAL; + } +} + +static int mcp4728_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + *val = data->chdata[chan->channel].dac_value; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + mcp4728_get_scale(chan->channel, data, val, val2); + return IIO_VAL_INT_PLUS_MICRO; + } + return -EINVAL; +} + +static int mcp4728_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long mask) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (val < 0 || val > GENMASK(MCP4728_RESOLUTION - 1, 0)) + return -EINVAL; + data->chdata[chan->channel].dac_value = val; + return mcp4728_program_channel_cfg(chan->channel, indio_dev); + case IIO_CHAN_INFO_SCALE: + ret = mcp4728_set_scale(chan->channel, data, val, val2); + if (ret) + return ret; + + return mcp4728_program_channel_cfg(chan->channel, indio_dev); + default: + return -EINVAL; + } +} + +static void mcp4728_init_scale_avail(enum mcp4728_scale scale, int vref_mv, + struct mcp4728_data *data) +{ + s64 tmp; + int value_micro; + int value_int; + + tmp = (s64)vref_mv * 1000000LL >> MCP4728_RESOLUTION; + value_int = div_s64_rem(tmp, 1000000LL, &value_micro); + + data->scales_avail[scale * 2] = value_int; + data->scales_avail[scale * 2 + 1] = value_micro; +} + +static int mcp4728_init_scales_avail(struct mcp4728_data *data) +{ + int ret; + + ret = regulator_get_voltage(data->vdd_reg); + if (ret < 0) + return ret; + + mcp4728_init_scale_avail(MCP4728_SCALE_VDD, ret / 1000, data); + mcp4728_init_scale_avail(MCP4728_SCALE_VINT_NO_GAIN, 2048, data); + mcp4728_init_scale_avail(MCP4728_SCALE_VINT_GAIN_X2, 4096, data); + + return 0; +} + +static int mcp4728_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long info) +{ + struct mcp4728_data *data = iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_SCALE: + *type = IIO_VAL_INT_PLUS_MICRO; + + switch (chan->type) { + case IIO_VOLTAGE: + *vals = data->scales_avail; + *length = MCP4728_N_SCALES * 2; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + default: + return -EINVAL; + } +} + +static const struct iio_info mcp4728_info = { + .read_raw = mcp4728_read_raw, + .write_raw = mcp4728_write_raw, + .read_avail = &mcp4728_read_avail, + .attrs = &mcp4728_attribute_group, +}; + +static int mcp4728_suspend(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct mcp4728_data *data = iio_priv(indio_dev); + unsigned int i; + + data->powerdown = true; + + for (i = 0; i < MCP4728_N_CHANNELS; i++) { + int err = mcp4728_program_channel_cfg(i, indio_dev); + + if (err) + return err; + } + return 0; +} + +static int mcp4728_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct mcp4728_data *data = iio_priv(indio_dev); + int err = 0; + unsigned int i; + + data->powerdown = false; + + for (i = 0; i < MCP4728_N_CHANNELS; i++) { + int ret = mcp4728_program_channel_cfg(i, indio_dev); + + if (ret) + err = ret; + } + return err; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(mcp4728_pm_ops, mcp4728_suspend, + mcp4728_resume); + +static int mcp4728_init_channels_data(struct mcp4728_data *data) +{ + u8 inbuf[MCP4728_READ_RESPONSE_LEN]; + int ret; + unsigned int i; + + ret = i2c_master_recv(data->client, inbuf, MCP4728_READ_RESPONSE_LEN); + if (ret < 0) { + return dev_err_probe(&data->client->dev, ret, + "failed to read mcp4728 conf.\n"); + } else if (ret != MCP4728_READ_RESPONSE_LEN) { + return dev_err_probe(&data->client->dev, -EIO, + "failed to read mcp4728 conf. Wrong Response Len ret=%d\n", + ret); + } + + for (i = 0; i < MCP4728_N_CHANNELS; i++) { + struct mcp4728_channel_data *ch = &data->chdata[i]; + u8 r2 = inbuf[i * 6 + 1]; + u8 r3 = inbuf[i * 6 + 2]; + + ch->dac_value = FIELD_GET(MCP4728_DAC_H_MASK, r2) << 8 | + FIELD_GET(MCP4728_DAC_L_MASK, r3); + ch->ref_mode = FIELD_GET(MCP4728_VREF_MASK, r2); + ch->pd_mode = FIELD_GET(MCP4728_PDMODE_MASK, r2); + ch->g_mode = FIELD_GET(MCP4728_GAIN_MASK, r2); + } + + return 0; +} + +static void mcp4728_reg_disable(void *reg) +{ + regulator_disable(reg); +} + +static int mcp4728_probe(struct i2c_client *client) +{ + const struct i2c_device_id *id = i2c_client_get_device_id(client); + struct mcp4728_data *data; + struct iio_dev *indio_dev; + int err; + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!indio_dev) + return -ENOMEM; + + data = iio_priv(indio_dev); + i2c_set_clientdata(client, indio_dev); + data->client = client; + + data->vdd_reg = devm_regulator_get(&client->dev, "vdd"); + if (IS_ERR(data->vdd_reg)) + return PTR_ERR(data->vdd_reg); + + err = regulator_enable(data->vdd_reg); + if (err) + return err; + + err = devm_add_action_or_reset(&client->dev, mcp4728_reg_disable, + data->vdd_reg); + if (err) + return err; + + /* + * MCP4728 has internal EEPROM that save each channel boot + * configuration. It means that device configuration is unknown to the + * driver at kernel boot. mcp4728_init_channels_data() reads back DAC + * settings and stores them in data structure. + */ + err = mcp4728_init_channels_data(data); + if (err) { + return dev_err_probe(&client->dev, err, + "failed to read mcp4728 current configuration\n"); + } + + err = mcp4728_init_scales_avail(data); + if (err) { + return dev_err_probe(&client->dev, err, + "failed to init scales\n"); + } + + indio_dev->name = id->name; + indio_dev->info = &mcp4728_info; + indio_dev->channels = mcp4728_channels; + indio_dev->num_channels = MCP4728_N_CHANNELS; + indio_dev->modes = INDIO_DIRECT_MODE; + + return devm_iio_device_register(&client->dev, indio_dev); +} + +static const struct i2c_device_id mcp4728_id[] = { + { "mcp4728", 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, mcp4728_id); + +static const struct of_device_id mcp4728_of_match[] = { + { .compatible = "microchip,mcp4728" }, + {} +}; +MODULE_DEVICE_TABLE(of, mcp4728_of_match); + +static struct i2c_driver mcp4728_driver = { + .driver = { + .name = "mcp4728", + .of_match_table = mcp4728_of_match, + .pm = pm_sleep_ptr(&mcp4728_pm_ops), + }, + .probe = mcp4728_probe, + .id_table = mcp4728_id, +}; +module_i2c_driver(mcp4728_driver); + +MODULE_AUTHOR("Andrea Collamati <andrea.collamati@gmail.com>"); +MODULE_DESCRIPTION("MCP4728 12-bit DAC"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/filter/admv8818.c b/drivers/iio/filter/admv8818.c index fe8d46cb7f1d..848baa6e3bbf 100644 --- a/drivers/iio/filter/admv8818.c +++ b/drivers/iio/filter/admv8818.c @@ -78,6 +78,7 @@ enum { enum { ADMV8818_AUTO_MODE, ADMV8818_MANUAL_MODE, + ADMV8818_BYPASS_MODE, }; struct admv8818_state { @@ -114,7 +115,8 @@ static const struct regmap_config admv8818_regmap_config = { static const char * const admv8818_modes[] = { [0] = "auto", - [1] = "manual" + [1] = "manual", + [2] = "bypass" }; static int __admv8818_hpf_select(struct admv8818_state *st, u64 freq) @@ -394,6 +396,36 @@ static int admv8818_reg_access(struct iio_dev *indio_dev, return regmap_write(st->regmap, reg, write_val); } +static int admv8818_filter_bypass(struct admv8818_state *st) +{ + int ret; + + mutex_lock(&st->lock); + + ret = regmap_update_bits(st->regmap, ADMV8818_REG_WR0_SW, + ADMV8818_SW_IN_SET_WR0_MSK | + ADMV8818_SW_IN_WR0_MSK | + ADMV8818_SW_OUT_SET_WR0_MSK | + ADMV8818_SW_OUT_WR0_MSK, + FIELD_PREP(ADMV8818_SW_IN_SET_WR0_MSK, 1) | + FIELD_PREP(ADMV8818_SW_IN_WR0_MSK, 0) | + FIELD_PREP(ADMV8818_SW_OUT_SET_WR0_MSK, 1) | + FIELD_PREP(ADMV8818_SW_OUT_WR0_MSK, 0)); + if (ret) + goto exit; + + ret = regmap_update_bits(st->regmap, ADMV8818_REG_WR0_FILTER, + ADMV8818_HPF_WR0_MSK | + ADMV8818_LPF_WR0_MSK, + FIELD_PREP(ADMV8818_HPF_WR0_MSK, 0) | + FIELD_PREP(ADMV8818_LPF_WR0_MSK, 0)); + +exit: + mutex_unlock(&st->lock); + + return ret; +} + static int admv8818_get_mode(struct iio_dev *indio_dev, const struct iio_chan_spec *chan) { @@ -411,14 +443,22 @@ static int admv8818_set_mode(struct iio_dev *indio_dev, if (!st->clkin) { if (mode == ADMV8818_MANUAL_MODE) - return 0; + goto set_mode; + + if (mode == ADMV8818_BYPASS_MODE) { + ret = admv8818_filter_bypass(st); + if (ret) + return ret; + + goto set_mode; + } return -EINVAL; } switch (mode) { case ADMV8818_AUTO_MODE: - if (!st->filter_mode) + if (st->filter_mode == ADMV8818_AUTO_MODE) return 0; ret = clk_prepare_enable(st->clkin); @@ -434,20 +474,27 @@ static int admv8818_set_mode(struct iio_dev *indio_dev, break; case ADMV8818_MANUAL_MODE: - if (st->filter_mode) - return 0; + case ADMV8818_BYPASS_MODE: + if (st->filter_mode == ADMV8818_AUTO_MODE) { + clk_disable_unprepare(st->clkin); - clk_disable_unprepare(st->clkin); + ret = clk_notifier_unregister(st->clkin, &st->nb); + if (ret) + return ret; + } - ret = clk_notifier_unregister(st->clkin, &st->nb); - if (ret) - return ret; + if (mode == ADMV8818_BYPASS_MODE) { + ret = admv8818_filter_bypass(st); + if (ret) + return ret; + } break; default: return -EINVAL; } +set_mode: st->filter_mode = mode; return ret; diff --git a/drivers/iio/frequency/admv1013.c b/drivers/iio/frequency/admv1013.c index 8c8e0bbfc99f..6355c1f28423 100644 --- a/drivers/iio/frequency/admv1013.c +++ b/drivers/iio/frequency/admv1013.c @@ -382,6 +382,11 @@ static const struct iio_info admv1013_info = { .debugfs_reg_access = &admv1013_reg_access, }; +static const char * const admv1013_vcc_regs[] = { + "vcc-drv", "vcc2-drv", "vcc-vva", "vcc-amp1", "vcc-amp2", + "vcc-env", "vcc-bg", "vcc-bg2", "vcc-mixer", "vcc-quad" +}; + static int admv1013_freq_change(struct notifier_block *nb, unsigned long action, void *data) { struct admv1013_state *st = container_of(nb, struct admv1013_state, nb); @@ -557,6 +562,15 @@ static int admv1013_properties_parse(struct admv1013_state *st) return dev_err_probe(&spi->dev, PTR_ERR(st->reg), "failed to get the common-mode voltage\n"); + ret = devm_regulator_bulk_get_enable(&st->spi->dev, + ARRAY_SIZE(admv1013_vcc_regs), + admv1013_vcc_regs); + if (ret) { + dev_err_probe(&spi->dev, ret, + "Failed to request VCC regulators\n"); + return ret; + } + return 0; } diff --git a/drivers/iio/imu/adis16475.c b/drivers/iio/imu/adis16475.c index 3abffb01ba31..17275a53ca2c 100644 --- a/drivers/iio/imu/adis16475.c +++ b/drivers/iio/imu/adis16475.c @@ -115,8 +115,6 @@ enum { ADIS16475_SCAN_ACCEL_Y, ADIS16475_SCAN_ACCEL_Z, ADIS16475_SCAN_TEMP, - ADIS16475_SCAN_DIAG_S_FLAGS, - ADIS16475_SCAN_CRC_FAILURE, }; static bool low_rate_allow; @@ -728,6 +726,7 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .has_burst32 = true, .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), }, [ADIS16477_2] = { @@ -743,6 +742,7 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .has_burst32 = true, .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), }, [ADIS16477_3] = { @@ -758,6 +758,7 @@ static const struct adis16475_chip_info adis16475_chip_info[] = { .max_dec = 1999, .sync = adis16475_sync_mode, .num_sync = ARRAY_SIZE(adis16475_sync_mode), + .has_burst32 = true, .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts), }, [ADIS16465_1] = { diff --git a/drivers/iio/imu/inv_icm42600/Kconfig b/drivers/iio/imu/inv_icm42600/Kconfig index 50cbcfcb6cf1..f56b0816cc4d 100644 --- a/drivers/iio/imu/inv_icm42600/Kconfig +++ b/drivers/iio/imu/inv_icm42600/Kconfig @@ -3,6 +3,7 @@ config INV_ICM42600 tristate select IIO_BUFFER + select IIO_INV_SENSORS_TIMESTAMP config INV_ICM42600_I2C tristate "InvenSense ICM-426xx I2C driver" diff --git a/drivers/iio/imu/inv_icm42600/Makefile b/drivers/iio/imu/inv_icm42600/Makefile index 291714d9aa54..0f49f6df3647 100644 --- a/drivers/iio/imu/inv_icm42600/Makefile +++ b/drivers/iio/imu/inv_icm42600/Makefile @@ -6,7 +6,6 @@ inv-icm42600-y += inv_icm42600_gyro.o inv-icm42600-y += inv_icm42600_accel.o inv-icm42600-y += inv_icm42600_temp.o inv-icm42600-y += inv_icm42600_buffer.o -inv-icm42600-y += inv_icm42600_timestamp.o obj-$(CONFIG_INV_ICM42600_I2C) += inv-icm42600-i2c.o inv-icm42600-i2c-y += inv_icm42600_i2c.o diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c index c3f433ad3af6..b1e4fde27d25 100644 --- a/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c +++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_accel.c @@ -10,14 +10,15 @@ #include <linux/regmap.h> #include <linux/delay.h> #include <linux/math64.h> -#include <linux/iio/iio.h> + #include <linux/iio/buffer.h> +#include <linux/iio/common/inv_sensors_timestamp.h> +#include <linux/iio/iio.h> #include <linux/iio/kfifo_buf.h> #include "inv_icm42600.h" #include "inv_icm42600_temp.h" #include "inv_icm42600_buffer.h" -#include "inv_icm42600_timestamp.h" #define INV_ICM42600_ACCEL_CHAN(_modifier, _index, _ext_info) \ { \ @@ -98,7 +99,7 @@ static int inv_icm42600_accel_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); - struct inv_icm42600_timestamp *ts = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = iio_priv(indio_dev); struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT; unsigned int fifo_en = 0; unsigned int sleep_temp = 0; @@ -126,7 +127,7 @@ static int inv_icm42600_accel_update_scan_mode(struct iio_dev *indio_dev, } /* update data FIFO write */ - inv_icm42600_timestamp_apply_odr(ts, 0, 0, 0); + inv_sensors_timestamp_apply_odr(ts, 0, 0, 0); ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); if (ret) goto out_unlock; @@ -311,7 +312,7 @@ static int inv_icm42600_accel_write_odr(struct iio_dev *indio_dev, int val, int val2) { struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); - struct inv_icm42600_timestamp *ts = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = iio_priv(indio_dev); struct device *dev = regmap_get_device(st->map); unsigned int idx; struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT; @@ -330,8 +331,8 @@ static int inv_icm42600_accel_write_odr(struct iio_dev *indio_dev, pm_runtime_get_sync(dev); mutex_lock(&st->lock); - ret = inv_icm42600_timestamp_update_odr(ts, inv_icm42600_odr_to_period(conf.odr), - iio_buffer_enabled(indio_dev)); + ret = inv_sensors_timestamp_update_odr(ts, inv_icm42600_odr_to_period(conf.odr), + iio_buffer_enabled(indio_dev)); if (ret) goto out_unlock; @@ -707,7 +708,8 @@ struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st) { struct device *dev = regmap_get_device(st->map); const char *name; - struct inv_icm42600_timestamp *ts; + struct inv_sensors_timestamp_chip ts_chip; + struct inv_sensors_timestamp *ts; struct iio_dev *indio_dev; int ret; @@ -719,8 +721,15 @@ struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st) if (!indio_dev) return ERR_PTR(-ENOMEM); + /* + * clock period is 32kHz (31250ns) + * jitter is +/- 2% (20 per mille) + */ + ts_chip.clock_period = 31250; + ts_chip.jitter = 20; + ts_chip.init_period = inv_icm42600_odr_to_period(st->conf.accel.odr); ts = iio_priv(indio_dev); - inv_icm42600_timestamp_init(ts, inv_icm42600_odr_to_period(st->conf.accel.odr)); + inv_sensors_timestamp_init(ts, &ts_chip); iio_device_set_drvdata(indio_dev, st); indio_dev->name = name; @@ -745,7 +754,7 @@ struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st) int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev) { struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); - struct inv_icm42600_timestamp *ts = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = iio_priv(indio_dev); ssize_t i, size; unsigned int no; const void *accel, *gyro, *timestamp; @@ -768,15 +777,15 @@ int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev) /* update odr */ if (odr & INV_ICM42600_SENSOR_ACCEL) - inv_icm42600_timestamp_apply_odr(ts, st->fifo.period, - st->fifo.nb.total, no); + inv_sensors_timestamp_apply_odr(ts, st->fifo.period, + st->fifo.nb.total, no); /* buffer is copied to userspace, zeroing it to avoid any data leak */ memset(&buffer, 0, sizeof(buffer)); memcpy(&buffer.accel, accel, sizeof(buffer.accel)); /* convert 8 bits FIFO temperature in high resolution format */ buffer.temp = temp ? (*temp * 64) : 0; - ts_val = inv_icm42600_timestamp_pop(ts); + ts_val = inv_sensors_timestamp_pop(ts); iio_push_to_buffers_with_timestamp(indio_dev, &buffer, ts_val); } diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c index 32d7f8364230..6ef1df9d60b7 100644 --- a/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c +++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.c @@ -9,11 +9,12 @@ #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/delay.h> -#include <linux/iio/iio.h> + #include <linux/iio/buffer.h> +#include <linux/iio/common/inv_sensors_timestamp.h> +#include <linux/iio/iio.h> #include "inv_icm42600.h" -#include "inv_icm42600_timestamp.h" #include "inv_icm42600_buffer.h" /* FIFO header: 1 byte */ @@ -275,12 +276,12 @@ static int inv_icm42600_buffer_preenable(struct iio_dev *indio_dev) { struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); struct device *dev = regmap_get_device(st->map); - struct inv_icm42600_timestamp *ts = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = iio_priv(indio_dev); pm_runtime_get_sync(dev); mutex_lock(&st->lock); - inv_icm42600_timestamp_reset(ts); + inv_sensors_timestamp_reset(ts); mutex_unlock(&st->lock); return 0; @@ -504,7 +505,7 @@ int inv_icm42600_buffer_fifo_read(struct inv_icm42600_state *st, int inv_icm42600_buffer_fifo_parse(struct inv_icm42600_state *st) { - struct inv_icm42600_timestamp *ts; + struct inv_sensors_timestamp *ts; int ret; if (st->fifo.nb.total == 0) @@ -512,8 +513,8 @@ int inv_icm42600_buffer_fifo_parse(struct inv_icm42600_state *st) /* handle gyroscope timestamp and FIFO data parsing */ ts = iio_priv(st->indio_gyro); - inv_icm42600_timestamp_interrupt(ts, st->fifo.period, st->fifo.nb.total, - st->fifo.nb.gyro, st->timestamp.gyro); + inv_sensors_timestamp_interrupt(ts, st->fifo.period, st->fifo.nb.total, + st->fifo.nb.gyro, st->timestamp.gyro); if (st->fifo.nb.gyro > 0) { ret = inv_icm42600_gyro_parse_fifo(st->indio_gyro); if (ret) @@ -522,8 +523,8 @@ int inv_icm42600_buffer_fifo_parse(struct inv_icm42600_state *st) /* handle accelerometer timestamp and FIFO data parsing */ ts = iio_priv(st->indio_accel); - inv_icm42600_timestamp_interrupt(ts, st->fifo.period, st->fifo.nb.total, - st->fifo.nb.accel, st->timestamp.accel); + inv_sensors_timestamp_interrupt(ts, st->fifo.period, st->fifo.nb.total, + st->fifo.nb.accel, st->timestamp.accel); if (st->fifo.nb.accel > 0) { ret = inv_icm42600_accel_parse_fifo(st->indio_accel); if (ret) @@ -536,7 +537,7 @@ int inv_icm42600_buffer_fifo_parse(struct inv_icm42600_state *st) int inv_icm42600_buffer_hwfifo_flush(struct inv_icm42600_state *st, unsigned int count) { - struct inv_icm42600_timestamp *ts; + struct inv_sensors_timestamp *ts; int64_t gyro_ts, accel_ts; int ret; @@ -552,9 +553,9 @@ int inv_icm42600_buffer_hwfifo_flush(struct inv_icm42600_state *st, if (st->fifo.nb.gyro > 0) { ts = iio_priv(st->indio_gyro); - inv_icm42600_timestamp_interrupt(ts, st->fifo.period, - st->fifo.nb.total, st->fifo.nb.gyro, - gyro_ts); + inv_sensors_timestamp_interrupt(ts, st->fifo.period, + st->fifo.nb.total, st->fifo.nb.gyro, + gyro_ts); ret = inv_icm42600_gyro_parse_fifo(st->indio_gyro); if (ret) return ret; @@ -562,9 +563,9 @@ int inv_icm42600_buffer_hwfifo_flush(struct inv_icm42600_state *st, if (st->fifo.nb.accel > 0) { ts = iio_priv(st->indio_accel); - inv_icm42600_timestamp_interrupt(ts, st->fifo.period, - st->fifo.nb.total, st->fifo.nb.accel, - accel_ts); + inv_sensors_timestamp_interrupt(ts, st->fifo.period, + st->fifo.nb.total, st->fifo.nb.accel, + accel_ts); ret = inv_icm42600_accel_parse_fifo(st->indio_accel); if (ret) return ret; diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c index 7b3a2a0dc2cb..a5e81906e37e 100644 --- a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c +++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c @@ -15,11 +15,11 @@ #include <linux/pm_runtime.h> #include <linux/property.h> #include <linux/regmap.h> + #include <linux/iio/iio.h> #include "inv_icm42600.h" #include "inv_icm42600_buffer.h" -#include "inv_icm42600_timestamp.h" static const struct regmap_range_cfg inv_icm42600_regmap_ranges[] = { { @@ -516,6 +516,17 @@ static int inv_icm42600_irq_init(struct inv_icm42600_state *st, int irq, "inv_icm42600", st); } +static int inv_icm42600_timestamp_setup(struct inv_icm42600_state *st) +{ + unsigned int val; + + /* enable timestamp register */ + val = INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN | + INV_ICM42600_TMST_CONFIG_TMST_EN; + return regmap_update_bits(st->map, INV_ICM42600_REG_TMST_CONFIG, + INV_ICM42600_TMST_CONFIG_MASK, val); +} + static int inv_icm42600_enable_regulator_vddio(struct inv_icm42600_state *st) { int ret; @@ -788,3 +799,4 @@ EXPORT_NS_GPL_DEV_PM_OPS(inv_icm42600_pm_ops, IIO_ICM42600) = { MODULE_AUTHOR("InvenSense, Inc."); MODULE_DESCRIPTION("InvenSense ICM-426xx device driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(IIO_INV_SENSORS_TIMESTAMP); diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c index 9d94a8518e3c..3bf946e56e1d 100644 --- a/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c +++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_gyro.c @@ -10,14 +10,15 @@ #include <linux/regmap.h> #include <linux/delay.h> #include <linux/math64.h> -#include <linux/iio/iio.h> + #include <linux/iio/buffer.h> +#include <linux/iio/common/inv_sensors_timestamp.h> +#include <linux/iio/iio.h> #include <linux/iio/kfifo_buf.h> #include "inv_icm42600.h" #include "inv_icm42600_temp.h" #include "inv_icm42600_buffer.h" -#include "inv_icm42600_timestamp.h" #define INV_ICM42600_GYRO_CHAN(_modifier, _index, _ext_info) \ { \ @@ -98,7 +99,7 @@ static int inv_icm42600_gyro_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) { struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); - struct inv_icm42600_timestamp *ts = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = iio_priv(indio_dev); struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT; unsigned int fifo_en = 0; unsigned int sleep_gyro = 0; @@ -126,7 +127,7 @@ static int inv_icm42600_gyro_update_scan_mode(struct iio_dev *indio_dev, } /* update data FIFO write */ - inv_icm42600_timestamp_apply_odr(ts, 0, 0, 0); + inv_sensors_timestamp_apply_odr(ts, 0, 0, 0); ret = inv_icm42600_buffer_set_fifo_en(st, fifo_en | st->fifo.en); if (ret) goto out_unlock; @@ -323,7 +324,7 @@ static int inv_icm42600_gyro_write_odr(struct iio_dev *indio_dev, int val, int val2) { struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); - struct inv_icm42600_timestamp *ts = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = iio_priv(indio_dev); struct device *dev = regmap_get_device(st->map); unsigned int idx; struct inv_icm42600_sensor_conf conf = INV_ICM42600_SENSOR_CONF_INIT; @@ -342,8 +343,8 @@ static int inv_icm42600_gyro_write_odr(struct iio_dev *indio_dev, pm_runtime_get_sync(dev); mutex_lock(&st->lock); - ret = inv_icm42600_timestamp_update_odr(ts, inv_icm42600_odr_to_period(conf.odr), - iio_buffer_enabled(indio_dev)); + ret = inv_sensors_timestamp_update_odr(ts, inv_icm42600_odr_to_period(conf.odr), + iio_buffer_enabled(indio_dev)); if (ret) goto out_unlock; @@ -718,7 +719,8 @@ struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st) { struct device *dev = regmap_get_device(st->map); const char *name; - struct inv_icm42600_timestamp *ts; + struct inv_sensors_timestamp_chip ts_chip; + struct inv_sensors_timestamp *ts; struct iio_dev *indio_dev; int ret; @@ -730,8 +732,15 @@ struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st) if (!indio_dev) return ERR_PTR(-ENOMEM); + /* + * clock period is 32kHz (31250ns) + * jitter is +/- 2% (20 per mille) + */ + ts_chip.clock_period = 31250; + ts_chip.jitter = 20; + ts_chip.init_period = inv_icm42600_odr_to_period(st->conf.accel.odr); ts = iio_priv(indio_dev); - inv_icm42600_timestamp_init(ts, inv_icm42600_odr_to_period(st->conf.gyro.odr)); + inv_sensors_timestamp_init(ts, &ts_chip); iio_device_set_drvdata(indio_dev, st); indio_dev->name = name; @@ -757,7 +766,7 @@ struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st) int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev) { struct inv_icm42600_state *st = iio_device_get_drvdata(indio_dev); - struct inv_icm42600_timestamp *ts = iio_priv(indio_dev); + struct inv_sensors_timestamp *ts = iio_priv(indio_dev); ssize_t i, size; unsigned int no; const void *accel, *gyro, *timestamp; @@ -780,15 +789,15 @@ int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev) /* update odr */ if (odr & INV_ICM42600_SENSOR_GYRO) - inv_icm42600_timestamp_apply_odr(ts, st->fifo.period, - st->fifo.nb.total, no); + inv_sensors_timestamp_apply_odr(ts, st->fifo.period, + st->fifo.nb.total, no); /* buffer is copied to userspace, zeroing it to avoid any data leak */ memset(&buffer, 0, sizeof(buffer)); memcpy(&buffer.gyro, gyro, sizeof(buffer.gyro)); /* convert 8 bits FIFO temperature in high resolution format */ buffer.temp = temp ? (*temp * 64) : 0; - ts_val = inv_icm42600_timestamp_pop(ts); + ts_val = inv_sensors_timestamp_pop(ts); iio_push_to_buffers_with_timestamp(indio_dev, &buffer, ts_val); } diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_timestamp.h b/drivers/iio/imu/inv_icm42600/inv_icm42600_timestamp.h deleted file mode 100644 index 4e4f331d4fe4..000000000000 --- a/drivers/iio/imu/inv_icm42600/inv_icm42600_timestamp.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2020 Invensense, Inc. - */ - -#ifndef INV_ICM42600_TIMESTAMP_H_ -#define INV_ICM42600_TIMESTAMP_H_ - -#include <linux/kernel.h> - -struct inv_icm42600_state; - -/** - * struct inv_icm42600_timestamp_interval - timestamps interval - * @lo: interval lower bound - * @up: interval upper bound - */ -struct inv_icm42600_timestamp_interval { - int64_t lo; - int64_t up; -}; - -/** - * struct inv_icm42600_timestamp_acc - accumulator for computing an estimation - * @val: current estimation of the value, the mean of all values - * @idx: current index of the next free place in values table - * @values: table of all measured values, use for computing the mean - */ -struct inv_icm42600_timestamp_acc { - uint32_t val; - size_t idx; - uint32_t values[32]; -}; - -/** - * struct inv_icm42600_timestamp - timestamp management states - * @it: interrupts interval timestamps - * @timestamp: store last timestamp for computing next data timestamp - * @mult: current internal period multiplier - * @new_mult: new set internal period multiplier (not yet effective) - * @period: measured current period of the sensor - * @chip_period: accumulator for computing internal chip period - */ -struct inv_icm42600_timestamp { - struct inv_icm42600_timestamp_interval it; - int64_t timestamp; - uint32_t mult; - uint32_t new_mult; - uint32_t period; - struct inv_icm42600_timestamp_acc chip_period; -}; - -void inv_icm42600_timestamp_init(struct inv_icm42600_timestamp *ts, - uint32_t period); - -int inv_icm42600_timestamp_setup(struct inv_icm42600_state *st); - -int inv_icm42600_timestamp_update_odr(struct inv_icm42600_timestamp *ts, - uint32_t period, bool fifo); - -void inv_icm42600_timestamp_interrupt(struct inv_icm42600_timestamp *ts, - uint32_t fifo_period, size_t fifo_nb, - size_t sensor_nb, int64_t timestamp); - -static inline int64_t -inv_icm42600_timestamp_pop(struct inv_icm42600_timestamp *ts) -{ - ts->timestamp += ts->period; - return ts->timestamp; -} - -void inv_icm42600_timestamp_apply_odr(struct inv_icm42600_timestamp *ts, - uint32_t fifo_period, size_t fifo_nb, - unsigned int fifo_no); - -static inline void -inv_icm42600_timestamp_reset(struct inv_icm42600_timestamp *ts) -{ - const struct inv_icm42600_timestamp_interval interval_init = {0LL, 0LL}; - - ts->it = interval_init; - ts->timestamp = 0; -} - -#endif diff --git a/drivers/iio/imu/inv_mpu6050/Kconfig b/drivers/iio/imu/inv_mpu6050/Kconfig index 64dd73dcc4ba..5f62e4fd475d 100644 --- a/drivers/iio/imu/inv_mpu6050/Kconfig +++ b/drivers/iio/imu/inv_mpu6050/Kconfig @@ -7,6 +7,7 @@ config INV_MPU6050_IIO tristate select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select IIO_INV_SENSORS_TIMESTAMP config INV_MPU6050_I2C tristate "Invensense MPU6050 devices (I2C)" diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c index 592a6e60b413..29f906c884bd 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c @@ -12,12 +12,15 @@ #include <linux/jiffies.h> #include <linux/irq.h> #include <linux/interrupt.h> -#include <linux/iio/iio.h> #include <linux/acpi.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <linux/pm.h> #include <linux/pm_runtime.h> + +#include <linux/iio/common/inv_sensors_timestamp.h> +#include <linux/iio/iio.h> + #include "inv_mpu_iio.h" #include "inv_mpu_magn.h" @@ -521,6 +524,7 @@ static int inv_mpu6050_init_config(struct iio_dev *indio_dev) int result; u8 d; struct inv_mpu6050_state *st = iio_priv(indio_dev); + struct inv_sensors_timestamp_chip timestamp; result = inv_mpu6050_set_gyro_fsr(st, st->chip_config.fsr); if (result) @@ -544,12 +548,12 @@ static int inv_mpu6050_init_config(struct iio_dev *indio_dev) if (result) return result; - /* - * Internal chip period is 1ms (1kHz). - * Let's use at the beginning the theorical value before measuring - * with interrupt timestamps. - */ - st->chip_period = NSEC_PER_MSEC; + /* clock jitter is +/- 2% */ + timestamp.clock_period = NSEC_PER_SEC / INV_MPU6050_INTERNAL_FREQ_HZ; + timestamp.jitter = 20; + timestamp.init_period = + NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider); + inv_sensors_timestamp_init(&st->timestamp, ×tamp); /* magn chip init, noop if not present in the chip */ result = inv_mpu_magn_probe(st); @@ -936,6 +940,8 @@ inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { int fifo_rate; + u32 fifo_period; + bool fifo_on; u8 d; int result; struct iio_dev *indio_dev = dev_to_iio_dev(dev); @@ -952,12 +958,21 @@ inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr, d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate); /* compute back the fifo rate to handle truncation cases */ fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d); + fifo_period = NSEC_PER_SEC / fifo_rate; mutex_lock(&st->lock); if (d == st->chip_config.divider) { result = 0; goto fifo_rate_fail_unlock; } + + fifo_on = st->chip_config.accl_fifo_enable || + st->chip_config.gyro_fifo_enable || + st->chip_config.magn_fifo_enable; + result = inv_sensors_timestamp_update_odr(&st->timestamp, fifo_period, fifo_on); + if (result) + goto fifo_rate_fail_unlock; + result = pm_runtime_resume_and_get(pdev); if (result) goto fifo_rate_fail_unlock; @@ -1330,6 +1345,9 @@ static int inv_check_and_setup_chip(struct inv_mpu6050_state *st) st->reg = hw_info[st->chip_type].reg; memcpy(&st->chip_config, hw_info[st->chip_type].config, sizeof(st->chip_config)); + st->data = devm_kzalloc(regmap_get_device(st->map), st->hw->fifo_size, GFP_KERNEL); + if (st->data == NULL) + return -ENOMEM; /* check chip self-identification */ result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val); @@ -1785,3 +1803,4 @@ EXPORT_NS_GPL_DEV_PM_OPS(inv_mpu_pmops, IIO_MPU6050) = { MODULE_AUTHOR("Invensense Corporation"); MODULE_DESCRIPTION("Invensense device MPU6050 driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(IIO_INV_SENSORS_TIMESTAMP); diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h index b4ab2c397d0f..ed5a96e78df0 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h @@ -9,15 +9,17 @@ #include <linux/i2c.h> #include <linux/i2c-mux.h> #include <linux/mutex.h> -#include <linux/iio/iio.h> -#include <linux/iio/buffer.h> +#include <linux/platform_data/invensense_mpu6050.h> #include <linux/regmap.h> -#include <linux/iio/sysfs.h> + +#include <linux/iio/buffer.h> +#include <linux/iio/common/inv_sensors_timestamp.h> +#include <linux/iio/iio.h> #include <linux/iio/kfifo_buf.h> #include <linux/iio/trigger.h> #include <linux/iio/triggered_buffer.h> #include <linux/iio/trigger_consumer.h> -#include <linux/platform_data/invensense_mpu6050.h> +#include <linux/iio/sysfs.h> /** * struct inv_mpu6050_reg_map - Notable registers. @@ -170,16 +172,14 @@ struct inv_mpu6050_hw { * @map regmap pointer. * @irq interrupt number. * @irq_mask the int_pin_cfg mask to configure interrupt type. - * @chip_period: chip internal period estimation (~1kHz). - * @it_timestamp: timestamp from previous interrupt. - * @data_timestamp: timestamp for next data sample. + * @timestamp: timestamping module * @vdd_supply: VDD voltage regulator for the chip. * @vddio_supply I/O voltage regulator for the chip. * @magn_disabled: magnetometer disabled for backward compatibility reason. * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss. * @magn_orient: magnetometer sensor chip orientation if available. * @suspended_sensors: sensors mask of sensors turned off for suspend - * @data: dma safe buffer used for bulk reads. + * @data: read buffer used for bulk reads. */ struct inv_mpu6050_state { struct mutex lock; @@ -196,16 +196,14 @@ struct inv_mpu6050_state { int irq; u8 irq_mask; unsigned skip_samples; - s64 chip_period; - s64 it_timestamp; - s64 data_timestamp; + struct inv_sensors_timestamp timestamp; struct regulator *vdd_supply; struct regulator *vddio_supply; bool magn_disabled; s32 magn_raw_to_gauss[3]; struct iio_mount_matrix magn_orient; unsigned int suspended_sensors; - u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(IIO_DMA_MINALIGN); + u8 *data; }; /*register and associated bit definition*/ diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c index 45c37525c2f1..66d4ba088e70 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c @@ -13,81 +13,10 @@ #include <linux/interrupt.h> #include <linux/poll.h> #include <linux/math64.h> -#include "inv_mpu_iio.h" - -/** - * inv_mpu6050_update_period() - Update chip internal period estimation - * - * @st: driver state - * @timestamp: the interrupt timestamp - * @nb: number of data set in the fifo - * - * This function uses interrupt timestamps to estimate the chip period and - * to choose the data timestamp to come. - */ -static void inv_mpu6050_update_period(struct inv_mpu6050_state *st, - s64 timestamp, size_t nb) -{ - /* Period boundaries for accepting timestamp */ - const s64 period_min = - (NSEC_PER_MSEC * (100 - INV_MPU6050_TS_PERIOD_JITTER)) / 100; - const s64 period_max = - (NSEC_PER_MSEC * (100 + INV_MPU6050_TS_PERIOD_JITTER)) / 100; - const s32 divider = INV_MPU6050_FREQ_DIVIDER(st); - s64 delta, interval; - bool use_it_timestamp = false; - - if (st->it_timestamp == 0) { - /* not initialized, forced to use it_timestamp */ - use_it_timestamp = true; - } else if (nb == 1) { - /* - * Validate the use of it timestamp by checking if interrupt - * has been delayed. - * nb > 1 means interrupt was delayed for more than 1 sample, - * so it's obviously not good. - * Compute the chip period between 2 interrupts for validating. - */ - delta = div_s64(timestamp - st->it_timestamp, divider); - if (delta > period_min && delta < period_max) { - /* update chip period and use it timestamp */ - st->chip_period = (st->chip_period + delta) / 2; - use_it_timestamp = true; - } - } - if (use_it_timestamp) { - /* - * Manage case of multiple samples in the fifo (nb > 1): - * compute timestamp corresponding to the first sample using - * estimated chip period. - */ - interval = (nb - 1) * st->chip_period * divider; - st->data_timestamp = timestamp - interval; - } +#include <linux/iio/common/inv_sensors_timestamp.h> - /* save it timestamp */ - st->it_timestamp = timestamp; -} - -/** - * inv_mpu6050_get_timestamp() - Return the current data timestamp - * - * @st: driver state - * @return: current data timestamp - * - * This function returns the current data timestamp and prepares for next one. - */ -static s64 inv_mpu6050_get_timestamp(struct inv_mpu6050_state *st) -{ - s64 ts; - - /* return current data timestamp and increment */ - ts = st->data_timestamp; - st->data_timestamp += st->chip_period * INV_MPU6050_FREQ_DIVIDER(st); - - return ts; -} +#include "inv_mpu_iio.h" static int inv_reset_fifo(struct iio_dev *indio_dev) { @@ -121,7 +50,9 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p) size_t bytes_per_datum; int result; u16 fifo_count; + u32 fifo_period; s64 timestamp; + u8 data[INV_MPU6050_OUTPUT_DATA_SIZE]; int int_status; size_t i, nb; @@ -175,21 +106,30 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p) goto flush_fifo; } - /* compute and process all complete datum */ + /* compute and process only all complete datum */ nb = fifo_count / bytes_per_datum; - inv_mpu6050_update_period(st, pf->timestamp, nb); + fifo_count = nb * bytes_per_datum; + /* Each FIFO data contains all sensors, so same number for FIFO and sensor data */ + fifo_period = NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider); + inv_sensors_timestamp_interrupt(&st->timestamp, fifo_period, nb, nb, pf->timestamp); + inv_sensors_timestamp_apply_odr(&st->timestamp, fifo_period, nb, 0); + + /* clear internal data buffer for avoiding kernel data leak */ + memset(data, 0, sizeof(data)); + + /* read all data once and process every samples */ + result = regmap_noinc_read(st->map, st->reg->fifo_r_w, st->data, fifo_count); + if (result) + goto flush_fifo; for (i = 0; i < nb; ++i) { - result = regmap_noinc_read(st->map, st->reg->fifo_r_w, - st->data, bytes_per_datum); - if (result) - goto flush_fifo; /* skip first samples if needed */ if (st->skip_samples) { st->skip_samples--; continue; } - timestamp = inv_mpu6050_get_timestamp(st); - iio_push_to_buffers_with_timestamp(indio_dev, st->data, timestamp); + memcpy(data, &st->data[i * bytes_per_datum], bytes_per_datum); + timestamp = inv_sensors_timestamp_pop(&st->timestamp); + iio_push_to_buffers_with_timestamp(indio_dev, data, timestamp); } end_session: diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c index 882546897255..676704f9151f 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c @@ -4,6 +4,9 @@ */ #include <linux/pm_runtime.h> + +#include <linux/iio/common/inv_sensors_timestamp.h> + #include "inv_mpu_iio.h" static unsigned int inv_scan_query_mpu6050(struct iio_dev *indio_dev) @@ -106,7 +109,8 @@ int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable) int ret; if (enable) { - st->it_timestamp = 0; + /* reset timestamping */ + inv_sensors_timestamp_reset(&st->timestamp); /* reset FIFO */ d = st->chip_config.user_ctrl | INV_MPU6050_BIT_FIFO_RST; ret = regmap_write(st->map, st->reg->user_ctrl, d); diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index adcba832e6fa..d752e9c0499b 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* The industrial I/O core +/* + * The industrial I/O core * * Copyright (c) 2008 Jonathan Cameron * @@ -183,7 +184,9 @@ static const char * const iio_chan_info_postfix[] = { * @indio_dev: Device structure whose ID is being queried * * The IIO device ID is a unique index used for example for the naming - * of the character device /dev/iio\:device[ID] + * of the character device /dev/iio\:device[ID]. + * + * Returns: Unique ID for the device. */ int iio_device_id(struct iio_dev *indio_dev) { @@ -196,14 +199,16 @@ EXPORT_SYMBOL_GPL(iio_device_id); /** * iio_buffer_enabled() - helper function to test if the buffer is enabled * @indio_dev: IIO device structure for device + * + * Returns: True, if the buffer is enabled. */ bool iio_buffer_enabled(struct iio_dev *indio_dev) { struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); - return iio_dev_opaque->currentmode - & (INDIO_BUFFER_TRIGGERED | INDIO_BUFFER_HARDWARE | - INDIO_BUFFER_SOFTWARE); + return iio_dev_opaque->currentmode & + (INDIO_BUFFER_HARDWARE | INDIO_BUFFER_SOFTWARE | + INDIO_BUFFER_TRIGGERED); } EXPORT_SYMBOL_GPL(iio_buffer_enabled); @@ -225,6 +230,9 @@ EXPORT_SYMBOL_GPL(iio_get_debugfs_dentry); * iio_find_channel_from_si() - get channel from its scan index * @indio_dev: device * @si: scan index to match + * + * Returns: + * Constant pointer to iio_chan_spec, if scan index matches, NULL on failure. */ const struct iio_chan_spec *iio_find_channel_from_si(struct iio_dev *indio_dev, int si) @@ -249,7 +257,9 @@ EXPORT_SYMBOL(iio_read_const_attr); /** * iio_device_set_clock() - Set current timestamping clock for the device * @indio_dev: IIO device structure containing the device - * @clock_id: timestamping clock posix identifier to set. + * @clock_id: timestamping clock POSIX identifier to set. + * + * Returns: 0 on success, or a negative error code. */ int iio_device_set_clock(struct iio_dev *indio_dev, clockid_t clock_id) { @@ -275,6 +285,8 @@ EXPORT_SYMBOL(iio_device_set_clock); /** * iio_device_get_clock() - Retrieve current timestamping clock for the device * @indio_dev: IIO device structure containing the device + * + * Returns: Clock ID of the current timestamping clock for the device. */ clockid_t iio_device_get_clock(const struct iio_dev *indio_dev) { @@ -287,6 +299,8 @@ EXPORT_SYMBOL(iio_device_get_clock); /** * iio_get_time_ns() - utility function to get a time stamp for events etc * @indio_dev: device + * + * Returns: Timestamp of the event in nanoseconds. */ s64 iio_get_time_ns(const struct iio_dev *indio_dev) { @@ -372,8 +386,8 @@ static ssize_t iio_debugfs_read_reg(struct file *file, char __user *userbuf, } iio_dev_opaque->read_buf_len = snprintf(iio_dev_opaque->read_buf, - sizeof(iio_dev_opaque->read_buf), - "0x%X\n", val); + sizeof(iio_dev_opaque->read_buf), + "0x%X\n", val); return simple_read_from_buffer(userbuf, count, ppos, iio_dev_opaque->read_buf, @@ -389,7 +403,7 @@ static ssize_t iio_debugfs_write_reg(struct file *file, char buf[80]; int ret; - count = min_t(size_t, count, (sizeof(buf)-1)); + count = min(count, sizeof(buf) - 1); if (copy_from_user(buf, userbuf, count)) return -EFAULT; @@ -476,8 +490,7 @@ static ssize_t iio_read_channel_ext_info(struct device *dev, static ssize_t iio_write_channel_ext_info(struct device *dev, struct device_attribute *attr, - const char *buf, - size_t len) + const char *buf, size_t len) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); @@ -524,7 +537,7 @@ ssize_t iio_enum_read(struct iio_dev *indio_dev, i = e->get(indio_dev, chan); if (i < 0) return i; - else if (i >= e->num_items || !e->items[i]) + if (i >= e->num_items || !e->items[i]) return -EINVAL; return sysfs_emit(buf, "%s\n", e->items[i]); @@ -569,9 +582,9 @@ static int iio_setup_mount_idmatrix(const struct device *dev, ssize_t iio_show_mount_matrix(struct iio_dev *indio_dev, uintptr_t priv, const struct iio_chan_spec *chan, char *buf) { - const struct iio_mount_matrix *mtx = ((iio_get_mount_matrix_t *) - priv)(indio_dev, chan); + const struct iio_mount_matrix *mtx; + mtx = ((iio_get_mount_matrix_t *)priv)(indio_dev, chan); if (IS_ERR(mtx)) return PTR_ERR(mtx); @@ -594,7 +607,7 @@ EXPORT_SYMBOL_GPL(iio_show_mount_matrix); * If device is assigned no mounting matrix property, a default 3x3 identity * matrix will be filled in. * - * Return: 0 if success, or a negative error code on failure. + * Returns: 0 if success, or a negative error code on failure. */ int iio_read_mount_matrix(struct device *dev, struct iio_mount_matrix *matrix) { @@ -692,9 +705,9 @@ static ssize_t __iio_format_value(char *buf, size_t offset, unsigned int type, * @vals: Pointer to the values, exact meaning depends on the * type parameter. * - * Return: 0 by default, a negative number on failure or the - * total number of characters written for a type that belongs - * to the IIO_VAL_* constant. + * Returns: + * 0 by default, a negative number on failure or the total number of characters + * written for a type that belongs to the IIO_VAL_* constant. */ ssize_t iio_format_value(char *buf, unsigned int type, int size, int *vals) { @@ -847,8 +860,8 @@ static ssize_t iio_read_channel_info_avail(struct device *dev, * @fract: The fractional part of the number * @scale_db: True if this should parse as dB * - * Returns 0 on success, or a negative error code if the string could not be - * parsed. + * Returns: + * 0 on success, or a negative error code if the string could not be parsed. */ static int __iio_str_to_fixpoint(const char *str, int fract_mult, int *integer, int *fract, bool scale_db) @@ -917,8 +930,8 @@ static int __iio_str_to_fixpoint(const char *str, int fract_mult, * @integer: The integer part of the number * @fract: The fractional part of the number * - * Returns 0 on success, or a negative error code if the string could not be - * parsed. + * Returns: + * 0 on success, or a negative error code if the string could not be parsed. */ int iio_str_to_fixpoint(const char *str, int fract_mult, int *integer, int *fract) @@ -1009,14 +1022,12 @@ int __iio_device_attr_init(struct device_attribute *dev_attr, if (chan->modified && (shared_by == IIO_SEPARATE)) { if (chan->extend_name) full_postfix = kasprintf(GFP_KERNEL, "%s_%s_%s", - iio_modifier_names[chan - ->channel2], + iio_modifier_names[chan->channel2], chan->extend_name, postfix); else full_postfix = kasprintf(GFP_KERNEL, "%s_%s", - iio_modifier_names[chan - ->channel2], + iio_modifier_names[chan->channel2], postfix); } else { if (chan->extend_name == NULL || shared_by != IIO_SEPARATE) @@ -1217,7 +1228,7 @@ static int iio_device_add_info_mask_type(struct iio_dev *indio_dev, &iio_dev_opaque->channel_attr_list); if ((ret == -EBUSY) && (shared_by != IIO_SEPARATE)) continue; - else if (ret < 0) + if (ret < 0) return ret; attrcount++; } @@ -1255,7 +1266,7 @@ static int iio_device_add_info_mask_type_avail(struct iio_dev *indio_dev, kfree(avail_postfix); if ((ret == -EBUSY) && (shared_by != IIO_SEPARATE)) continue; - else if (ret < 0) + if (ret < 0) return ret; attrcount++; } @@ -1400,50 +1411,42 @@ static ssize_t label_show(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR_RO(label); +static const char * const clock_names[] = { + [CLOCK_REALTIME] = "realtime", + [CLOCK_MONOTONIC] = "monotonic", + [CLOCK_PROCESS_CPUTIME_ID] = "process_cputime_id", + [CLOCK_THREAD_CPUTIME_ID] = "thread_cputime_id", + [CLOCK_MONOTONIC_RAW] = "monotonic_raw", + [CLOCK_REALTIME_COARSE] = "realtime_coarse", + [CLOCK_MONOTONIC_COARSE] = "monotonic_coarse", + [CLOCK_BOOTTIME] = "boottime", + [CLOCK_REALTIME_ALARM] = "realtime_alarm", + [CLOCK_BOOTTIME_ALARM] = "boottime_alarm", + [CLOCK_SGI_CYCLE] = "sgi_cycle", + [CLOCK_TAI] = "tai", +}; + static ssize_t current_timestamp_clock_show(struct device *dev, struct device_attribute *attr, char *buf) { const struct iio_dev *indio_dev = dev_to_iio_dev(dev); const clockid_t clk = iio_device_get_clock(indio_dev); - const char *name; - ssize_t sz; switch (clk) { case CLOCK_REALTIME: - name = "realtime\n"; - sz = sizeof("realtime\n"); - break; case CLOCK_MONOTONIC: - name = "monotonic\n"; - sz = sizeof("monotonic\n"); - break; case CLOCK_MONOTONIC_RAW: - name = "monotonic_raw\n"; - sz = sizeof("monotonic_raw\n"); - break; case CLOCK_REALTIME_COARSE: - name = "realtime_coarse\n"; - sz = sizeof("realtime_coarse\n"); - break; case CLOCK_MONOTONIC_COARSE: - name = "monotonic_coarse\n"; - sz = sizeof("monotonic_coarse\n"); - break; case CLOCK_BOOTTIME: - name = "boottime\n"; - sz = sizeof("boottime\n"); - break; case CLOCK_TAI: - name = "tai\n"; - sz = sizeof("tai\n"); break; default: BUG(); } - memcpy(buf, name, sz); - return sz; + return sysfs_emit(buf, "%s\n", clock_names[clk]); } static ssize_t current_timestamp_clock_store(struct device *dev, @@ -1453,22 +1456,23 @@ static ssize_t current_timestamp_clock_store(struct device *dev, clockid_t clk; int ret; - if (sysfs_streq(buf, "realtime")) - clk = CLOCK_REALTIME; - else if (sysfs_streq(buf, "monotonic")) - clk = CLOCK_MONOTONIC; - else if (sysfs_streq(buf, "monotonic_raw")) - clk = CLOCK_MONOTONIC_RAW; - else if (sysfs_streq(buf, "realtime_coarse")) - clk = CLOCK_REALTIME_COARSE; - else if (sysfs_streq(buf, "monotonic_coarse")) - clk = CLOCK_MONOTONIC_COARSE; - else if (sysfs_streq(buf, "boottime")) - clk = CLOCK_BOOTTIME; - else if (sysfs_streq(buf, "tai")) - clk = CLOCK_TAI; - else + ret = sysfs_match_string(clock_names, buf); + if (ret < 0) + return ret; + clk = ret; + + switch (clk) { + case CLOCK_REALTIME: + case CLOCK_MONOTONIC: + case CLOCK_MONOTONIC_RAW: + case CLOCK_REALTIME_COARSE: + case CLOCK_MONOTONIC_COARSE: + case CLOCK_BOOTTIME: + case CLOCK_TAI: + break; + default: return -EINVAL; + } ret = iio_device_set_clock(dev_to_iio_dev(dev), clk); if (ret) @@ -1484,7 +1488,7 @@ int iio_device_register_sysfs_group(struct iio_dev *indio_dev, const struct attribute_group **new, **old = iio_dev_opaque->groups; unsigned int cnt = iio_dev_opaque->groupcounter; - new = krealloc(old, sizeof(*new) * (cnt + 2), GFP_KERNEL); + new = krealloc_array(old, cnt + 2, sizeof(*new), GFP_KERNEL); if (!new) return -ENOMEM; @@ -1621,7 +1625,10 @@ const struct device_type iio_device_type = { * iio_device_alloc() - allocate an iio_dev from a driver * @parent: Parent device. * @sizeof_priv: Space to allocate for private structure. - **/ + * + * Returns: + * Pointer to allocated iio_dev on success, NULL on failure. + */ struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv) { struct iio_dev_opaque *iio_dev_opaque; @@ -1677,7 +1684,7 @@ EXPORT_SYMBOL(iio_device_alloc); /** * iio_device_free() - free an iio_dev from a driver * @dev: the iio_dev associated with the device - **/ + */ void iio_device_free(struct iio_dev *dev) { if (dev) @@ -1698,7 +1705,7 @@ static void devm_iio_device_release(void *iio_dev) * Managed iio_device_alloc. iio_dev allocated with this function is * automatically freed on driver detach. * - * RETURNS: + * Returns: * Pointer to allocated iio_dev on success, NULL on failure. */ struct iio_dev *devm_iio_device_alloc(struct device *parent, int sizeof_priv) @@ -1725,8 +1732,8 @@ EXPORT_SYMBOL_GPL(devm_iio_device_alloc); * @filp: File structure for iio device used to keep and later access * private data * - * Return: 0 on success or -EBUSY if the device is already opened - **/ + * Returns: 0 on success or -EBUSY if the device is already opened + */ static int iio_chrdev_open(struct inode *inode, struct file *filp) { struct iio_dev_opaque *iio_dev_opaque = @@ -1759,7 +1766,7 @@ static int iio_chrdev_open(struct inode *inode, struct file *filp) * @inode: Inode structure pointer for the char device * @filp: File structure pointer for the char device * - * Return: 0 for successful release + * Returns: 0 for successful release. */ static int iio_chrdev_release(struct inode *inode, struct file *filp) { @@ -1798,7 +1805,7 @@ static long iio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) mutex_lock(&iio_dev_opaque->info_exist_lock); - /** + /* * The NULL check here is required to prevent crashing when a device * is being removed while userspace would still have open file handles * to try to access this device. @@ -1976,7 +1983,7 @@ EXPORT_SYMBOL(__iio_device_register); /** * iio_device_unregister() - unregister a device from the IIO subsystem * @indio_dev: Device structure representing the device. - **/ + */ void iio_device_unregister(struct iio_dev *indio_dev) { struct iio_dev_opaque *iio_dev_opaque = to_iio_dev_opaque(indio_dev); @@ -2027,7 +2034,7 @@ EXPORT_SYMBOL_GPL(__devm_iio_device_register); * * Use with iio_device_release_direct_mode() * - * Returns: 0 on success, -EBUSY on failure + * Returns: 0 on success, -EBUSY on failure. */ int iio_device_claim_direct_mode(struct iio_dev *indio_dev) { diff --git a/drivers/iio/industrialio-event.c b/drivers/iio/industrialio-event.c index f77ce49d4c36..19f7a91157ee 100644 --- a/drivers/iio/industrialio-event.c +++ b/drivers/iio/industrialio-event.c @@ -252,6 +252,8 @@ static const char * const iio_ev_info_text[] = { [IIO_EV_INFO_TIMEOUT] = "timeout", [IIO_EV_INFO_RESET_TIMEOUT] = "reset_timeout", [IIO_EV_INFO_TAP2_MIN_DELAY] = "tap2_min_delay", + [IIO_EV_INFO_RUNNING_PERIOD] = "runningperiod", + [IIO_EV_INFO_RUNNING_COUNT] = "runningcount", }; static enum iio_event_direction iio_ev_attr_dir(struct iio_dev_attr *attr) diff --git a/drivers/iio/industrialio-trigger.c b/drivers/iio/industrialio-trigger.c index f207e36b12cc..18f83158f637 100644 --- a/drivers/iio/industrialio-trigger.c +++ b/drivers/iio/industrialio-trigger.c @@ -313,7 +313,7 @@ int iio_trigger_attach_poll_func(struct iio_trigger *trig, /* Enable trigger in driver */ if (trig->ops && trig->ops->set_trigger_state && notinuse) { ret = trig->ops->set_trigger_state(trig, true); - if (ret < 0) + if (ret) goto out_free_irq; } diff --git a/drivers/iio/light/cm3605.c b/drivers/iio/light/cm3605.c index 0b30db77f78b..e7f0b81b7f5a 100644 --- a/drivers/iio/light/cm3605.c +++ b/drivers/iio/light/cm3605.c @@ -227,7 +227,7 @@ static int cm3605_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) { - ret = dev_err_probe(dev, irq, "failed to get irq\n"); + ret = irq; goto out_disable_aset; } diff --git a/drivers/iio/light/rohm-bu27008.c b/drivers/iio/light/rohm-bu27008.c index b50bf8973d9a..6a6d77805091 100644 --- a/drivers/iio/light/rohm-bu27008.c +++ b/drivers/iio/light/rohm-bu27008.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * BU27008 ROHM Colour Sensor + * ROHM Colour Sensor driver for + * - BU27008 RGBC sensor + * - BU27010 RGBC + Flickering sensor * * Copyright (c) 2023, ROHM Semiconductor. */ @@ -22,6 +24,25 @@ #include <linux/iio/trigger_consumer.h> #include <linux/iio/triggered_buffer.h> +/* + * A word about register address and mask definitions. + * + * At a quick glance to the data-sheet register tables, the BU27010 has all the + * registers that the BU27008 has. On top of that the BU27010 adds couple of new + * ones. + * + * So, all definitions BU27008_REG_* are there also for BU27010 but none of the + * BU27010_REG_* are present on BU27008. This makes sense as BU27010 just adds + * some features (Flicker FIFO, more power control) on top of the BU27008. + * + * Unfortunately, some of the wheel has been re-invented. Even though the names + * of the registers have stayed the same, pretty much all of the functionality + * provided by the registers has changed place. Contents of all MODE_CONTROL + * registers on BU27008 and BU27010 are different. + * + * Chip-specific mapping from register addresses/bits to functionality is done + * in bu27_chip_data structures. + */ #define BU27008_REG_SYSTEM_CONTROL 0x40 #define BU27008_MASK_SW_RESET BIT(7) #define BU27008_MASK_PART_ID GENMASK(5, 0) @@ -52,6 +73,56 @@ #define BU27008_REG_MANUFACTURER_ID 0x92 #define BU27008_REG_MAX BU27008_REG_MANUFACTURER_ID +/* BU27010 specific definitions */ + +#define BU27010_MASK_SW_RESET BIT(7) +#define BU27010_ID 0x1b +#define BU27010_REG_POWER 0x3e +#define BU27010_MASK_POWER BIT(0) + +#define BU27010_REG_RESET 0x3f +#define BU27010_MASK_RESET BIT(0) +#define BU27010_RESET_RELEASE BU27010_MASK_RESET + +#define BU27010_MASK_MEAS_EN BIT(1) + +#define BU27010_MASK_CHAN_SEL GENMASK(7, 6) +#define BU27010_MASK_MEAS_MODE GENMASK(5, 4) +#define BU27010_MASK_RGBC_GAIN GENMASK(3, 0) + +#define BU27010_MASK_DATA3_GAIN GENMASK(7, 6) +#define BU27010_MASK_DATA2_GAIN GENMASK(5, 4) +#define BU27010_MASK_DATA1_GAIN GENMASK(3, 2) +#define BU27010_MASK_DATA0_GAIN GENMASK(1, 0) + +#define BU27010_MASK_FLC_MODE BIT(7) +#define BU27010_MASK_FLC_GAIN GENMASK(4, 0) + +#define BU27010_REG_MODE_CONTROL4 0x44 +/* If flicker is ever to be supported the IRQ must be handled as a field */ +#define BU27010_IRQ_DIS_ALL GENMASK(1, 0) +#define BU27010_DRDY_EN BIT(0) +#define BU27010_MASK_INT_SEL GENMASK(1, 0) + +#define BU27010_REG_MODE_CONTROL5 0x45 +#define BU27010_MASK_RGB_VALID BIT(7) +#define BU27010_MASK_FLC_VALID BIT(6) +#define BU27010_MASK_WAIT_EN BIT(3) +#define BU27010_MASK_FIFO_EN BIT(2) +#define BU27010_MASK_RGB_EN BIT(1) +#define BU27010_MASK_FLC_EN BIT(0) + +#define BU27010_REG_DATA_FLICKER_LO 0x56 +#define BU27010_MASK_DATA_FLICKER_HI GENMASK(2, 0) +#define BU27010_REG_FLICKER_COUNT 0x5a +#define BU27010_REG_FIFO_LEVEL_LO 0x5b +#define BU27010_MASK_FIFO_LEVEL_HI BIT(0) +#define BU27010_REG_FIFO_DATA_LO 0x5d +#define BU27010_REG_FIFO_DATA_HI 0x5e +#define BU27010_MASK_FIFO_DATA_HI GENMASK(2, 0) +#define BU27010_REG_MANUFACTURER_ID 0x92 +#define BU27010_REG_MAX BU27010_REG_MANUFACTURER_ID + /** * enum bu27008_chan_type - BU27008 channel types * @BU27008_RED: Red channel. Always via data0. @@ -117,6 +188,17 @@ static const unsigned long bu27008_scan_masks[] = { */ #define BU27008_SCALE_1X 16 +/* + * On BU27010 available scales with gain 1x - 4096x, + * timings 55, 100, 200, 400 mS. Time impacts to gain: 1x, 2x, 4x, 8x. + * + * => Max total gain is HWGAIN * gain by integration time (8 * 4096) + * + * Using NANO precision for scale we must use scale 64x corresponding gain 1x + * to avoid precision loss. + */ +#define BU27010_SCALE_1X 64 + /* See the data sheet for the "Gain Setting" table */ #define BU27008_GSEL_1X 0x00 #define BU27008_GSEL_4X 0x08 @@ -152,10 +234,44 @@ static const struct iio_gain_sel_pair bu27008_gains_ir[] = { GAIN_SCALE_GAIN(1024, BU27008_GSEL_1024X), }; +#define BU27010_GSEL_1X 0x00 /* 000000 */ +#define BU27010_GSEL_4X 0x08 /* 001000 */ +#define BU27010_GSEL_16X 0x09 /* 001001 */ +#define BU27010_GSEL_64X 0x0e /* 001110 */ +#define BU27010_GSEL_256X 0x1e /* 011110 */ +#define BU27010_GSEL_1024X 0x2e /* 101110 */ +#define BU27010_GSEL_4096X 0x3f /* 111111 */ + +static const struct iio_gain_sel_pair bu27010_gains[] = { + GAIN_SCALE_GAIN(1, BU27010_GSEL_1X), + GAIN_SCALE_GAIN(4, BU27010_GSEL_4X), + GAIN_SCALE_GAIN(16, BU27010_GSEL_16X), + GAIN_SCALE_GAIN(64, BU27010_GSEL_64X), + GAIN_SCALE_GAIN(256, BU27010_GSEL_256X), + GAIN_SCALE_GAIN(1024, BU27010_GSEL_1024X), + GAIN_SCALE_GAIN(4096, BU27010_GSEL_4096X), +}; + +static const struct iio_gain_sel_pair bu27010_gains_ir[] = { + GAIN_SCALE_GAIN(2, BU27010_GSEL_1X), + GAIN_SCALE_GAIN(4, BU27010_GSEL_4X), + GAIN_SCALE_GAIN(16, BU27010_GSEL_16X), + GAIN_SCALE_GAIN(64, BU27010_GSEL_64X), + GAIN_SCALE_GAIN(256, BU27010_GSEL_256X), + GAIN_SCALE_GAIN(1024, BU27010_GSEL_1024X), + GAIN_SCALE_GAIN(4096, BU27010_GSEL_4096X), +}; + #define BU27008_MEAS_MODE_100MS 0x00 #define BU27008_MEAS_MODE_55MS 0x01 #define BU27008_MEAS_MODE_200MS 0x02 #define BU27008_MEAS_MODE_400MS 0x04 + +#define BU27010_MEAS_MODE_100MS 0x00 +#define BU27010_MEAS_MODE_55MS 0x03 +#define BU27010_MEAS_MODE_200MS 0x01 +#define BU27010_MEAS_MODE_400MS 0x02 + #define BU27008_MEAS_TIME_MAX_MS 400 static const struct iio_itime_sel_mul bu27008_itimes[] = { @@ -165,6 +281,13 @@ static const struct iio_itime_sel_mul bu27008_itimes[] = { GAIN_SCALE_ITIME_US(55000, BU27008_MEAS_MODE_55MS, 1), }; +static const struct iio_itime_sel_mul bu27010_itimes[] = { + GAIN_SCALE_ITIME_US(400000, BU27010_MEAS_MODE_400MS, 8), + GAIN_SCALE_ITIME_US(200000, BU27010_MEAS_MODE_200MS, 4), + GAIN_SCALE_ITIME_US(100000, BU27010_MEAS_MODE_100MS, 2), + GAIN_SCALE_ITIME_US(55000, BU27010_MEAS_MODE_55MS, 1), +}; + /* * All the RGBC channels share the same gain. * IR gain can be fine-tuned from the gain set for the RGBC by 2 bit, but this @@ -211,7 +334,35 @@ static const struct iio_chan_spec bu27008_channels[] = { IIO_CHAN_SOFT_TIMESTAMP(BU27008_NUM_CHANS), }; +struct bu27008_data; + +struct bu27_chip_data { + const char *name; + int (*chip_init)(struct bu27008_data *data); + int (*get_gain_sel)(struct bu27008_data *data, int *sel); + int (*write_gain_sel)(struct bu27008_data *data, int sel); + const struct regmap_config *regmap_cfg; + const struct iio_gain_sel_pair *gains; + const struct iio_gain_sel_pair *gains_ir; + const struct iio_itime_sel_mul *itimes; + int num_gains; + int num_gains_ir; + int num_itimes; + int scale1x; + + int drdy_en_reg; + int drdy_en_mask; + int meas_en_reg; + int meas_en_mask; + int valid_reg; + int chan_sel_reg; + int chan_sel_mask; + int int_time_mask; + u8 part_id; +}; + struct bu27008_data { + const struct bu27_chip_data *cd; struct regmap *regmap; struct iio_trigger *trig; struct device *dev; @@ -240,11 +391,29 @@ static const struct regmap_range bu27008_volatile_ranges[] = { }, }; +static const struct regmap_range bu27010_volatile_ranges[] = { + { + .range_min = BU27010_REG_RESET, /* RSTB */ + .range_max = BU27008_REG_SYSTEM_CONTROL, /* RESET */ + }, { + .range_min = BU27010_REG_MODE_CONTROL5, /* VALID bits */ + .range_max = BU27010_REG_MODE_CONTROL5, + }, { + .range_min = BU27008_REG_DATA0_LO, + .range_max = BU27010_REG_FIFO_DATA_HI, + }, +}; + static const struct regmap_access_table bu27008_volatile_regs = { .yes_ranges = &bu27008_volatile_ranges[0], .n_yes_ranges = ARRAY_SIZE(bu27008_volatile_ranges), }; +static const struct regmap_access_table bu27010_volatile_regs = { + .yes_ranges = &bu27010_volatile_ranges[0], + .n_yes_ranges = ARRAY_SIZE(bu27010_volatile_ranges), +}; + static const struct regmap_range bu27008_read_only_ranges[] = { { .range_min = BU27008_REG_DATA0_LO, @@ -255,11 +424,26 @@ static const struct regmap_range bu27008_read_only_ranges[] = { }, }; +static const struct regmap_range bu27010_read_only_ranges[] = { + { + .range_min = BU27008_REG_DATA0_LO, + .range_max = BU27010_REG_FIFO_DATA_HI, + }, { + .range_min = BU27010_REG_MANUFACTURER_ID, + .range_max = BU27010_REG_MANUFACTURER_ID, + } +}; + static const struct regmap_access_table bu27008_ro_regs = { .no_ranges = &bu27008_read_only_ranges[0], .n_no_ranges = ARRAY_SIZE(bu27008_read_only_ranges), }; +static const struct regmap_access_table bu27010_ro_regs = { + .no_ranges = &bu27010_read_only_ranges[0], + .n_no_ranges = ARRAY_SIZE(bu27010_read_only_ranges), +}; + static const struct regmap_config bu27008_regmap = { .reg_bits = 8, .val_bits = 8, @@ -282,50 +466,16 @@ static const struct regmap_config bu27008_regmap = { .disable_locking = true, }; -#define BU27008_MAX_VALID_RESULT_WAIT_US 50000 -#define BU27008_VALID_RESULT_WAIT_QUANTA_US 1000 - -static int bu27008_chan_read_data(struct bu27008_data *data, int reg, int *val) -{ - int ret, valid; - __le16 tmp; - - ret = regmap_read_poll_timeout(data->regmap, BU27008_REG_MODE_CONTROL3, - valid, (valid & BU27008_MASK_VALID), - BU27008_VALID_RESULT_WAIT_QUANTA_US, - BU27008_MAX_VALID_RESULT_WAIT_US); - if (ret) - return ret; - - ret = regmap_bulk_read(data->regmap, reg, &tmp, sizeof(tmp)); - if (ret) - dev_err(data->dev, "Reading channel data failed\n"); - - *val = le16_to_cpu(tmp); - - return ret; -} - -static int bu27008_get_gain(struct bu27008_data *data, struct iio_gts *gts, int *gain) -{ - int ret, sel; - - ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, &sel); - if (ret) - return ret; - - sel = FIELD_GET(BU27008_MASK_RGBC_GAIN, sel); +static const struct regmap_config bu27010_regmap = { + .reg_bits = 8, + .val_bits = 8, - ret = iio_gts_find_gain_by_sel(gts, sel); - if (ret < 0) { - dev_err(data->dev, "unknown gain value 0x%x\n", sel); - return ret; - } - - *gain = ret; - - return 0; -} + .max_register = BU27010_REG_MAX, + .cache_type = REGCACHE_RBTREE, + .volatile_table = &bu27010_volatile_regs, + .wr_table = &bu27010_ro_regs, + .disable_locking = true, +}; static int bu27008_write_gain_sel(struct bu27008_data *data, int sel) { @@ -368,6 +518,264 @@ static int bu27008_write_gain_sel(struct bu27008_data *data, int sel) BU27008_MASK_RGBC_GAIN, regval); } +static int bu27010_write_gain_sel(struct bu27008_data *data, int sel) +{ + unsigned int regval; + int ret, chan_selector; + + /* + * Gain 'selector' is composed of two registers. Selector is 6bit value, + * 4 high bits being the RGBC gain fieild in MODE_CONTROL1 register and + * two low bits being the channel specific gain in MODE_CONTROL2. + * + * Let's take the 4 high bits of whole 6 bit selector, and prepare + * the MODE_CONTROL1 value (RGBC gain part). + */ + regval = FIELD_PREP(BU27010_MASK_RGBC_GAIN, (sel >> 2)); + + ret = regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1, + BU27010_MASK_RGBC_GAIN, regval); + if (ret) + return ret; + + /* + * Two low two bits of the selector must be written for all 4 + * channels in the MODE_CONTROL2 register. Copy these two bits for + * all channels. + */ + chan_selector = sel & GENMASK(1, 0); + + regval = FIELD_PREP(BU27010_MASK_DATA0_GAIN, chan_selector); + regval |= FIELD_PREP(BU27010_MASK_DATA1_GAIN, chan_selector); + regval |= FIELD_PREP(BU27010_MASK_DATA2_GAIN, chan_selector); + regval |= FIELD_PREP(BU27010_MASK_DATA3_GAIN, chan_selector); + + return regmap_write(data->regmap, BU27008_REG_MODE_CONTROL2, regval); +} + +static int bu27008_get_gain_sel(struct bu27008_data *data, int *sel) +{ + int ret; + + /* + * If we always "lock" the gain selectors for all channels to prevent + * unsupported configs, then it does not matter which channel is used + * we can just return selector from any of them. + * + * This, however is not true if we decide to support only 4X and 16X + * and then individual gains for channels. Currently this is not the + * case. + * + * If we some day decide to support individual gains, then we need to + * have channel information here. + */ + + ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, sel); + if (ret) + return ret; + + *sel = FIELD_GET(BU27008_MASK_RGBC_GAIN, *sel); + + return 0; +} + +static int bu27010_get_gain_sel(struct bu27008_data *data, int *sel) +{ + int ret, tmp; + + /* + * We always "lock" the gain selectors for all channels to prevent + * unsupported configs. It does not matter which channel is used + * we can just return selector from any of them. + * + * Read the channel0 gain. + */ + ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL2, sel); + if (ret) + return ret; + + *sel = FIELD_GET(BU27010_MASK_DATA0_GAIN, *sel); + + /* Read the shared gain */ + ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL1, &tmp); + if (ret) + return ret; + + /* + * The gain selector is made as a combination of common RGBC gain and + * the channel specific gain. The channel specific gain forms the low + * bits of selector and RGBC gain is appended right after it. + * + * Compose the selector from channel0 gain and shared RGBC gain. + */ + *sel |= FIELD_GET(BU27010_MASK_RGBC_GAIN, tmp) << fls(BU27010_MASK_DATA0_GAIN); + + return ret; +} + +static int bu27008_chip_init(struct bu27008_data *data) +{ + int ret; + + ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL, + BU27008_MASK_SW_RESET, BU27008_MASK_SW_RESET); + if (ret) + return dev_err_probe(data->dev, ret, "Sensor reset failed\n"); + + /* + * The data-sheet does not tell how long performing the IC reset takes. + * However, the data-sheet says the minimum time it takes the IC to be + * able to take inputs after power is applied, is 100 uS. I'd assume + * > 1 mS is enough. + */ + msleep(1); + + ret = regmap_reinit_cache(data->regmap, data->cd->regmap_cfg); + if (ret) + dev_err(data->dev, "Failed to reinit reg cache\n"); + + return ret; +} + +static int bu27010_chip_init(struct bu27008_data *data) +{ + int ret; + + ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL, + BU27010_MASK_SW_RESET, BU27010_MASK_SW_RESET); + if (ret) + return dev_err_probe(data->dev, ret, "Sensor reset failed\n"); + + msleep(1); + + /* Power ON*/ + ret = regmap_write_bits(data->regmap, BU27010_REG_POWER, + BU27010_MASK_POWER, BU27010_MASK_POWER); + if (ret) + return dev_err_probe(data->dev, ret, "Sensor power-on failed\n"); + + msleep(1); + + /* Release blocks from reset */ + ret = regmap_write_bits(data->regmap, BU27010_REG_RESET, + BU27010_MASK_RESET, BU27010_RESET_RELEASE); + if (ret) + return dev_err_probe(data->dev, ret, "Sensor powering failed\n"); + + msleep(1); + + /* + * The IRQ enabling on BU27010 is done in a peculiar way. The IRQ + * enabling is not a bit mask where individual IRQs could be enabled but + * a field which values are: + * 00 => IRQs disabled + * 01 => Data-ready (RGBC/IR) + * 10 => Data-ready (flicker) + * 11 => Flicker FIFO + * + * So, only one IRQ can be enabled at a time and enabling for example + * flicker FIFO would automagically disable data-ready IRQ. + * + * Currently the driver does not support the flicker. Hence, we can + * just treat the RGBC data-ready as single bit which can be enabled / + * disabled. This works for as long as the second bit in the field + * stays zero. Here we ensure it gets zeroed. + */ + return regmap_clear_bits(data->regmap, BU27010_REG_MODE_CONTROL4, + BU27010_IRQ_DIS_ALL); +} + +static const struct bu27_chip_data bu27010_chip = { + .name = "bu27010", + .chip_init = bu27010_chip_init, + .get_gain_sel = bu27010_get_gain_sel, + .write_gain_sel = bu27010_write_gain_sel, + .regmap_cfg = &bu27010_regmap, + .gains = &bu27010_gains[0], + .gains_ir = &bu27010_gains_ir[0], + .itimes = &bu27010_itimes[0], + .num_gains = ARRAY_SIZE(bu27010_gains), + .num_gains_ir = ARRAY_SIZE(bu27010_gains_ir), + .num_itimes = ARRAY_SIZE(bu27010_itimes), + .scale1x = BU27010_SCALE_1X, + .drdy_en_reg = BU27010_REG_MODE_CONTROL4, + .drdy_en_mask = BU27010_DRDY_EN, + .meas_en_reg = BU27010_REG_MODE_CONTROL5, + .meas_en_mask = BU27010_MASK_MEAS_EN, + .valid_reg = BU27010_REG_MODE_CONTROL5, + .chan_sel_reg = BU27008_REG_MODE_CONTROL1, + .chan_sel_mask = BU27010_MASK_CHAN_SEL, + .int_time_mask = BU27010_MASK_MEAS_MODE, + .part_id = BU27010_ID, +}; + +static const struct bu27_chip_data bu27008_chip = { + .name = "bu27008", + .chip_init = bu27008_chip_init, + .get_gain_sel = bu27008_get_gain_sel, + .write_gain_sel = bu27008_write_gain_sel, + .regmap_cfg = &bu27008_regmap, + .gains = &bu27008_gains[0], + .gains_ir = &bu27008_gains_ir[0], + .itimes = &bu27008_itimes[0], + .num_gains = ARRAY_SIZE(bu27008_gains), + .num_gains_ir = ARRAY_SIZE(bu27008_gains_ir), + .num_itimes = ARRAY_SIZE(bu27008_itimes), + .scale1x = BU27008_SCALE_1X, + .drdy_en_reg = BU27008_REG_MODE_CONTROL3, + .drdy_en_mask = BU27008_MASK_INT_EN, + .valid_reg = BU27008_REG_MODE_CONTROL3, + .meas_en_reg = BU27008_REG_MODE_CONTROL3, + .meas_en_mask = BU27008_MASK_MEAS_EN, + .chan_sel_reg = BU27008_REG_MODE_CONTROL3, + .chan_sel_mask = BU27008_MASK_CHAN_SEL, + .int_time_mask = BU27008_MASK_MEAS_MODE, + .part_id = BU27008_ID, +}; + +#define BU27008_MAX_VALID_RESULT_WAIT_US 50000 +#define BU27008_VALID_RESULT_WAIT_QUANTA_US 1000 + +static int bu27008_chan_read_data(struct bu27008_data *data, int reg, int *val) +{ + int ret, valid; + __le16 tmp; + + ret = regmap_read_poll_timeout(data->regmap, data->cd->valid_reg, + valid, (valid & BU27008_MASK_VALID), + BU27008_VALID_RESULT_WAIT_QUANTA_US, + BU27008_MAX_VALID_RESULT_WAIT_US); + if (ret) + return ret; + + ret = regmap_bulk_read(data->regmap, reg, &tmp, sizeof(tmp)); + if (ret) + dev_err(data->dev, "Reading channel data failed\n"); + + *val = le16_to_cpu(tmp); + + return ret; +} + +static int bu27008_get_gain(struct bu27008_data *data, struct iio_gts *gts, int *gain) +{ + int ret, sel; + + ret = data->cd->get_gain_sel(data, &sel); + if (ret) + return ret; + + ret = iio_gts_find_gain_by_sel(gts, sel); + if (ret < 0) { + dev_err(data->dev, "unknown gain value 0x%x\n", sel); + return ret; + } + + *gain = ret; + + return 0; +} + static int bu27008_set_gain(struct bu27008_data *data, int gain) { int ret; @@ -376,7 +784,7 @@ static int bu27008_set_gain(struct bu27008_data *data, int gain) if (ret < 0) return ret; - return bu27008_write_gain_sel(data, ret); + return data->cd->write_gain_sel(data, ret); } static int bu27008_get_int_time_sel(struct bu27008_data *data, int *sel) @@ -384,15 +792,23 @@ static int bu27008_get_int_time_sel(struct bu27008_data *data, int *sel) int ret, val; ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL1, &val); - *sel = FIELD_GET(BU27008_MASK_MEAS_MODE, val); + if (ret) + return ret; - return ret; + val &= data->cd->int_time_mask; + val >>= ffs(data->cd->int_time_mask) - 1; + + *sel = val; + + return 0; } static int bu27008_set_int_time_sel(struct bu27008_data *data, int sel) { + sel <<= ffs(data->cd->int_time_mask) - 1; + return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1, - BU27008_MASK_MEAS_MODE, sel); + data->cd->int_time_mask, sel); } static int bu27008_get_int_time_us(struct bu27008_data *data) @@ -448,8 +864,7 @@ static int bu27008_set_int_time(struct bu27008_data *data, int time) if (ret < 0) return ret; - return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL1, - BU27008_MASK_MEAS_MODE, ret); + return bu27008_set_int_time_sel(data, ret); } /* Try to change the time so that the scale is maintained */ @@ -527,10 +942,13 @@ unlock_out: return ret; } -static int bu27008_meas_set(struct bu27008_data *data, int state) +static int bu27008_meas_set(struct bu27008_data *data, bool enable) { - return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3, - BU27008_MASK_MEAS_EN, state); + if (enable) + return regmap_set_bits(data->regmap, data->cd->meas_en_reg, + data->cd->meas_en_mask); + return regmap_clear_bits(data->regmap, data->cd->meas_en_reg, + data->cd->meas_en_mask); } static int bu27008_chan_cfg(struct bu27008_data *data, @@ -543,9 +961,15 @@ static int bu27008_chan_cfg(struct bu27008_data *data, else chan_sel = BU27008_CLEAR2_IR3; - chan_sel = FIELD_PREP(BU27008_MASK_CHAN_SEL, chan_sel); + /* + * prepare bitfield for channel sel. The FIELD_PREP works only when + * mask is constant. In our case the mask is assigned based on the + * chip type. Hence the open-coded FIELD_PREP here. We don't bother + * zeroing the irrelevant bits though - update_bits takes care of that. + */ + chan_sel <<= ffs(data->cd->chan_sel_mask) - 1; - return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3, + return regmap_update_bits(data->regmap, data->cd->chan_sel_reg, BU27008_MASK_CHAN_SEL, chan_sel); } @@ -558,7 +982,7 @@ static int bu27008_read_one(struct bu27008_data *data, struct iio_dev *idev, if (ret) return ret; - ret = bu27008_meas_set(data, BU27008_MEAS_EN); + ret = bu27008_meas_set(data, true); if (ret) return ret; @@ -574,7 +998,7 @@ static int bu27008_read_one(struct bu27008_data *data, struct iio_dev *idev, if (!ret) ret = IIO_VAL_INT; - if (bu27008_meas_set(data, BU27008_MEAS_DIS)) + if (bu27008_meas_set(data, false)) dev_warn(data->dev, "measurement disabling failed\n"); return ret; @@ -669,7 +1093,7 @@ static int bu27008_set_scale(struct bu27008_data *data, goto unlock_out; } - ret = bu27008_write_gain_sel(data, gain_sel); + ret = data->cd->write_gain_sel(data, gain_sel); unlock_out: mutex_unlock(&data->mutex); @@ -762,10 +1186,10 @@ static int bu27008_update_scan_mode(struct iio_dev *idev, chan_sel = BU27008_CLEAR2_IR3; } - chan_sel = FIELD_PREP(BU27008_MASK_CHAN_SEL, chan_sel); + chan_sel <<= ffs(data->cd->chan_sel_mask) - 1; - return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3, - BU27008_MASK_CHAN_SEL, chan_sel); + return regmap_update_bits(data->regmap, data->cd->chan_sel_reg, + data->cd->chan_sel_mask, chan_sel); } static const struct iio_info bu27008_info = { @@ -777,46 +1201,18 @@ static const struct iio_info bu27008_info = { .validate_trigger = iio_validate_own_trigger, }; -static int bu27008_chip_init(struct bu27008_data *data) -{ - int ret; - - ret = regmap_write_bits(data->regmap, BU27008_REG_SYSTEM_CONTROL, - BU27008_MASK_SW_RESET, BU27008_MASK_SW_RESET); - if (ret) - return dev_err_probe(data->dev, ret, "Sensor reset failed\n"); - - /* - * The data-sheet does not tell how long performing the IC reset takes. - * However, the data-sheet says the minimum time it takes the IC to be - * able to take inputs after power is applied, is 100 uS. I'd assume - * > 1 mS is enough. - */ - msleep(1); - - ret = regmap_reinit_cache(data->regmap, &bu27008_regmap); - if (ret) - dev_err(data->dev, "Failed to reinit reg cache\n"); - - return ret; -} - -static int bu27008_set_drdy_irq(struct bu27008_data *data, int state) -{ - return regmap_update_bits(data->regmap, BU27008_REG_MODE_CONTROL3, - BU27008_MASK_INT_EN, state); -} - -static int bu27008_trigger_set_state(struct iio_trigger *trig, - bool state) +static int bu27008_trigger_set_state(struct iio_trigger *trig, bool state) { struct bu27008_data *data = iio_trigger_get_drvdata(trig); int ret; + if (state) - ret = bu27008_set_drdy_irq(data, BU27008_INT_EN); + ret = regmap_set_bits(data->regmap, data->cd->drdy_en_reg, + data->cd->drdy_en_mask); else - ret = bu27008_set_drdy_irq(data, BU27008_INT_DIS); + ret = regmap_clear_bits(data->regmap, data->cd->drdy_en_reg, + data->cd->drdy_en_mask); if (ret) dev_err(data->dev, "Failed to set trigger state\n"); @@ -852,7 +1248,7 @@ static irqreturn_t bu27008_trigger_handler(int irq, void *p) * After some measurements, it seems reading the * BU27008_REG_MODE_CONTROL3 debounces the IRQ line */ - ret = regmap_read(data->regmap, BU27008_REG_MODE_CONTROL3, &dummy); + ret = regmap_read(data->regmap, data->cd->valid_reg, &dummy); if (ret < 0) goto err_read; @@ -872,14 +1268,14 @@ static int bu27008_buffer_preenable(struct iio_dev *idev) { struct bu27008_data *data = iio_priv(idev); - return bu27008_meas_set(data, BU27008_MEAS_EN); + return bu27008_meas_set(data, true); } static int bu27008_buffer_postdisable(struct iio_dev *idev) { struct bu27008_data *data = iio_priv(idev); - return bu27008_meas_set(data, BU27008_MEAS_DIS); + return bu27008_meas_set(data, false); } static const struct iio_buffer_setup_ops bu27008_buffer_ops = { @@ -952,11 +1348,6 @@ static int bu27008_probe(struct i2c_client *i2c) struct iio_dev *idev; int ret; - regmap = devm_regmap_init_i2c(i2c, &bu27008_regmap); - if (IS_ERR(regmap)) - return dev_err_probe(dev, PTR_ERR(regmap), - "Failed to initialize Regmap\n"); - idev = devm_iio_device_alloc(dev, sizeof(*data)); if (!idev) return -ENOMEM; @@ -967,24 +1358,34 @@ static int bu27008_probe(struct i2c_client *i2c) data = iio_priv(idev); + data->cd = device_get_match_data(&i2c->dev); + if (!data->cd) + return -ENODEV; + + regmap = devm_regmap_init_i2c(i2c, data->cd->regmap_cfg); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Failed to initialize Regmap\n"); + + ret = regmap_read(regmap, BU27008_REG_SYSTEM_CONTROL, ®); if (ret) return dev_err_probe(dev, ret, "Failed to access sensor\n"); part_id = FIELD_GET(BU27008_MASK_PART_ID, reg); - if (part_id != BU27008_ID) + if (part_id != data->cd->part_id) dev_warn(dev, "unknown device 0x%x\n", part_id); - ret = devm_iio_init_iio_gts(dev, BU27008_SCALE_1X, 0, bu27008_gains, - ARRAY_SIZE(bu27008_gains), bu27008_itimes, - ARRAY_SIZE(bu27008_itimes), &data->gts); + ret = devm_iio_init_iio_gts(dev, data->cd->scale1x, 0, data->cd->gains, + data->cd->num_gains, data->cd->itimes, + data->cd->num_itimes, &data->gts); if (ret) return ret; - ret = devm_iio_init_iio_gts(dev, BU27008_SCALE_1X, 0, bu27008_gains_ir, - ARRAY_SIZE(bu27008_gains_ir), bu27008_itimes, - ARRAY_SIZE(bu27008_itimes), &data->gts_ir); + ret = devm_iio_init_iio_gts(dev, data->cd->scale1x, 0, data->cd->gains_ir, + data->cd->num_gains_ir, data->cd->itimes, + data->cd->num_itimes, &data->gts_ir); if (ret) return ret; @@ -995,12 +1396,12 @@ static int bu27008_probe(struct i2c_client *i2c) idev->channels = bu27008_channels; idev->num_channels = ARRAY_SIZE(bu27008_channels); - idev->name = "bu27008"; + idev->name = data->cd->name; idev->info = &bu27008_info; idev->modes = INDIO_DIRECT_MODE; idev->available_scan_masks = bu27008_scan_masks; - ret = bu27008_chip_init(data); + ret = data->cd->chip_init(data); if (ret) return ret; @@ -1021,7 +1422,8 @@ static int bu27008_probe(struct i2c_client *i2c) } static const struct of_device_id bu27008_of_match[] = { - { .compatible = "rohm,bu27008" }, + { .compatible = "rohm,bu27008", .data = &bu27008_chip }, + { .compatible = "rohm,bu27010", .data = &bu27010_chip }, { } }; MODULE_DEVICE_TABLE(of, bu27008_of_match); @@ -1036,7 +1438,7 @@ static struct i2c_driver bu27008_i2c_driver = { }; module_i2c_driver(bu27008_i2c_driver); -MODULE_DESCRIPTION("ROHM BU27008 colour sensor driver"); +MODULE_DESCRIPTION("ROHM BU27008 and BU27010 colour sensor driver"); MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); MODULE_LICENSE("GPL"); MODULE_IMPORT_NS(IIO_GTS_HELPER); diff --git a/drivers/iio/light/vcnl4000.c b/drivers/iio/light/vcnl4000.c index 7c7362e28821..3a52b09c2823 100644 --- a/drivers/iio/light/vcnl4000.c +++ b/drivers/iio/light/vcnl4000.c @@ -24,6 +24,7 @@ #include <linux/delay.h> #include <linux/pm_runtime.h> #include <linux/interrupt.h> +#include <linux/units.h> #include <linux/iio/buffer.h> #include <linux/iio/events.h> @@ -60,11 +61,15 @@ #define VCNL4200_AL_CONF 0x00 /* Ambient light configuration */ #define VCNL4200_PS_CONF1 0x03 /* Proximity configuration */ +#define VCNL4200_PS_CONF3 0x04 /* Proximity configuration */ #define VCNL4040_PS_THDL_LM 0x06 /* Proximity threshold low */ #define VCNL4040_PS_THDH_LM 0x07 /* Proximity threshold high */ +#define VCNL4040_ALS_THDL_LM 0x02 /* Ambient light threshold low */ +#define VCNL4040_ALS_THDH_LM 0x01 /* Ambient light threshold high */ #define VCNL4200_PS_DATA 0x08 /* Proximity data */ #define VCNL4200_AL_DATA 0x09 /* Ambient light data */ #define VCNL4040_INT_FLAGS 0x0b /* Interrupt register */ +#define VCNL4200_INT_FLAGS 0x0d /* Interrupt register */ #define VCNL4200_DEV_ID 0x0e /* Device ID, slave address and version */ #define VCNL4040_DEV_ID 0x0c /* Device ID and version */ @@ -79,11 +84,19 @@ #define VCNL4000_SELF_TIMED_EN BIT(0) /* start self-timed measurement */ #define VCNL4040_ALS_CONF_ALS_SHUTDOWN BIT(0) +#define VCNL4040_ALS_CONF_IT GENMASK(7, 6) /* Ambient integration time */ +#define VCNL4040_ALS_CONF_INT_EN BIT(1) /* Ambient light Interrupt enable */ +#define VCNL4040_ALS_CONF_PERS GENMASK(3, 2) /* Ambient interrupt persistence setting */ #define VCNL4040_PS_CONF1_PS_SHUTDOWN BIT(0) #define VCNL4040_PS_CONF2_PS_IT GENMASK(3, 1) /* Proximity integration time */ +#define VCNL4040_CONF1_PS_PERS GENMASK(5, 4) /* Proximity interrupt persistence setting */ #define VCNL4040_PS_CONF2_PS_INT GENMASK(9, 8) /* Proximity interrupt mode */ +#define VCNL4040_PS_CONF3_MPS GENMASK(6, 5) /* Proximity multi pulse number */ +#define VCNL4040_PS_MS_LED_I GENMASK(10, 8) /* Proximity current */ #define VCNL4040_PS_IF_AWAY BIT(8) /* Proximity event cross low threshold */ #define VCNL4040_PS_IF_CLOSE BIT(9) /* Proximity event cross high threshold */ +#define VCNL4040_ALS_RISING BIT(12) /* Ambient Light cross high threshold */ +#define VCNL4040_ALS_FALLING BIT(13) /* Ambient Light cross low threshold */ /* Bit masks for interrupt registers. */ #define VCNL4010_INT_THR_SEL BIT(0) /* Select threshold interrupt source */ @@ -123,6 +136,44 @@ static const int vcnl4040_ps_it_times[][2] = { {0, 800}, }; +static const int vcnl4200_ps_it_times[][2] = { + {0, 96}, + {0, 144}, + {0, 192}, + {0, 384}, + {0, 768}, + {0, 864}, +}; + +static const int vcnl4040_als_it_times[][2] = { + {0, 80000}, + {0, 160000}, + {0, 320000}, + {0, 640000}, +}; + +static const int vcnl4200_als_it_times[][2] = { + {0, 50000}, + {0, 100000}, + {0, 200000}, + {0, 400000}, +}; + +static const int vcnl4040_ps_calibbias_ua[][2] = { + {0, 50000}, + {0, 75000}, + {0, 100000}, + {0, 120000}, + {0, 140000}, + {0, 160000}, + {0, 180000}, + {0, 200000}, +}; + +static const int vcnl4040_als_persistence[] = {1, 2, 4, 8}; +static const int vcnl4040_ps_persistence[] = {1, 2, 3, 4}; +static const int vcnl4040_ps_oversampling_ratio[] = {1, 2, 4, 8}; + #define VCNL4000_SLEEP_DELAY_MS 2000 /* before we enter pm_runtime_suspend */ enum vcnl4000_device_ids { @@ -145,6 +196,7 @@ struct vcnl4000_data { int rev; int al_scale; u8 ps_int; /* proximity interrupt mode */ + u8 als_int; /* ambient light interrupt mode*/ const struct vcnl4000_chip_spec *chip_spec; struct mutex vcnl4000_lock; struct vcnl4200_channel vcnl4200_al; @@ -164,6 +216,13 @@ struct vcnl4000_chip_spec { int (*set_power_state)(struct vcnl4000_data *data, bool on); irqreturn_t (*irq_thread)(int irq, void *priv); irqreturn_t (*trig_buffer_func)(int irq, void *priv); + + u8 int_reg; + const int(*ps_it_times)[][2]; + const int num_ps_it_times; + const int(*als_it_times)[][2]; + const int num_als_it_times; + const unsigned int ulux_step; }; static const struct i2c_device_id vcnl4000_id[] = { @@ -263,7 +322,7 @@ static int vcnl4200_set_power_state(struct vcnl4000_data *data, bool on) int ret; /* Do not power down if interrupts are enabled */ - if (!on && data->ps_int) + if (!on && (data->ps_int || data->als_int)) return 0; ret = vcnl4000_write_als_enable(data, on); @@ -308,6 +367,7 @@ static int vcnl4200_init(struct vcnl4000_data *data) data->rev = (ret >> 8) & 0xf; data->ps_int = 0; + data->als_int = 0; data->vcnl4200_al.reg = VCNL4200_AL_DATA; data->vcnl4200_ps.reg = VCNL4200_PS_DATA; @@ -317,16 +377,15 @@ static int vcnl4200_init(struct vcnl4000_data *data) data->vcnl4200_al.sampling_rate = ktime_set(0, 60000 * 1000); /* Default wait time is 4.8ms, add 20% tolerance. */ data->vcnl4200_ps.sampling_rate = ktime_set(0, 5760 * 1000); - data->al_scale = 24000; break; case VCNL4040_PROD_ID: /* Default wait time is 80ms, add 20% tolerance. */ data->vcnl4200_al.sampling_rate = ktime_set(0, 96000 * 1000); /* Default wait time is 5ms, add 20% tolerance. */ data->vcnl4200_ps.sampling_rate = ktime_set(0, 6000 * 1000); - data->al_scale = 120000; break; } + data->al_scale = data->chip_spec->ulux_step; mutex_init(&data->vcnl4200_al.lock); mutex_init(&data->vcnl4200_ps.lock); @@ -496,6 +555,60 @@ static int vcnl4000_set_pm_runtime_state(struct vcnl4000_data *data, bool on) return ret; } +static int vcnl4040_read_als_it(struct vcnl4000_data *data, int *val, int *val2) +{ + int ret; + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF); + if (ret < 0) + return ret; + + ret = FIELD_GET(VCNL4040_ALS_CONF_IT, ret); + if (ret >= data->chip_spec->num_als_it_times) + return -EINVAL; + + *val = (*data->chip_spec->als_it_times)[ret][0]; + *val2 = (*data->chip_spec->als_it_times)[ret][1]; + + return 0; +} + +static ssize_t vcnl4040_write_als_it(struct vcnl4000_data *data, int val) +{ + unsigned int i; + int ret; + u16 regval; + + for (i = 0; i < data->chip_spec->num_als_it_times; i++) { + if (val == (*data->chip_spec->als_it_times)[i][1]) + break; + } + + if (i == data->chip_spec->num_als_it_times) + return -EINVAL; + + data->vcnl4200_al.sampling_rate = ktime_set(0, val * 1200); + data->al_scale = div_u64(mul_u32_u32(data->chip_spec->ulux_step, + (*data->chip_spec->als_it_times)[0][1]), + val); + + mutex_lock(&data->vcnl4000_lock); + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF); + if (ret < 0) + goto out_unlock; + + regval = FIELD_PREP(VCNL4040_ALS_CONF_IT, i); + regval |= (ret & ~VCNL4040_ALS_CONF_IT); + ret = i2c_smbus_write_word_data(data->client, + VCNL4200_AL_CONF, + regval); + +out_unlock: + mutex_unlock(&data->vcnl4000_lock); + return ret; +} + static int vcnl4040_read_ps_it(struct vcnl4000_data *data, int *val, int *val2) { int ret; @@ -506,11 +619,11 @@ static int vcnl4040_read_ps_it(struct vcnl4000_data *data, int *val, int *val2) ret = FIELD_GET(VCNL4040_PS_CONF2_PS_IT, ret); - if (ret >= ARRAY_SIZE(vcnl4040_ps_it_times)) + if (ret >= data->chip_spec->num_ps_it_times) return -EINVAL; - *val = vcnl4040_ps_it_times[ret][0]; - *val2 = vcnl4040_ps_it_times[ret][1]; + *val = (*data->chip_spec->ps_it_times)[ret][0]; + *val2 = (*data->chip_spec->ps_it_times)[ret][1]; return 0; } @@ -521,8 +634,8 @@ static ssize_t vcnl4040_write_ps_it(struct vcnl4000_data *data, int val) int ret, index = -1; u16 regval; - for (i = 0; i < ARRAY_SIZE(vcnl4040_ps_it_times); i++) { - if (val == vcnl4040_ps_it_times[i][1]) { + for (i = 0; i < data->chip_spec->num_ps_it_times; i++) { + if (val == (*data->chip_spec->ps_it_times)[i][1]) { index = i; break; } @@ -531,6 +644,8 @@ static ssize_t vcnl4040_write_ps_it(struct vcnl4000_data *data, int val) if (index < 0) return -EINVAL; + data->vcnl4200_ps.sampling_rate = ktime_set(0, val * 60 * NSEC_PER_USEC); + mutex_lock(&data->vcnl4000_lock); ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); @@ -547,6 +662,224 @@ out: return ret; } +static ssize_t vcnl4040_read_als_period(struct vcnl4000_data *data, int *val, int *val2) +{ + int ret, ret_pers, it; + int64_t val_c; + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF); + if (ret < 0) + return ret; + + ret_pers = FIELD_GET(VCNL4040_ALS_CONF_PERS, ret); + if (ret_pers >= ARRAY_SIZE(vcnl4040_als_persistence)) + return -EINVAL; + + it = FIELD_GET(VCNL4040_ALS_CONF_IT, ret); + if (it >= data->chip_spec->num_als_it_times) + return -EINVAL; + + val_c = mul_u32_u32((*data->chip_spec->als_it_times)[it][1], + vcnl4040_als_persistence[ret_pers]); + *val = div_u64_rem(val_c, MICRO, val2); + + return IIO_VAL_INT_PLUS_MICRO; +} + +static ssize_t vcnl4040_write_als_period(struct vcnl4000_data *data, int val, int val2) +{ + unsigned int i; + int ret, it; + u16 regval; + u64 val_n = mul_u32_u32(val, MICRO) + val2; + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF); + if (ret < 0) + return ret; + + it = FIELD_GET(VCNL4040_ALS_CONF_IT, ret); + if (it >= data->chip_spec->num_als_it_times) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(vcnl4040_als_persistence) - 1; i++) { + if (val_n < mul_u32_u32(vcnl4040_als_persistence[i], + (*data->chip_spec->als_it_times)[it][1])) + break; + } + + mutex_lock(&data->vcnl4000_lock); + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF); + if (ret < 0) + goto out_unlock; + + regval = FIELD_PREP(VCNL4040_ALS_CONF_PERS, i); + regval |= (ret & ~VCNL4040_ALS_CONF_PERS); + ret = i2c_smbus_write_word_data(data->client, VCNL4200_AL_CONF, + regval); + +out_unlock: + mutex_unlock(&data->vcnl4000_lock); + return ret; +} + +static ssize_t vcnl4040_read_ps_period(struct vcnl4000_data *data, int *val, int *val2) +{ + int ret, ret_pers, it; + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); + if (ret < 0) + return ret; + + ret_pers = FIELD_GET(VCNL4040_CONF1_PS_PERS, ret); + if (ret_pers >= ARRAY_SIZE(vcnl4040_ps_persistence)) + return -EINVAL; + + it = FIELD_GET(VCNL4040_PS_CONF2_PS_IT, ret); + if (it >= data->chip_spec->num_ps_it_times) + return -EINVAL; + + *val = (*data->chip_spec->ps_it_times)[it][0]; + *val2 = (*data->chip_spec->ps_it_times)[it][1] * + vcnl4040_ps_persistence[ret_pers]; + + return IIO_VAL_INT_PLUS_MICRO; +} + +static ssize_t vcnl4040_write_ps_period(struct vcnl4000_data *data, int val, int val2) +{ + int ret, it, i; + u16 regval; + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); + if (ret < 0) + return ret; + + it = FIELD_GET(VCNL4040_PS_CONF2_PS_IT, ret); + if (it >= data->chip_spec->num_ps_it_times) + return -EINVAL; + + if (val > 0) + i = ARRAY_SIZE(vcnl4040_ps_persistence) - 1; + else { + for (i = 0; i < ARRAY_SIZE(vcnl4040_ps_persistence) - 1; i++) { + if (val2 <= vcnl4040_ps_persistence[i] * + (*data->chip_spec->ps_it_times)[it][1]) + break; + } + } + + mutex_lock(&data->vcnl4000_lock); + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); + if (ret < 0) + goto out_unlock; + + regval = FIELD_PREP(VCNL4040_CONF1_PS_PERS, i); + regval |= (ret & ~VCNL4040_CONF1_PS_PERS); + ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, + regval); + +out_unlock: + mutex_unlock(&data->vcnl4000_lock); + return ret; +} + +static ssize_t vcnl4040_read_ps_oversampling_ratio(struct vcnl4000_data *data, int *val) +{ + int ret; + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3); + if (ret < 0) + return ret; + + ret = FIELD_GET(VCNL4040_PS_CONF3_MPS, ret); + if (ret >= ARRAY_SIZE(vcnl4040_ps_oversampling_ratio)) + return -EINVAL; + + *val = vcnl4040_ps_oversampling_ratio[ret]; + + return ret; +} + +static ssize_t vcnl4040_write_ps_oversampling_ratio(struct vcnl4000_data *data, int val) +{ + unsigned int i; + int ret; + u16 regval; + + for (i = 0; i < ARRAY_SIZE(vcnl4040_ps_oversampling_ratio); i++) { + if (val == vcnl4040_ps_oversampling_ratio[i]) + break; + } + + if (i >= ARRAY_SIZE(vcnl4040_ps_oversampling_ratio)) + return -EINVAL; + + mutex_lock(&data->vcnl4000_lock); + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3); + if (ret < 0) + goto out_unlock; + + regval = FIELD_PREP(VCNL4040_PS_CONF3_MPS, i); + regval |= (ret & ~VCNL4040_PS_CONF3_MPS); + ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF3, + regval); + +out_unlock: + mutex_unlock(&data->vcnl4000_lock); + return ret; +} + +static ssize_t vcnl4040_read_ps_calibbias(struct vcnl4000_data *data, int *val, int *val2) +{ + int ret; + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3); + if (ret < 0) + return ret; + + ret = FIELD_GET(VCNL4040_PS_MS_LED_I, ret); + if (ret >= ARRAY_SIZE(vcnl4040_ps_calibbias_ua)) + return -EINVAL; + + *val = vcnl4040_ps_calibbias_ua[ret][0]; + *val2 = vcnl4040_ps_calibbias_ua[ret][1]; + + return ret; +} + +static ssize_t vcnl4040_write_ps_calibbias(struct vcnl4000_data *data, int val) +{ + unsigned int i; + int ret; + u16 regval; + + for (i = 0; i < ARRAY_SIZE(vcnl4040_ps_calibbias_ua); i++) { + if (val == vcnl4040_ps_calibbias_ua[i][1]) + break; + } + + if (i >= ARRAY_SIZE(vcnl4040_ps_calibbias_ua)) + return -EINVAL; + + mutex_lock(&data->vcnl4000_lock); + + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF3); + if (ret < 0) + goto out_unlock; + + regval = (ret & ~VCNL4040_PS_MS_LED_I); + regval |= FIELD_PREP(VCNL4040_PS_MS_LED_I, i); + ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF3, + regval); + +out_unlock: + mutex_unlock(&data->vcnl4000_lock); + return ret; +} + static int vcnl4000_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -584,12 +917,39 @@ static int vcnl4000_read_raw(struct iio_dev *indio_dev, *val2 = data->al_scale; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_INT_TIME: - if (chan->type != IIO_PROXIMITY) + switch (chan->type) { + case IIO_LIGHT: + ret = vcnl4040_read_als_it(data, val, val2); + break; + case IIO_PROXIMITY: + ret = vcnl4040_read_ps_it(data, val, val2); + break; + default: return -EINVAL; - ret = vcnl4040_read_ps_it(data, val, val2); + } if (ret < 0) return ret; return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + switch (chan->type) { + case IIO_PROXIMITY: + ret = vcnl4040_read_ps_oversampling_ratio(data, val); + if (ret < 0) + return ret; + return IIO_VAL_INT; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_CALIBBIAS: + switch (chan->type) { + case IIO_PROXIMITY: + ret = vcnl4040_read_ps_calibbias(data, val, val2); + if (ret < 0) + return ret; + return IIO_VAL_INT_PLUS_MICRO; + default: + return -EINVAL; + } default: return -EINVAL; } @@ -605,9 +965,28 @@ static int vcnl4040_write_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_INT_TIME: if (val != 0) return -EINVAL; - if (chan->type != IIO_PROXIMITY) + switch (chan->type) { + case IIO_LIGHT: + return vcnl4040_write_als_it(data, val2); + case IIO_PROXIMITY: + return vcnl4040_write_ps_it(data, val2); + default: return -EINVAL; - return vcnl4040_write_ps_it(data, val2); + } + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + switch (chan->type) { + case IIO_PROXIMITY: + return vcnl4040_write_ps_oversampling_ratio(data, val); + default: + return -EINVAL; + } + case IIO_CHAN_INFO_CALIBBIAS: + switch (chan->type) { + case IIO_PROXIMITY: + return vcnl4040_write_ps_calibbias(data, val2); + default: + return -EINVAL; + } default: return -EINVAL; } @@ -618,12 +997,44 @@ static int vcnl4040_read_avail(struct iio_dev *indio_dev, const int **vals, int *type, int *length, long mask) { + struct vcnl4000_data *data = iio_priv(indio_dev); + switch (mask) { case IIO_CHAN_INFO_INT_TIME: - *vals = (int *)vcnl4040_ps_it_times; + switch (chan->type) { + case IIO_LIGHT: + *vals = (int *)(*data->chip_spec->als_it_times); + *length = 2 * data->chip_spec->num_als_it_times; + break; + case IIO_PROXIMITY: + *vals = (int *)(*data->chip_spec->ps_it_times); + *length = 2 * data->chip_spec->num_ps_it_times; + break; + default: + return -EINVAL; + } *type = IIO_VAL_INT_PLUS_MICRO; - *length = 2 * ARRAY_SIZE(vcnl4040_ps_it_times); return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + switch (chan->type) { + case IIO_PROXIMITY: + *vals = (int *)vcnl4040_ps_oversampling_ratio; + *length = ARRAY_SIZE(vcnl4040_ps_oversampling_ratio); + *type = IIO_VAL_INT; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } + case IIO_CHAN_INFO_CALIBBIAS: + switch (chan->type) { + case IIO_PROXIMITY: + *vals = (int *)vcnl4040_ps_calibbias_ua; + *length = 2 * ARRAY_SIZE(vcnl4040_ps_calibbias_ua); + *type = IIO_VAL_INT_PLUS_MICRO; + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } default: return -EINVAL; } @@ -818,24 +1229,58 @@ static int vcnl4040_read_event(struct iio_dev *indio_dev, int ret; struct vcnl4000_data *data = iio_priv(indio_dev); - switch (dir) { - case IIO_EV_DIR_RISING: - ret = i2c_smbus_read_word_data(data->client, - VCNL4040_PS_THDH_LM); - if (ret < 0) - return ret; - *val = ret; - return IIO_VAL_INT; - case IIO_EV_DIR_FALLING: - ret = i2c_smbus_read_word_data(data->client, - VCNL4040_PS_THDL_LM); - if (ret < 0) - return ret; - *val = ret; - return IIO_VAL_INT; + switch (chan->type) { + case IIO_LIGHT: + switch (info) { + case IIO_EV_INFO_PERIOD: + return vcnl4040_read_als_period(data, val, val2); + case IIO_EV_INFO_VALUE: + switch (dir) { + case IIO_EV_DIR_RISING: + ret = i2c_smbus_read_word_data(data->client, + VCNL4040_ALS_THDH_LM); + break; + case IIO_EV_DIR_FALLING: + ret = i2c_smbus_read_word_data(data->client, + VCNL4040_ALS_THDL_LM); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + break; + case IIO_PROXIMITY: + switch (info) { + case IIO_EV_INFO_PERIOD: + return vcnl4040_read_ps_period(data, val, val2); + case IIO_EV_INFO_VALUE: + switch (dir) { + case IIO_EV_DIR_RISING: + ret = i2c_smbus_read_word_data(data->client, + VCNL4040_PS_THDH_LM); + break; + case IIO_EV_DIR_FALLING: + ret = i2c_smbus_read_word_data(data->client, + VCNL4040_PS_THDL_LM); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + break; default: return -EINVAL; } + if (ret < 0) + return ret; + *val = ret; + return IIO_VAL_INT; } static int vcnl4040_write_event(struct iio_dev *indio_dev, @@ -848,22 +1293,61 @@ static int vcnl4040_write_event(struct iio_dev *indio_dev, int ret; struct vcnl4000_data *data = iio_priv(indio_dev); - switch (dir) { - case IIO_EV_DIR_RISING: - ret = i2c_smbus_write_word_data(data->client, - VCNL4040_PS_THDH_LM, val); - if (ret < 0) - return ret; - return IIO_VAL_INT; - case IIO_EV_DIR_FALLING: - ret = i2c_smbus_write_word_data(data->client, - VCNL4040_PS_THDL_LM, val); - if (ret < 0) - return ret; - return IIO_VAL_INT; + switch (chan->type) { + case IIO_LIGHT: + switch (info) { + case IIO_EV_INFO_PERIOD: + return vcnl4040_write_als_period(data, val, val2); + case IIO_EV_INFO_VALUE: + switch (dir) { + case IIO_EV_DIR_RISING: + ret = i2c_smbus_write_word_data(data->client, + VCNL4040_ALS_THDH_LM, + val); + break; + case IIO_EV_DIR_FALLING: + ret = i2c_smbus_write_word_data(data->client, + VCNL4040_ALS_THDL_LM, + val); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + break; + case IIO_PROXIMITY: + switch (info) { + case IIO_EV_INFO_PERIOD: + return vcnl4040_write_ps_period(data, val, val2); + case IIO_EV_INFO_VALUE: + switch (dir) { + case IIO_EV_DIR_RISING: + ret = i2c_smbus_write_word_data(data->client, + VCNL4040_PS_THDH_LM, + val); + break; + case IIO_EV_DIR_FALLING: + ret = i2c_smbus_write_word_data(data->client, + VCNL4040_PS_THDL_LM, + val); + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + break; default: return -EINVAL; } + if (ret < 0) + return ret; + return IIO_VAL_INT; } static bool vcnl4010_is_thr_enabled(struct vcnl4000_data *data) @@ -956,15 +1440,28 @@ static int vcnl4040_read_event_config(struct iio_dev *indio_dev, int ret; struct vcnl4000_data *data = iio_priv(indio_dev); - ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); - if (ret < 0) - return ret; + switch (chan->type) { + case IIO_LIGHT: + ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF); + if (ret < 0) + return ret; + + data->als_int = FIELD_GET(VCNL4040_ALS_CONF_INT_EN, ret); - data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, ret); + return data->als_int; + case IIO_PROXIMITY: + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); + if (ret < 0) + return ret; - return (dir == IIO_EV_DIR_RISING) ? - FIELD_GET(VCNL4040_PS_IF_AWAY, ret) : - FIELD_GET(VCNL4040_PS_IF_CLOSE, ret); + data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, ret); + + return (dir == IIO_EV_DIR_RISING) ? + FIELD_GET(VCNL4040_PS_IF_AWAY, ret) : + FIELD_GET(VCNL4040_PS_IF_CLOSE, ret); + default: + return -EINVAL; + } } static int vcnl4040_write_event_config(struct iio_dev *indio_dev, @@ -972,29 +1469,51 @@ static int vcnl4040_write_event_config(struct iio_dev *indio_dev, enum iio_event_type type, enum iio_event_direction dir, int state) { - int ret; + int ret = -EINVAL; u16 val, mask; struct vcnl4000_data *data = iio_priv(indio_dev); mutex_lock(&data->vcnl4000_lock); - ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); - if (ret < 0) - goto out; + switch (chan->type) { + case IIO_LIGHT: + ret = i2c_smbus_read_word_data(data->client, VCNL4200_AL_CONF); + if (ret < 0) + goto out; - if (dir == IIO_EV_DIR_RISING) - mask = VCNL4040_PS_IF_AWAY; - else - mask = VCNL4040_PS_IF_CLOSE; + mask = VCNL4040_ALS_CONF_INT_EN; + if (state) + val = (ret | mask); + else + val = (ret & ~mask); - val = state ? (ret | mask) : (ret & ~mask); + data->als_int = FIELD_GET(VCNL4040_ALS_CONF_INT_EN, val); + ret = i2c_smbus_write_word_data(data->client, VCNL4200_AL_CONF, + val); + break; + case IIO_PROXIMITY: + ret = i2c_smbus_read_word_data(data->client, VCNL4200_PS_CONF1); + if (ret < 0) + goto out; - data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, val); - ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, val); + if (dir == IIO_EV_DIR_RISING) + mask = VCNL4040_PS_IF_AWAY; + else + mask = VCNL4040_PS_IF_CLOSE; + + val = state ? (ret | mask) : (ret & ~mask); + + data->ps_int = FIELD_GET(VCNL4040_PS_CONF2_PS_INT, val); + ret = i2c_smbus_write_word_data(data->client, VCNL4200_PS_CONF1, + val); + break; + default: + break; + } out: mutex_unlock(&data->vcnl4000_lock); - data->chip_spec->set_power_state(data, data->ps_int != 0); + data->chip_spec->set_power_state(data, data->ps_int || data->als_int); return ret; } @@ -1005,7 +1524,7 @@ static irqreturn_t vcnl4040_irq_thread(int irq, void *p) struct vcnl4000_data *data = iio_priv(indio_dev); int ret; - ret = i2c_smbus_read_word_data(data->client, VCNL4040_INT_FLAGS); + ret = i2c_smbus_read_word_data(data->client, data->chip_spec->int_reg); if (ret < 0) return IRQ_HANDLED; @@ -1025,6 +1544,22 @@ static irqreturn_t vcnl4040_irq_thread(int irq, void *p) iio_get_time_ns(indio_dev)); } + if (ret & VCNL4040_ALS_FALLING) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_FALLING), + iio_get_time_ns(indio_dev)); + } + + if (ret & VCNL4040_ALS_RISING) { + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0, + IIO_EV_TYPE_THRESH, + IIO_EV_DIR_RISING), + iio_get_time_ns(indio_dev)); + } + return IRQ_HANDLED; } @@ -1191,6 +1726,22 @@ static const struct iio_event_spec vcnl4000_event_spec[] = { } }; +static const struct iio_event_spec vcnl4040_als_event_spec[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_PERIOD), + }, +}; + static const struct iio_event_spec vcnl4040_event_spec[] = { { .type = IIO_EV_TYPE_THRESH, @@ -1200,6 +1751,10 @@ static const struct iio_event_spec vcnl4040_event_spec[] = { .type = IIO_EV_TYPE_THRESH, .dir = IIO_EV_DIR_FALLING, .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE), + }, { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_separate = BIT(IIO_EV_INFO_PERIOD), }, }; @@ -1244,12 +1799,20 @@ static const struct iio_chan_spec vcnl4040_channels[] = { { .type = IIO_LIGHT, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE), + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_INT_TIME), + .info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME), + .event_spec = vcnl4040_als_event_spec, + .num_event_specs = ARRAY_SIZE(vcnl4040_als_event_spec), }, { .type = IIO_PROXIMITY, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_INT_TIME), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME), + BIT(IIO_CHAN_INFO_INT_TIME) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | + BIT(IIO_CHAN_INFO_CALIBBIAS), + .info_mask_separate_available = BIT(IIO_CHAN_INFO_INT_TIME) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | + BIT(IIO_CHAN_INFO_CALIBBIAS), .ext_info = vcnl4000_ext_info, .event_spec = vcnl4040_event_spec, .num_event_specs = ARRAY_SIZE(vcnl4040_event_spec), @@ -1314,6 +1877,12 @@ static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = { .num_channels = ARRAY_SIZE(vcnl4040_channels), .info = &vcnl4040_info, .irq_thread = vcnl4040_irq_thread, + .int_reg = VCNL4040_INT_FLAGS, + .ps_it_times = &vcnl4040_ps_it_times, + .num_ps_it_times = ARRAY_SIZE(vcnl4040_ps_it_times), + .als_it_times = &vcnl4040_als_it_times, + .num_als_it_times = ARRAY_SIZE(vcnl4040_als_it_times), + .ulux_step = 100000, }, [VCNL4200] = { .prod = "VCNL4200", @@ -1321,9 +1890,16 @@ static const struct vcnl4000_chip_spec vcnl4000_chip_spec_cfg[] = { .measure_light = vcnl4200_measure_light, .measure_proximity = vcnl4200_measure_proximity, .set_power_state = vcnl4200_set_power_state, - .channels = vcnl4000_channels, + .channels = vcnl4040_channels, .num_channels = ARRAY_SIZE(vcnl4000_channels), - .info = &vcnl4000_info, + .info = &vcnl4040_info, + .irq_thread = vcnl4040_irq_thread, + .int_reg = VCNL4200_INT_FLAGS, + .ps_it_times = &vcnl4200_ps_it_times, + .num_ps_it_times = ARRAY_SIZE(vcnl4200_ps_it_times), + .als_it_times = &vcnl4200_als_it_times, + .num_als_it_times = ARRAY_SIZE(vcnl4200_als_it_times), + .ulux_step = 24000, }, }; diff --git a/drivers/iio/potentiometer/mcp4018.c b/drivers/iio/potentiometer/mcp4018.c index 89daecc90305..44678d372126 100644 --- a/drivers/iio/potentiometer/mcp4018.c +++ b/drivers/iio/potentiometer/mcp4018.c @@ -99,20 +99,25 @@ static const struct iio_info mcp4018_info = { .write_raw = mcp4018_write_raw, }; +#define MCP4018_ID_TABLE(_name, cfg) { \ + .name = _name, \ + .driver_data = (kernel_ulong_t)&mcp4018_cfg[cfg], \ +} + static const struct i2c_device_id mcp4018_id[] = { - { "mcp4017-502", MCP4018_502 }, - { "mcp4017-103", MCP4018_103 }, - { "mcp4017-503", MCP4018_503 }, - { "mcp4017-104", MCP4018_104 }, - { "mcp4018-502", MCP4018_502 }, - { "mcp4018-103", MCP4018_103 }, - { "mcp4018-503", MCP4018_503 }, - { "mcp4018-104", MCP4018_104 }, - { "mcp4019-502", MCP4018_502 }, - { "mcp4019-103", MCP4018_103 }, - { "mcp4019-503", MCP4018_503 }, - { "mcp4019-104", MCP4018_104 }, - {} + MCP4018_ID_TABLE("mcp4017-502", MCP4018_502), + MCP4018_ID_TABLE("mcp4017-103", MCP4018_103), + MCP4018_ID_TABLE("mcp4017-503", MCP4018_503), + MCP4018_ID_TABLE("mcp4017-104", MCP4018_104), + MCP4018_ID_TABLE("mcp4018-502", MCP4018_502), + MCP4018_ID_TABLE("mcp4018-103", MCP4018_103), + MCP4018_ID_TABLE("mcp4018-503", MCP4018_503), + MCP4018_ID_TABLE("mcp4018-104", MCP4018_104), + MCP4018_ID_TABLE("mcp4019-502", MCP4018_502), + MCP4018_ID_TABLE("mcp4019-103", MCP4018_103), + MCP4018_ID_TABLE("mcp4019-503", MCP4018_503), + MCP4018_ID_TABLE("mcp4019-104", MCP4018_104), + { /* sentinel */ } }; MODULE_DEVICE_TABLE(i2c, mcp4018_id); @@ -157,9 +162,7 @@ static int mcp4018_probe(struct i2c_client *client) i2c_set_clientdata(client, indio_dev); data->client = client; - data->cfg = device_get_match_data(dev); - if (!data->cfg) - data->cfg = &mcp4018_cfg[i2c_match_id(mcp4018_id, client)->driver_data]; + data->cfg = i2c_get_match_data(client); indio_dev->info = &mcp4018_info; indio_dev->channels = &mcp4018_channel; diff --git a/drivers/iio/potentiometer/mcp4531.c b/drivers/iio/potentiometer/mcp4531.c index c513c00c8243..f28880ebd758 100644 --- a/drivers/iio/potentiometer/mcp4531.c +++ b/drivers/iio/potentiometer/mcp4531.c @@ -206,72 +206,77 @@ static const struct iio_info mcp4531_info = { .write_raw = mcp4531_write_raw, }; +#define MCP4531_ID_TABLE(_name, cfg) { \ + .name = _name, \ + .driver_data = (kernel_ulong_t)&mcp4531_cfg[cfg], \ +} + static const struct i2c_device_id mcp4531_id[] = { - { "mcp4531-502", MCP453x_502 }, - { "mcp4531-103", MCP453x_103 }, - { "mcp4531-503", MCP453x_503 }, - { "mcp4531-104", MCP453x_104 }, - { "mcp4532-502", MCP453x_502 }, - { "mcp4532-103", MCP453x_103 }, - { "mcp4532-503", MCP453x_503 }, - { "mcp4532-104", MCP453x_104 }, - { "mcp4541-502", MCP454x_502 }, - { "mcp4541-103", MCP454x_103 }, - { "mcp4541-503", MCP454x_503 }, - { "mcp4541-104", MCP454x_104 }, - { "mcp4542-502", MCP454x_502 }, - { "mcp4542-103", MCP454x_103 }, - { "mcp4542-503", MCP454x_503 }, - { "mcp4542-104", MCP454x_104 }, - { "mcp4551-502", MCP455x_502 }, - { "mcp4551-103", MCP455x_103 }, - { "mcp4551-503", MCP455x_503 }, - { "mcp4551-104", MCP455x_104 }, - { "mcp4552-502", MCP455x_502 }, - { "mcp4552-103", MCP455x_103 }, - { "mcp4552-503", MCP455x_503 }, - { "mcp4552-104", MCP455x_104 }, - { "mcp4561-502", MCP456x_502 }, - { "mcp4561-103", MCP456x_103 }, - { "mcp4561-503", MCP456x_503 }, - { "mcp4561-104", MCP456x_104 }, - { "mcp4562-502", MCP456x_502 }, - { "mcp4562-103", MCP456x_103 }, - { "mcp4562-503", MCP456x_503 }, - { "mcp4562-104", MCP456x_104 }, - { "mcp4631-502", MCP463x_502 }, - { "mcp4631-103", MCP463x_103 }, - { "mcp4631-503", MCP463x_503 }, - { "mcp4631-104", MCP463x_104 }, - { "mcp4632-502", MCP463x_502 }, - { "mcp4632-103", MCP463x_103 }, - { "mcp4632-503", MCP463x_503 }, - { "mcp4632-104", MCP463x_104 }, - { "mcp4641-502", MCP464x_502 }, - { "mcp4641-103", MCP464x_103 }, - { "mcp4641-503", MCP464x_503 }, - { "mcp4641-104", MCP464x_104 }, - { "mcp4642-502", MCP464x_502 }, - { "mcp4642-103", MCP464x_103 }, - { "mcp4642-503", MCP464x_503 }, - { "mcp4642-104", MCP464x_104 }, - { "mcp4651-502", MCP465x_502 }, - { "mcp4651-103", MCP465x_103 }, - { "mcp4651-503", MCP465x_503 }, - { "mcp4651-104", MCP465x_104 }, - { "mcp4652-502", MCP465x_502 }, - { "mcp4652-103", MCP465x_103 }, - { "mcp4652-503", MCP465x_503 }, - { "mcp4652-104", MCP465x_104 }, - { "mcp4661-502", MCP466x_502 }, - { "mcp4661-103", MCP466x_103 }, - { "mcp4661-503", MCP466x_503 }, - { "mcp4661-104", MCP466x_104 }, - { "mcp4662-502", MCP466x_502 }, - { "mcp4662-103", MCP466x_103 }, - { "mcp4662-503", MCP466x_503 }, - { "mcp4662-104", MCP466x_104 }, - {} + MCP4531_ID_TABLE("mcp4531-502", MCP453x_502), + MCP4531_ID_TABLE("mcp4531-103", MCP453x_103), + MCP4531_ID_TABLE("mcp4531-503", MCP453x_503), + MCP4531_ID_TABLE("mcp4531-104", MCP453x_104), + MCP4531_ID_TABLE("mcp4532-502", MCP453x_502), + MCP4531_ID_TABLE("mcp4532-103", MCP453x_103), + MCP4531_ID_TABLE("mcp4532-503", MCP453x_503), + MCP4531_ID_TABLE("mcp4532-104", MCP453x_104), + MCP4531_ID_TABLE("mcp4541-502", MCP454x_502), + MCP4531_ID_TABLE("mcp4541-103", MCP454x_103), + MCP4531_ID_TABLE("mcp4541-503", MCP454x_503), + MCP4531_ID_TABLE("mcp4541-104", MCP454x_104), + MCP4531_ID_TABLE("mcp4542-502", MCP454x_502), + MCP4531_ID_TABLE("mcp4542-103", MCP454x_103), + MCP4531_ID_TABLE("mcp4542-503", MCP454x_503), + MCP4531_ID_TABLE("mcp4542-104", MCP454x_104), + MCP4531_ID_TABLE("mcp4551-502", MCP455x_502), + MCP4531_ID_TABLE("mcp4551-103", MCP455x_103), + MCP4531_ID_TABLE("mcp4551-503", MCP455x_503), + MCP4531_ID_TABLE("mcp4551-104", MCP455x_104), + MCP4531_ID_TABLE("mcp4552-502", MCP455x_502), + MCP4531_ID_TABLE("mcp4552-103", MCP455x_103), + MCP4531_ID_TABLE("mcp4552-503", MCP455x_503), + MCP4531_ID_TABLE("mcp4552-104", MCP455x_104), + MCP4531_ID_TABLE("mcp4561-502", MCP456x_502), + MCP4531_ID_TABLE("mcp4561-103", MCP456x_103), + MCP4531_ID_TABLE("mcp4561-503", MCP456x_503), + MCP4531_ID_TABLE("mcp4561-104", MCP456x_104), + MCP4531_ID_TABLE("mcp4562-502", MCP456x_502), + MCP4531_ID_TABLE("mcp4562-103", MCP456x_103), + MCP4531_ID_TABLE("mcp4562-503", MCP456x_503), + MCP4531_ID_TABLE("mcp4562-104", MCP456x_104), + MCP4531_ID_TABLE("mcp4631-502", MCP463x_502), + MCP4531_ID_TABLE("mcp4631-103", MCP463x_103), + MCP4531_ID_TABLE("mcp4631-503", MCP463x_503), + MCP4531_ID_TABLE("mcp4631-104", MCP463x_104), + MCP4531_ID_TABLE("mcp4632-502", MCP463x_502), + MCP4531_ID_TABLE("mcp4632-103", MCP463x_103), + MCP4531_ID_TABLE("mcp4632-503", MCP463x_503), + MCP4531_ID_TABLE("mcp4632-104", MCP463x_104), + MCP4531_ID_TABLE("mcp4641-502", MCP464x_502), + MCP4531_ID_TABLE("mcp4641-103", MCP464x_103), + MCP4531_ID_TABLE("mcp4641-503", MCP464x_503), + MCP4531_ID_TABLE("mcp4641-104", MCP464x_104), + MCP4531_ID_TABLE("mcp4642-502", MCP464x_502), + MCP4531_ID_TABLE("mcp4642-103", MCP464x_103), + MCP4531_ID_TABLE("mcp4642-503", MCP464x_503), + MCP4531_ID_TABLE("mcp4642-104", MCP464x_104), + MCP4531_ID_TABLE("mcp4651-502", MCP465x_502), + MCP4531_ID_TABLE("mcp4651-103", MCP465x_103), + MCP4531_ID_TABLE("mcp4651-503", MCP465x_503), + MCP4531_ID_TABLE("mcp4651-104", MCP465x_104), + MCP4531_ID_TABLE("mcp4652-502", MCP465x_502), + MCP4531_ID_TABLE("mcp4652-103", MCP465x_103), + MCP4531_ID_TABLE("mcp4652-503", MCP465x_503), + MCP4531_ID_TABLE("mcp4652-104", MCP465x_104), + MCP4531_ID_TABLE("mcp4661-502", MCP466x_502), + MCP4531_ID_TABLE("mcp4661-103", MCP466x_103), + MCP4531_ID_TABLE("mcp4661-503", MCP466x_503), + MCP4531_ID_TABLE("mcp4661-104", MCP466x_104), + MCP4531_ID_TABLE("mcp4662-502", MCP466x_502), + MCP4531_ID_TABLE("mcp4662-103", MCP466x_103), + MCP4531_ID_TABLE("mcp4662-503", MCP466x_503), + MCP4531_ID_TABLE("mcp4662-104", MCP466x_104), + { /* sentinel */ } }; MODULE_DEVICE_TABLE(i2c, mcp4531_id); @@ -368,9 +373,7 @@ static int mcp4531_probe(struct i2c_client *client) i2c_set_clientdata(client, indio_dev); data->client = client; - data->cfg = device_get_match_data(dev); - if (!data->cfg) - data->cfg = &mcp4531_cfg[i2c_match_id(mcp4531_id, client)->driver_data]; + data->cfg = i2c_get_match_data(client); indio_dev->info = &mcp4531_info; indio_dev->channels = mcp4531_channels; diff --git a/drivers/iio/proximity/Kconfig b/drivers/iio/proximity/Kconfig index 0e5c17530b8b..2ca3b0bc5eba 100644 --- a/drivers/iio/proximity/Kconfig +++ b/drivers/iio/proximity/Kconfig @@ -32,6 +32,18 @@ config CROS_EC_MKBP_PROXIMITY To compile this driver as a module, choose M here: the module will be called cros_ec_mkbp_proximity. +config IRSD200 + tristate "Murata IRS-D200 PIR sensor" + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + select REGMAP_I2C + depends on I2C + help + Say Y here to build a driver for the Murata IRS-D200 PIR sensor. + + To compile this driver as a module, choose M here: the module will be + called irsd200. + config ISL29501 tristate "Intersil ISL29501 Time Of Flight sensor" depends on I2C diff --git a/drivers/iio/proximity/Makefile b/drivers/iio/proximity/Makefile index cc838bb5408a..f36598380446 100644 --- a/drivers/iio/proximity/Makefile +++ b/drivers/iio/proximity/Makefile @@ -6,6 +6,7 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_AS3935) += as3935.o obj-$(CONFIG_CROS_EC_MKBP_PROXIMITY) += cros_ec_mkbp_proximity.o +obj-$(CONFIG_IRSD200) += irsd200.o obj-$(CONFIG_ISL29501) += isl29501.o obj-$(CONFIG_LIDAR_LITE_V2) += pulsedlight-lidar-lite-v2.o obj-$(CONFIG_MB1232) += mb1232.o diff --git a/drivers/iio/proximity/irsd200.c b/drivers/iio/proximity/irsd200.c new file mode 100644 index 000000000000..5bd791b46d98 --- /dev/null +++ b/drivers/iio/proximity/irsd200.c @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for Murata IRS-D200 PIR sensor. + * + * Copyright (C) 2023 Axis Communications AB + */ + +#include <asm/unaligned.h> +#include <linux/bitfield.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#include <linux/iio/buffer.h> +#include <linux/iio/events.h> +#include <linux/iio/iio.h> +#include <linux/iio/trigger.h> +#include <linux/iio/trigger_consumer.h> +#include <linux/iio/triggered_buffer.h> +#include <linux/iio/types.h> + +#define IRS_DRV_NAME "irsd200" + +/* Registers. */ +#define IRS_REG_OP 0x00 /* Operation mode. */ +#define IRS_REG_DATA_LO 0x02 /* Sensor data LSB. */ +#define IRS_REG_DATA_HI 0x03 /* Sensor data MSB. */ +#define IRS_REG_STATUS 0x04 /* Interrupt status. */ +#define IRS_REG_COUNT 0x05 /* Count of exceeding threshold. */ +#define IRS_REG_DATA_RATE 0x06 /* Output data rate. */ +#define IRS_REG_FILTER 0x07 /* High-pass and low-pass filter. */ +#define IRS_REG_INTR 0x09 /* Interrupt mode. */ +#define IRS_REG_NR_COUNT 0x0a /* Number of counts before interrupt. */ +#define IRS_REG_THR_HI 0x0b /* Upper threshold. */ +#define IRS_REG_THR_LO 0x0c /* Lower threshold. */ +#define IRS_REG_TIMER_LO 0x0d /* Timer setting LSB. */ +#define IRS_REG_TIMER_HI 0x0e /* Timer setting MSB. */ + +/* Interrupt status bits. */ +#define IRS_INTR_DATA 0 /* Data update. */ +#define IRS_INTR_TIMER 1 /* Timer expiration. */ +#define IRS_INTR_COUNT_THR_AND 2 /* Count "AND" threshold. */ +#define IRS_INTR_COUNT_THR_OR 3 /* Count "OR" threshold. */ + +/* Operation states. */ +#define IRS_OP_ACTIVE 0x00 +#define IRS_OP_SLEEP 0x01 + +/* + * Quantization scale value for threshold. Used for conversion from/to register + * value. + */ +#define IRS_THR_QUANT_SCALE 128 + +#define IRS_UPPER_COUNT(count) FIELD_GET(GENMASK(7, 4), count) +#define IRS_LOWER_COUNT(count) FIELD_GET(GENMASK(3, 0), count) + +/* Index corresponds to the value of IRS_REG_DATA_RATE register. */ +static const int irsd200_data_rates[] = { + 50, + 100, +}; + +/* Index corresponds to the (field) value of IRS_REG_FILTER register. */ +static const unsigned int irsd200_lp_filter_freq[] = { + 10, + 7, +}; + +/* + * Index corresponds to the (field) value of IRS_REG_FILTER register. Note that + * this represents a fractional value (e.g the first value corresponds to 3 / 10 + * = 0.3 Hz). + */ +static const unsigned int irsd200_hp_filter_freq[][2] = { + { 3, 10 }, + { 5, 10 }, +}; + +/* Register fields. */ +enum irsd200_regfield { + /* Data interrupt. */ + IRS_REGF_INTR_DATA, + /* Timer interrupt. */ + IRS_REGF_INTR_TIMER, + /* AND count threshold interrupt. */ + IRS_REGF_INTR_COUNT_THR_AND, + /* OR count threshold interrupt. */ + IRS_REGF_INTR_COUNT_THR_OR, + + /* Low-pass filter frequency. */ + IRS_REGF_LP_FILTER, + /* High-pass filter frequency. */ + IRS_REGF_HP_FILTER, + + /* Sentinel value. */ + IRS_REGF_MAX +}; + +static const struct reg_field irsd200_regfields[] = { + [IRS_REGF_INTR_DATA] = + REG_FIELD(IRS_REG_INTR, IRS_INTR_DATA, IRS_INTR_DATA), + [IRS_REGF_INTR_TIMER] = + REG_FIELD(IRS_REG_INTR, IRS_INTR_TIMER, IRS_INTR_TIMER), + [IRS_REGF_INTR_COUNT_THR_AND] = REG_FIELD( + IRS_REG_INTR, IRS_INTR_COUNT_THR_AND, IRS_INTR_COUNT_THR_AND), + [IRS_REGF_INTR_COUNT_THR_OR] = REG_FIELD( + IRS_REG_INTR, IRS_INTR_COUNT_THR_OR, IRS_INTR_COUNT_THR_OR), + + [IRS_REGF_LP_FILTER] = REG_FIELD(IRS_REG_FILTER, 1, 1), + [IRS_REGF_HP_FILTER] = REG_FIELD(IRS_REG_FILTER, 0, 0), +}; + +static const struct regmap_config irsd200_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = IRS_REG_TIMER_HI, +}; + +struct irsd200_data { + struct regmap *regmap; + struct regmap_field *regfields[IRS_REGF_MAX]; + struct device *dev; +}; + +static int irsd200_setup(struct irsd200_data *data) +{ + unsigned int val; + int ret; + + /* Disable all interrupt sources. */ + ret = regmap_write(data->regmap, IRS_REG_INTR, 0); + if (ret) { + dev_err(data->dev, "Could not set interrupt sources (%d)\n", + ret); + return ret; + } + + /* Set operation to active. */ + ret = regmap_write(data->regmap, IRS_REG_OP, IRS_OP_ACTIVE); + if (ret) { + dev_err(data->dev, "Could not set operation mode (%d)\n", ret); + return ret; + } + + /* Clear threshold count. */ + ret = regmap_read(data->regmap, IRS_REG_COUNT, &val); + if (ret) { + dev_err(data->dev, "Could not clear threshold count (%d)\n", + ret); + return ret; + } + + /* Clear status. */ + ret = regmap_write(data->regmap, IRS_REG_STATUS, 0x0f); + if (ret) { + dev_err(data->dev, "Could not clear status (%d)\n", ret); + return ret; + } + + return 0; +} + +static int irsd200_read_threshold(struct irsd200_data *data, + enum iio_event_direction dir, int *val) +{ + unsigned int regval; + unsigned int reg; + int scale; + int ret; + + /* Set quantization scale. */ + if (dir == IIO_EV_DIR_RISING) { + scale = IRS_THR_QUANT_SCALE; + reg = IRS_REG_THR_HI; + } else if (dir == IIO_EV_DIR_FALLING) { + scale = -IRS_THR_QUANT_SCALE; + reg = IRS_REG_THR_LO; + } else { + return -EINVAL; + } + + ret = regmap_read(data->regmap, reg, ®val); + if (ret) { + dev_err(data->dev, "Could not read threshold (%d)\n", ret); + return ret; + } + + *val = ((int)regval) * scale; + + return 0; +} + +static int irsd200_write_threshold(struct irsd200_data *data, + enum iio_event_direction dir, int val) +{ + unsigned int regval; + unsigned int reg; + int scale; + int ret; + + /* Set quantization scale. */ + if (dir == IIO_EV_DIR_RISING) { + if (val < 0) + return -ERANGE; + + scale = IRS_THR_QUANT_SCALE; + reg = IRS_REG_THR_HI; + } else if (dir == IIO_EV_DIR_FALLING) { + if (val > 0) + return -ERANGE; + + scale = -IRS_THR_QUANT_SCALE; + reg = IRS_REG_THR_LO; + } else { + return -EINVAL; + } + + regval = val / scale; + + if (regval >= BIT(8)) + return -ERANGE; + + ret = regmap_write(data->regmap, reg, regval); + if (ret) { + dev_err(data->dev, "Could not write threshold (%d)\n", ret); + return ret; + } + + return 0; +} + +static int irsd200_read_data(struct irsd200_data *data, s16 *val) +{ + __le16 buf; + int ret; + + ret = regmap_bulk_read(data->regmap, IRS_REG_DATA_LO, &buf, + sizeof(buf)); + if (ret) { + dev_err(data->dev, "Could not bulk read data (%d)\n", ret); + return ret; + } + + *val = le16_to_cpu(buf); + + return 0; +} + +static int irsd200_read_data_rate(struct irsd200_data *data, int *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(data->regmap, IRS_REG_DATA_RATE, ®val); + if (ret) { + dev_err(data->dev, "Could not read data rate (%d)\n", ret); + return ret; + } + + if (regval >= ARRAY_SIZE(irsd200_data_rates)) + return -ERANGE; + + *val = irsd200_data_rates[regval]; + + return 0; +} + +static int irsd200_write_data_rate(struct irsd200_data *data, int val) +{ + size_t idx; + int ret; + + for (idx = 0; idx < ARRAY_SIZE(irsd200_data_rates); ++idx) { + if (irsd200_data_rates[idx] == val) + break; + } + + if (idx == ARRAY_SIZE(irsd200_data_rates)) + return -ERANGE; + + ret = regmap_write(data->regmap, IRS_REG_DATA_RATE, idx); + if (ret) { + dev_err(data->dev, "Could not write data rate (%d)\n", ret); + return ret; + } + + /* + * Data sheet says the device needs 3 seconds of settling time. The + * device operates normally during this period though. This is more of a + * "guarantee" than trying to prevent other user space reads/writes. + */ + ssleep(3); + + return 0; +} + +static int irsd200_read_timer(struct irsd200_data *data, int *val, int *val2) +{ + __le16 buf; + int ret; + + ret = regmap_bulk_read(data->regmap, IRS_REG_TIMER_LO, &buf, + sizeof(buf)); + if (ret) { + dev_err(data->dev, "Could not bulk read timer (%d)\n", ret); + return ret; + } + + ret = irsd200_read_data_rate(data, val2); + if (ret) + return ret; + + *val = le16_to_cpu(buf); + + return 0; +} + +static int irsd200_write_timer(struct irsd200_data *data, int val, int val2) +{ + unsigned int regval; + int data_rate; + __le16 buf; + int ret; + + if (val < 0 || val2 < 0) + return -ERANGE; + + ret = irsd200_read_data_rate(data, &data_rate); + if (ret) + return ret; + + /* Quantize from seconds. */ + regval = val * data_rate + (val2 * data_rate) / 1000000; + + /* Value is 10 bits. */ + if (regval >= BIT(10)) + return -ERANGE; + + buf = cpu_to_le16((u16)regval); + + ret = regmap_bulk_write(data->regmap, IRS_REG_TIMER_LO, &buf, + sizeof(buf)); + if (ret) { + dev_err(data->dev, "Could not bulk write timer (%d)\n", ret); + return ret; + } + + return 0; +} + +static int irsd200_read_nr_count(struct irsd200_data *data, int *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(data->regmap, IRS_REG_NR_COUNT, ®val); + if (ret) { + dev_err(data->dev, "Could not read nr count (%d)\n", ret); + return ret; + } + + *val = regval; + + return 0; +} + +static int irsd200_write_nr_count(struct irsd200_data *data, int val) +{ + unsigned int regval; + int ret; + + /* A value of zero means that IRS_REG_STATUS is never set. */ + if (val <= 0 || val >= 8) + return -ERANGE; + + regval = val; + + if (regval >= 2) { + /* + * According to the data sheet, timer must be also set in this + * case (i.e. be non-zero). Check and enforce that. + */ + ret = irsd200_read_timer(data, &val, &val); + if (ret) + return ret; + + if (val == 0) { + dev_err(data->dev, + "Timer must be non-zero when nr count is %u\n", + regval); + return -EPERM; + } + } + + ret = regmap_write(data->regmap, IRS_REG_NR_COUNT, regval); + if (ret) { + dev_err(data->dev, "Could not write nr count (%d)\n", ret); + return ret; + } + + return 0; +} + +static int irsd200_read_lp_filter(struct irsd200_data *data, int *val) +{ + unsigned int regval; + int ret; + + ret = regmap_field_read(data->regfields[IRS_REGF_LP_FILTER], ®val); + if (ret) { + dev_err(data->dev, "Could not read lp filter frequency (%d)\n", + ret); + return ret; + } + + *val = irsd200_lp_filter_freq[regval]; + + return 0; +} + +static int irsd200_write_lp_filter(struct irsd200_data *data, int val) +{ + size_t idx; + int ret; + + for (idx = 0; idx < ARRAY_SIZE(irsd200_lp_filter_freq); ++idx) { + if (irsd200_lp_filter_freq[idx] == val) + break; + } + + if (idx == ARRAY_SIZE(irsd200_lp_filter_freq)) + return -ERANGE; + + ret = regmap_field_write(data->regfields[IRS_REGF_LP_FILTER], idx); + if (ret) { + dev_err(data->dev, "Could not write lp filter frequency (%d)\n", + ret); + return ret; + } + + return 0; +} + +static int irsd200_read_hp_filter(struct irsd200_data *data, int *val, + int *val2) +{ + unsigned int regval; + int ret; + + ret = regmap_field_read(data->regfields[IRS_REGF_HP_FILTER], ®val); + if (ret) { + dev_err(data->dev, "Could not read hp filter frequency (%d)\n", + ret); + return ret; + } + + *val = irsd200_hp_filter_freq[regval][0]; + *val2 = irsd200_hp_filter_freq[regval][1]; + + return 0; +} + +static int irsd200_write_hp_filter(struct irsd200_data *data, int val, int val2) +{ + size_t idx; + int ret; + + /* Truncate fractional part to one digit. */ + val2 /= 100000; + + for (idx = 0; idx < ARRAY_SIZE(irsd200_hp_filter_freq); ++idx) { + if (irsd200_hp_filter_freq[idx][0] == val2) + break; + } + + if (idx == ARRAY_SIZE(irsd200_hp_filter_freq) || val != 0) + return -ERANGE; + + ret = regmap_field_write(data->regfields[IRS_REGF_HP_FILTER], idx); + if (ret) { + dev_err(data->dev, "Could not write hp filter frequency (%d)\n", + ret); + return ret; + } + + return 0; +} + +static int irsd200_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct irsd200_data *data = iio_priv(indio_dev); + int ret; + s16 buf; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = irsd200_read_data(data, &buf); + if (ret) + return ret; + + *val = buf; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + ret = irsd200_read_data_rate(data, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + ret = irsd200_read_lp_filter(data, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: + ret = irsd200_read_hp_filter(data, val, val2); + if (ret) + return ret; + + return IIO_VAL_FRACTIONAL; + default: + return -EINVAL; + } +} + +static int irsd200_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + *vals = irsd200_data_rates; + *type = IIO_VAL_INT; + *length = ARRAY_SIZE(irsd200_data_rates); + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + *vals = irsd200_lp_filter_freq; + *type = IIO_VAL_INT; + *length = ARRAY_SIZE(irsd200_lp_filter_freq); + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: + *vals = (int *)irsd200_hp_filter_freq; + *type = IIO_VAL_FRACTIONAL; + *length = 2 * ARRAY_SIZE(irsd200_hp_filter_freq); + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int irsd200_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long mask) +{ + struct irsd200_data *data = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + return irsd200_write_data_rate(data, val); + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + return irsd200_write_lp_filter(data, val); + case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: + return irsd200_write_hp_filter(data, val, val2); + default: + return -EINVAL; + } +} + +static int irsd200_read_event(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int *val, int *val2) +{ + struct irsd200_data *data = iio_priv(indio_dev); + int ret; + + switch (info) { + case IIO_EV_INFO_VALUE: + ret = irsd200_read_threshold(data, dir, val); + if (ret) + return ret; + + return IIO_VAL_INT; + case IIO_EV_INFO_RUNNING_PERIOD: + ret = irsd200_read_timer(data, val, val2); + if (ret) + return ret; + + return IIO_VAL_FRACTIONAL; + case IIO_EV_INFO_RUNNING_COUNT: + ret = irsd200_read_nr_count(data, val); + if (ret) + return ret; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int irsd200_write_event(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, + enum iio_event_info info, int val, int val2) +{ + struct irsd200_data *data = iio_priv(indio_dev); + + switch (info) { + case IIO_EV_INFO_VALUE: + return irsd200_write_threshold(data, dir, val); + case IIO_EV_INFO_RUNNING_PERIOD: + return irsd200_write_timer(data, val, val2); + case IIO_EV_INFO_RUNNING_COUNT: + return irsd200_write_nr_count(data, val); + default: + return -EINVAL; + } +} + +static int irsd200_read_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir) +{ + struct irsd200_data *data = iio_priv(indio_dev); + unsigned int val; + int ret; + + switch (type) { + case IIO_EV_TYPE_THRESH: + ret = regmap_field_read( + data->regfields[IRS_REGF_INTR_COUNT_THR_OR], &val); + if (ret) + return ret; + + return val; + default: + return -EINVAL; + } +} + +static int irsd200_write_event_config(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + enum iio_event_type type, + enum iio_event_direction dir, int state) +{ + struct irsd200_data *data = iio_priv(indio_dev); + unsigned int tmp; + int ret; + + switch (type) { + case IIO_EV_TYPE_THRESH: + /* Clear the count register (by reading from it). */ + ret = regmap_read(data->regmap, IRS_REG_COUNT, &tmp); + if (ret) + return ret; + + return regmap_field_write( + data->regfields[IRS_REGF_INTR_COUNT_THR_OR], !!state); + default: + return -EINVAL; + } +} + +static irqreturn_t irsd200_irq_thread(int irq, void *dev_id) +{ + struct iio_dev *indio_dev = dev_id; + struct irsd200_data *data = iio_priv(indio_dev); + enum iio_event_direction dir; + unsigned int lower_count; + unsigned int upper_count; + unsigned int status = 0; + unsigned int source = 0; + unsigned int clear = 0; + unsigned int count = 0; + int ret; + + ret = regmap_read(data->regmap, IRS_REG_INTR, &source); + if (ret) { + dev_err(data->dev, "Could not read interrupt source (%d)\n", + ret); + return IRQ_HANDLED; + } + + ret = regmap_read(data->regmap, IRS_REG_STATUS, &status); + if (ret) { + dev_err(data->dev, "Could not acknowledge interrupt (%d)\n", + ret); + return IRQ_HANDLED; + } + + if (status & BIT(IRS_INTR_DATA) && iio_buffer_enabled(indio_dev)) { + iio_trigger_poll_nested(indio_dev->trig); + clear |= BIT(IRS_INTR_DATA); + } + + if (status & BIT(IRS_INTR_COUNT_THR_OR) && + source & BIT(IRS_INTR_COUNT_THR_OR)) { + /* + * The register value resets to zero after reading. We therefore + * need to read once and manually extract the lower and upper + * count register fields. + */ + ret = regmap_read(data->regmap, IRS_REG_COUNT, &count); + if (ret) + dev_err(data->dev, "Could not read count (%d)\n", ret); + + upper_count = IRS_UPPER_COUNT(count); + lower_count = IRS_LOWER_COUNT(count); + + /* + * We only check the OR mode to be able to push events for + * rising and falling thresholds. AND mode is covered when both + * upper and lower count is non-zero, and is signaled with + * IIO_EV_DIR_EITHER. + */ + if (upper_count && !lower_count) + dir = IIO_EV_DIR_RISING; + else if (!upper_count && lower_count) + dir = IIO_EV_DIR_FALLING; + else + dir = IIO_EV_DIR_EITHER; + + iio_push_event(indio_dev, + IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0, + IIO_EV_TYPE_THRESH, dir), + iio_get_time_ns(indio_dev)); + + /* + * The OR mode will always trigger when the AND mode does, but + * not vice versa. However, it seems like the AND bit needs to + * be cleared if data capture _and_ threshold count interrupts + * are desirable, even though it hasn't explicitly been selected + * (with IRS_REG_INTR). Either way, it doesn't hurt... + */ + clear |= BIT(IRS_INTR_COUNT_THR_OR) | + BIT(IRS_INTR_COUNT_THR_AND); + } + + if (!clear) + return IRQ_NONE; + + ret = regmap_write(data->regmap, IRS_REG_STATUS, clear); + if (ret) + dev_err(data->dev, + "Could not clear interrupt status (%d)\n", ret); + + return IRQ_HANDLED; +} + +static irqreturn_t irsd200_trigger_handler(int irq, void *pollf) +{ + struct iio_dev *indio_dev = ((struct iio_poll_func *)pollf)->indio_dev; + struct irsd200_data *data = iio_priv(indio_dev); + s16 buf = 0; + int ret; + + ret = irsd200_read_data(data, &buf); + if (ret) + goto end; + + iio_push_to_buffers_with_timestamp(indio_dev, &buf, + iio_get_time_ns(indio_dev)); + +end: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int irsd200_set_trigger_state(struct iio_trigger *trig, bool state) +{ + struct irsd200_data *data = iio_trigger_get_drvdata(trig); + int ret; + + ret = regmap_field_write(data->regfields[IRS_REGF_INTR_DATA], state); + if (ret) { + dev_err(data->dev, "Could not %s data interrupt source (%d)\n", + state ? "enable" : "disable", ret); + } + + return ret; +} + +static const struct iio_info irsd200_info = { + .read_raw = irsd200_read_raw, + .read_avail = irsd200_read_avail, + .write_raw = irsd200_write_raw, + .read_event_value = irsd200_read_event, + .write_event_value = irsd200_write_event, + .read_event_config = irsd200_read_event_config, + .write_event_config = irsd200_write_event_config, +}; + +static const struct iio_trigger_ops irsd200_trigger_ops = { + .set_trigger_state = irsd200_set_trigger_state, + .validate_device = iio_trigger_validate_own_device, +}; + +static const struct iio_event_spec irsd200_event_spec[] = { + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_RISING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_FALLING, + .mask_separate = BIT(IIO_EV_INFO_VALUE), + }, + { + .type = IIO_EV_TYPE_THRESH, + .dir = IIO_EV_DIR_EITHER, + .mask_separate = + BIT(IIO_EV_INFO_RUNNING_PERIOD) | + BIT(IIO_EV_INFO_RUNNING_COUNT) | + BIT(IIO_EV_INFO_ENABLE), + }, +}; + +static const struct iio_chan_spec irsd200_channels[] = { + { + .type = IIO_PROXIMITY, + .info_mask_separate = + BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | + BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), + .info_mask_separate_available = + BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | + BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), + .event_spec = irsd200_event_spec, + .num_event_specs = ARRAY_SIZE(irsd200_event_spec), + .scan_type = { + .sign = 's', + .realbits = 16, + .storagebits = 16, + .endianness = IIO_CPU, + }, + }, +}; + +static int irsd200_probe(struct i2c_client *client) +{ + struct iio_trigger *trigger; + struct irsd200_data *data; + struct iio_dev *indio_dev; + size_t i; + int ret; + + indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!indio_dev) + return dev_err_probe(&client->dev, -ENOMEM, + "Could not allocate iio device\n"); + + data = iio_priv(indio_dev); + data->dev = &client->dev; + + data->regmap = devm_regmap_init_i2c(client, &irsd200_regmap_config); + if (IS_ERR(data->regmap)) + return dev_err_probe(data->dev, PTR_ERR(data->regmap), + "Could not initialize regmap\n"); + + for (i = 0; i < IRS_REGF_MAX; ++i) { + data->regfields[i] = devm_regmap_field_alloc( + data->dev, data->regmap, irsd200_regfields[i]); + if (IS_ERR(data->regfields[i])) + return dev_err_probe( + data->dev, PTR_ERR(data->regfields[i]), + "Could not allocate register field %zu\n", i); + } + + ret = devm_regulator_get_enable(data->dev, "vdd"); + if (ret) + return dev_err_probe( + data->dev, ret, + "Could not get and enable regulator (%d)\n", ret); + + ret = irsd200_setup(data); + if (ret) + return ret; + + indio_dev->info = &irsd200_info; + indio_dev->name = IRS_DRV_NAME; + indio_dev->channels = irsd200_channels; + indio_dev->num_channels = ARRAY_SIZE(irsd200_channels); + indio_dev->modes = INDIO_DIRECT_MODE; + + if (!client->irq) + return dev_err_probe(data->dev, -ENXIO, "No irq available\n"); + + ret = devm_iio_triggered_buffer_setup(data->dev, indio_dev, NULL, + irsd200_trigger_handler, NULL); + if (ret) + return dev_err_probe( + data->dev, ret, + "Could not setup iio triggered buffer (%d)\n", ret); + + ret = devm_request_threaded_irq(data->dev, client->irq, NULL, + irsd200_irq_thread, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + NULL, indio_dev); + if (ret) + return dev_err_probe(data->dev, ret, + "Could not request irq (%d)\n", ret); + + trigger = devm_iio_trigger_alloc(data->dev, "%s-dev%d", indio_dev->name, + iio_device_id(indio_dev)); + if (!trigger) + return dev_err_probe(data->dev, -ENOMEM, + "Could not allocate iio trigger\n"); + + trigger->ops = &irsd200_trigger_ops; + iio_trigger_set_drvdata(trigger, data); + + ret = devm_iio_trigger_register(data->dev, trigger); + if (ret) + return dev_err_probe(data->dev, ret, + "Could not register iio trigger (%d)\n", + ret); + + ret = devm_iio_device_register(data->dev, indio_dev); + if (ret) + return dev_err_probe(data->dev, ret, + "Could not register iio device (%d)\n", + ret); + + return 0; +} + +static const struct of_device_id irsd200_of_match[] = { + { + .compatible = "murata,irsd200", + }, + {} +}; +MODULE_DEVICE_TABLE(of, irsd200_of_match); + +static struct i2c_driver irsd200_driver = { + .driver = { + .name = IRS_DRV_NAME, + .of_match_table = irsd200_of_match, + }, + .probe = irsd200_probe, +}; +module_i2c_driver(irsd200_driver); + +MODULE_AUTHOR("Waqar Hameed <waqar.hameed@axis.com>"); +MODULE_DESCRIPTION("Murata IRS-D200 PIR sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/proximity/isl29501.c b/drivers/iio/proximity/isl29501.c index fe45ca35a124..bcebacaf3dab 100644 --- a/drivers/iio/proximity/isl29501.c +++ b/drivers/iio/proximity/isl29501.c @@ -12,7 +12,7 @@ #include <linux/module.h> #include <linux/i2c.h> #include <linux/err.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> diff --git a/drivers/iio/proximity/mb1232.c b/drivers/iio/proximity/mb1232.c index fb1073c8d9f7..614e65cb9d42 100644 --- a/drivers/iio/proximity/mb1232.c +++ b/drivers/iio/proximity/mb1232.c @@ -76,7 +76,7 @@ static s16 mb1232_read_distance(struct mb1232_data *data) goto error_unlock; } - if (data->irqnr >= 0) { + if (data->irqnr > 0) { /* it cannot take more than 100 ms */ ret = wait_for_completion_killable_timeout(&data->ranging, HZ/10); @@ -212,10 +212,7 @@ static int mb1232_probe(struct i2c_client *client) init_completion(&data->ranging); data->irqnr = fwnode_irq_get(dev_fwnode(&client->dev), 0); - if (data->irqnr <= 0) { - /* usage of interrupt is optional */ - data->irqnr = -1; - } else { + if (data->irqnr > 0) { ret = devm_request_irq(dev, data->irqnr, mb1232_handle_irq, IRQF_TRIGGER_FALLING, id->name, indio_dev); if (ret < 0) { diff --git a/drivers/iio/temperature/mlx90614.c b/drivers/iio/temperature/mlx90614.c index 676dc8701924..07bb5df24ab3 100644 --- a/drivers/iio/temperature/mlx90614.c +++ b/drivers/iio/temperature/mlx90614.c @@ -27,8 +27,8 @@ #include <linux/gpio/consumer.h> #include <linux/i2c.h> #include <linux/jiffies.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> #include <linux/pm_runtime.h> #include <linux/iio/iio.h> diff --git a/drivers/iio/trigger/stm32-lptimer-trigger.c b/drivers/iio/trigger/stm32-lptimer-trigger.c index 2e447a3f047d..f1e18913236a 100644 --- a/drivers/iio/trigger/stm32-lptimer-trigger.c +++ b/drivers/iio/trigger/stm32-lptimer-trigger.c @@ -73,7 +73,6 @@ static int stm32_lptim_trigger_probe(struct platform_device *pdev) { struct stm32_lptim_trigger *priv; u32 index; - int ret; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -88,13 +87,7 @@ static int stm32_lptim_trigger_probe(struct platform_device *pdev) priv->dev = &pdev->dev; priv->trg = stm32_lptim_triggers[index]; - ret = stm32_lptim_setup_trig(priv); - if (ret) - return ret; - - platform_set_drvdata(pdev, priv); - - return 0; + return stm32_lptim_setup_trig(priv); } static const struct of_device_id stm32_lptim_trig_of_match[] = { diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index 5604ce351a9f..d0888babb9a1 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 CFLAGS_core.o := -I$(src) -icc-core-objs := core.o bulk.o +icc-core-objs := core.o bulk.o debugfs-client.o obj-$(CONFIG_INTERCONNECT) += icc-core.o obj-$(CONFIG_INTERCONNECT_IMX) += imx/ diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index 5fac448c28fd..dfab160ca529 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -28,6 +28,7 @@ static LIST_HEAD(icc_providers); static int providers_count; static bool synced_state; static DEFINE_MUTEX(icc_lock); +static DEFINE_MUTEX(icc_bw_lock); static struct dentry *icc_debugfs_dir; static void icc_summary_show_one(struct seq_file *s, struct icc_node *n) @@ -147,6 +148,21 @@ static struct icc_node *node_find(const int id) return idr_find(&icc_idr, id); } +static struct icc_node *node_find_by_name(const char *name) +{ + struct icc_provider *provider; + struct icc_node *n; + + list_for_each_entry(provider, &icc_providers, provider_list) { + list_for_each_entry(n, &provider->nodes, node_list) { + if (!strcmp(n->name, name)) + return n; + } + } + + return NULL; +} + static struct icc_path *path_init(struct device *dev, struct icc_node *dst, ssize_t num_nodes) { @@ -562,6 +578,54 @@ struct icc_path *of_icc_get(struct device *dev, const char *name) EXPORT_SYMBOL_GPL(of_icc_get); /** + * icc_get() - get a path handle between two endpoints + * @dev: device pointer for the consumer device + * @src: source node name + * @dst: destination node name + * + * This function will search for a path between two endpoints and return an + * icc_path handle on success. Use icc_put() to release constraints when they + * are not needed anymore. + * + * Return: icc_path pointer on success or ERR_PTR() on error. NULL is returned + * when the API is disabled. + */ +struct icc_path *icc_get(struct device *dev, const char *src, const char *dst) +{ + struct icc_node *src_node, *dst_node; + struct icc_path *path = ERR_PTR(-EPROBE_DEFER); + + mutex_lock(&icc_lock); + + src_node = node_find_by_name(src); + if (!src_node) { + dev_err(dev, "%s: invalid src=%s\n", __func__, src); + goto out; + } + + dst_node = node_find_by_name(dst); + if (!dst_node) { + dev_err(dev, "%s: invalid dst=%s\n", __func__, dst); + goto out; + } + + path = path_find(dev, src_node, dst_node); + if (IS_ERR(path)) { + dev_err(dev, "%s: invalid path=%ld\n", __func__, PTR_ERR(path)); + goto out; + } + + path->name = kasprintf(GFP_KERNEL, "%s-%s", src_node->name, dst_node->name); + if (!path->name) { + kfree(path); + path = ERR_PTR(-ENOMEM); + } +out: + mutex_unlock(&icc_lock); + return path; +} + +/** * icc_set_tag() - set an optional tag on a path * @path: the path we want to tag * @tag: the tag value @@ -631,7 +695,7 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) if (WARN_ON(IS_ERR(path) || !path->num_nodes)) return -EINVAL; - mutex_lock(&icc_lock); + mutex_lock(&icc_bw_lock); old_avg = path->reqs[0].avg_bw; old_peak = path->reqs[0].peak_bw; @@ -663,7 +727,7 @@ int icc_set_bw(struct icc_path *path, u32 avg_bw, u32 peak_bw) apply_constraints(path); } - mutex_unlock(&icc_lock); + mutex_unlock(&icc_bw_lock); trace_icc_set_bw_end(path, ret); @@ -872,6 +936,7 @@ void icc_node_add(struct icc_node *node, struct icc_provider *provider) return; mutex_lock(&icc_lock); + mutex_lock(&icc_bw_lock); node->provider = provider; list_add_tail(&node->node_list, &provider->nodes); @@ -900,6 +965,7 @@ void icc_node_add(struct icc_node *node, struct icc_provider *provider) node->avg_bw = 0; node->peak_bw = 0; + mutex_unlock(&icc_bw_lock); mutex_unlock(&icc_lock); } EXPORT_SYMBOL_GPL(icc_node_add); @@ -1025,6 +1091,7 @@ void icc_sync_state(struct device *dev) return; mutex_lock(&icc_lock); + mutex_lock(&icc_bw_lock); synced_state = true; list_for_each_entry(p, &icc_providers, provider_list) { dev_dbg(p->dev, "interconnect provider is in synced state\n"); @@ -1037,13 +1104,21 @@ void icc_sync_state(struct device *dev) } } } + mutex_unlock(&icc_bw_lock); mutex_unlock(&icc_lock); } EXPORT_SYMBOL_GPL(icc_sync_state); static int __init icc_init(void) { - struct device_node *root = of_find_node_by_path("/"); + struct device_node *root; + + /* Teach lockdep about lock ordering wrt. shrinker: */ + fs_reclaim_acquire(GFP_KERNEL); + might_lock(&icc_bw_lock); + fs_reclaim_release(GFP_KERNEL); + + root = of_find_node_by_path("/"); providers_count = of_count_icc_providers(root); of_node_put(root); @@ -1053,6 +1128,9 @@ static int __init icc_init(void) icc_debugfs_dir, NULL, &icc_summary_fops); debugfs_create_file("interconnect_graph", 0444, icc_debugfs_dir, NULL, &icc_graph_fops); + + icc_debugfs_client_init(icc_debugfs_dir); + return 0; } diff --git a/drivers/interconnect/debugfs-client.c b/drivers/interconnect/debugfs-client.c new file mode 100644 index 000000000000..bc3fd8a7b9eb --- /dev/null +++ b/drivers/interconnect/debugfs-client.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include <linux/debugfs.h> +#include <linux/interconnect.h> +#include <linux/platform_device.h> + +#include "internal.h" + +/* + * This can be dangerous, therefore don't provide any real compile time + * configuration option for this feature. + * People who want to use this will need to modify the source code directly. + */ +#undef INTERCONNECT_ALLOW_WRITE_DEBUGFS + +#if defined(INTERCONNECT_ALLOW_WRITE_DEBUGFS) && defined(CONFIG_DEBUG_FS) + +static LIST_HEAD(debugfs_paths); +static DEFINE_MUTEX(debugfs_lock); + +static struct platform_device *pdev; +static struct icc_path *cur_path; + +static char *src_node; +static char *dst_node; +static u32 avg_bw; +static u32 peak_bw; +static u32 tag; + +struct debugfs_path { + const char *src; + const char *dst; + struct icc_path *path; + struct list_head list; +}; + +static struct icc_path *get_path(const char *src, const char *dst) +{ + struct debugfs_path *path; + + list_for_each_entry(path, &debugfs_paths, list) { + if (!strcmp(path->src, src) && !strcmp(path->dst, dst)) + return path->path; + } + + return NULL; +} + +static int icc_get_set(void *data, u64 val) +{ + struct debugfs_path *debugfs_path; + char *src, *dst; + int ret = 0; + + mutex_lock(&debugfs_lock); + + rcu_read_lock(); + src = rcu_dereference(src_node); + dst = rcu_dereference(dst_node); + + /* + * If we've already looked up a path, then use the existing one instead + * of calling icc_get() again. This allows for updating previous BW + * votes when "get" is written to multiple times for multiple paths. + */ + cur_path = get_path(src, dst); + if (cur_path) { + rcu_read_unlock(); + goto out; + } + + src = kstrdup(src, GFP_ATOMIC); + dst = kstrdup(dst, GFP_ATOMIC); + rcu_read_unlock(); + + if (!src || !dst) { + ret = -ENOMEM; + goto err_free; + } + + cur_path = icc_get(&pdev->dev, src, dst); + if (IS_ERR(cur_path)) { + ret = PTR_ERR(cur_path); + goto err_free; + } + + debugfs_path = kzalloc(sizeof(*debugfs_path), GFP_KERNEL); + if (!debugfs_path) { + ret = -ENOMEM; + goto err_put; + } + + debugfs_path->path = cur_path; + debugfs_path->src = src; + debugfs_path->dst = dst; + list_add_tail(&debugfs_path->list, &debugfs_paths); + + goto out; + +err_put: + icc_put(cur_path); +err_free: + kfree(src); + kfree(dst); +out: + mutex_unlock(&debugfs_lock); + return ret; +} + +DEFINE_DEBUGFS_ATTRIBUTE(icc_get_fops, NULL, icc_get_set, "%llu\n"); + +static int icc_commit_set(void *data, u64 val) +{ + int ret; + + mutex_lock(&debugfs_lock); + + if (IS_ERR_OR_NULL(cur_path)) { + ret = PTR_ERR(cur_path); + goto out; + } + + icc_set_tag(cur_path, tag); + ret = icc_set_bw(cur_path, avg_bw, peak_bw); +out: + mutex_unlock(&debugfs_lock); + return ret; +} + +DEFINE_DEBUGFS_ATTRIBUTE(icc_commit_fops, NULL, icc_commit_set, "%llu\n"); + +int icc_debugfs_client_init(struct dentry *icc_dir) +{ + struct dentry *client_dir; + int ret; + + pdev = platform_device_alloc("icc-debugfs-client", PLATFORM_DEVID_NONE); + + ret = platform_device_add(pdev); + if (ret) { + pr_err("%s: failed to add platform device: %d\n", __func__, ret); + platform_device_put(pdev); + return ret; + } + + client_dir = debugfs_create_dir("test_client", icc_dir); + + debugfs_create_str("src_node", 0600, client_dir, &src_node); + debugfs_create_str("dst_node", 0600, client_dir, &dst_node); + debugfs_create_file("get", 0200, client_dir, NULL, &icc_get_fops); + debugfs_create_u32("avg_bw", 0600, client_dir, &avg_bw); + debugfs_create_u32("peak_bw", 0600, client_dir, &peak_bw); + debugfs_create_u32("tag", 0600, client_dir, &tag); + debugfs_create_file("commit", 0200, client_dir, NULL, &icc_commit_fops); + + return 0; +} + +#else + +int icc_debugfs_client_init(struct dentry *icc_dir) +{ + return 0; +} + +#endif diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c index 4d43ebff4257..d787f2ea36d9 100644 --- a/drivers/interconnect/icc-clk.c +++ b/drivers/interconnect/icc-clk.c @@ -16,7 +16,7 @@ struct icc_clk_node { struct icc_clk_provider { struct icc_provider provider; int num_clocks; - struct icc_clk_node clocks[]; + struct icc_clk_node clocks[] __counted_by(num_clocks); }; #define to_icc_clk_provider(_provider) \ diff --git a/drivers/interconnect/imx/imx8mp.c b/drivers/interconnect/imx/imx8mp.c index 8bfaf173f1da..a66ae3638b18 100644 --- a/drivers/interconnect/imx/imx8mp.c +++ b/drivers/interconnect/imx/imx8mp.c @@ -7,7 +7,6 @@ */ #include <linux/module.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <dt-bindings/interconnect/fsl,imx8mp.h> diff --git a/drivers/interconnect/internal.h b/drivers/interconnect/internal.h index f5f82a5c939e..3b9d50589c01 100644 --- a/drivers/interconnect/internal.h +++ b/drivers/interconnect/internal.h @@ -38,7 +38,10 @@ struct icc_req { struct icc_path { const char *name; size_t num_nodes; - struct icc_req reqs[]; + struct icc_req reqs[] __counted_by(num_nodes); }; +struct icc_path *icc_get(struct device *dev, const char *src, const char *dst); +int icc_debugfs_client_init(struct dentry *icc_dir); + #endif diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c index d5f2a6b5376b..a2d437a05a11 100644 --- a/drivers/interconnect/qcom/bcm-voter.c +++ b/drivers/interconnect/qcom/bcm-voter.c @@ -58,6 +58,36 @@ static u64 bcm_div(u64 num, u32 base) return num; } +/* BCMs with enable_mask use one-hot-encoding for on/off signaling */ +static void bcm_aggregate_mask(struct qcom_icc_bcm *bcm) +{ + struct qcom_icc_node *node; + int bucket, i; + + for (bucket = 0; bucket < QCOM_ICC_NUM_BUCKETS; bucket++) { + bcm->vote_x[bucket] = 0; + bcm->vote_y[bucket] = 0; + + for (i = 0; i < bcm->num_nodes; i++) { + node = bcm->nodes[i]; + + /* If any vote in this bucket exists, keep the BCM enabled */ + if (node->sum_avg[bucket] || node->max_peak[bucket]) { + bcm->vote_x[bucket] = 0; + bcm->vote_y[bucket] = bcm->enable_mask; + break; + } + } + } + + if (bcm->keepalive) { + bcm->vote_x[QCOM_ICC_BUCKET_AMC] = bcm->enable_mask; + bcm->vote_x[QCOM_ICC_BUCKET_WAKE] = bcm->enable_mask; + bcm->vote_y[QCOM_ICC_BUCKET_AMC] = bcm->enable_mask; + bcm->vote_y[QCOM_ICC_BUCKET_WAKE] = bcm->enable_mask; + } +} + static void bcm_aggregate(struct qcom_icc_bcm *bcm) { struct qcom_icc_node *node; @@ -83,11 +113,6 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm) temp = agg_peak[bucket] * bcm->vote_scale; bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit); - - if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) { - bcm->vote_x[bucket] = 0; - bcm->vote_y[bucket] = bcm->enable_mask; - } } if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 && @@ -260,8 +285,12 @@ int qcom_icc_bcm_voter_commit(struct bcm_voter *voter) return 0; mutex_lock(&voter->lock); - list_for_each_entry(bcm, &voter->commit_list, list) - bcm_aggregate(bcm); + list_for_each_entry(bcm, &voter->commit_list, list) { + if (bcm->enable_mask) + bcm_aggregate_mask(bcm); + else + bcm_aggregate(bcm); + } /* * Pre sort the BCMs based on VCD for ease of generating a command list diff --git a/drivers/interconnect/qcom/bcm-voter.h b/drivers/interconnect/qcom/bcm-voter.h index 0f64c0bab2c0..b4d36e349f3c 100644 --- a/drivers/interconnect/qcom/bcm-voter.h +++ b/drivers/interconnect/qcom/bcm-voter.h @@ -12,14 +12,6 @@ #include "icc-rpmh.h" -#define DEFINE_QBCM(_name, _bcmname, _keepalive, ...) \ -static struct qcom_icc_bcm _name = { \ - .name = _bcmname, \ - .keepalive = _keepalive, \ - .num_nodes = ARRAY_SIZE(((struct qcom_icc_node *[]){ __VA_ARGS__ })), \ - .nodes = { __VA_ARGS__ }, \ -} - struct bcm_voter *of_bcm_voter_get(struct device *dev, const char *name); void qcom_icc_bcm_voter_add(struct bcm_voter *voter, struct qcom_icc_bcm *bcm); int qcom_icc_bcm_voter_commit(struct bcm_voter *voter); diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 3209d8de709b..2c16917ba1fd 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -7,7 +7,7 @@ #include <linux/interconnect-provider.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> @@ -240,7 +240,7 @@ static int qcom_icc_rpm_set(struct qcom_icc_node *qn, u64 *bw) } } - return ret; + return 0; } /** diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c index fdb5e58e408b..b9f27ce3b607 100644 --- a/drivers/interconnect/qcom/icc-rpmh.c +++ b/drivers/interconnect/qcom/icc-rpmh.c @@ -7,7 +7,7 @@ #include <linux/interconnect-provider.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> +#include <linux/of_platform.h> #include <linux/slab.h> #include "bcm-voter.h" @@ -185,6 +185,7 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), GFP_KERNEL); if (!data) return -ENOMEM; + data->num_nodes = num_nodes; provider = &qp->provider; provider->dev = dev; @@ -228,8 +229,6 @@ int qcom_icc_rpmh_probe(struct platform_device *pdev) data->nodes[i] = node; } - data->num_nodes = num_nodes; - ret = icc_provider_register(provider); if (ret) goto err_remove_nodes; diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h index 7843d8864d6b..5f0af8b1fc43 100644 --- a/drivers/interconnect/qcom/icc-rpmh.h +++ b/drivers/interconnect/qcom/icc-rpmh.h @@ -120,16 +120,6 @@ struct qcom_icc_desc { size_t num_bcms; }; -#define DEFINE_QNODE(_name, _id, _channels, _buswidth, ...) \ - static struct qcom_icc_node _name = { \ - .id = _id, \ - .name = #_name, \ - .channels = _channels, \ - .buswidth = _buswidth, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ - .links = { __VA_ARGS__ }, \ - } - int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, u32 peak_bw, u32 *agg_avg, u32 *agg_peak); int qcom_icc_set(struct icc_node *src, struct icc_node *dst); diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index b567a2b4199c..35148880b3e8 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -8,9 +8,9 @@ #include <linux/interconnect-provider.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> -#include <linux/of_device.h> #include <dt-bindings/interconnect/qcom,msm8916.h> diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 6732eeeb8158..b52c5ac1175c 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -9,9 +9,9 @@ #include <linux/interconnect-provider.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/regmap.h> -#include <linux/of_device.h> #include <dt-bindings/interconnect/qcom,msm8939.h> diff --git a/drivers/interconnect/qcom/msm8974.c b/drivers/interconnect/qcom/msm8974.c index 968162213d40..885ca9d6d4ed 100644 --- a/drivers/interconnect/qcom/msm8974.c +++ b/drivers/interconnect/qcom/msm8974.c @@ -33,8 +33,7 @@ #include <linux/interconnect-provider.h> #include <linux/io.h> #include <linux/module.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -676,6 +675,7 @@ static int msm8974_icc_probe(struct platform_device *pdev) GFP_KERNEL); if (!data) return -ENOMEM; + data->num_nodes = num_nodes; qp->bus_clks = devm_kmemdup(dev, msm8974_icc_bus_clocks, sizeof(msm8974_icc_bus_clocks), GFP_KERNEL); @@ -722,7 +722,6 @@ static int msm8974_icc_probe(struct platform_device *pdev) data->nodes[i] = node; } - data->num_nodes = num_nodes; ret = icc_provider_register(provider); if (ret) diff --git a/drivers/interconnect/qcom/msm8996.c b/drivers/interconnect/qcom/msm8996.c index b9695c1931ce..88683dfa468f 100644 --- a/drivers/interconnect/qcom/msm8996.c +++ b/drivers/interconnect/qcom/msm8996.c @@ -8,9 +8,8 @@ #include <linux/device.h> #include <linux/interconnect-provider.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index a1f4f918b911..dc321bb86d0b 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -9,7 +9,7 @@ #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> @@ -232,6 +232,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes), GFP_KERNEL); if (!data) return -ENOMEM; + data->num_nodes = num_nodes; provider = &qp->provider; provider->dev = &pdev->dev; @@ -261,7 +262,6 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) data->nodes[i] = node; } - data->num_nodes = num_nodes; ret = icc_provider_register(provider); if (ret) diff --git a/drivers/interconnect/qcom/qcm2290.c b/drivers/interconnect/qcom/qcm2290.c index 8fc4acc4220b..5bc4b7516608 100644 --- a/drivers/interconnect/qcom/qcm2290.c +++ b/drivers/interconnect/qcom/qcm2290.c @@ -10,9 +10,8 @@ #include <linux/device.h> #include <linux/interconnect-provider.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> @@ -1197,6 +1196,7 @@ static const struct qcom_icc_desc qcm2290_bimc = { .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), .bus_clk_desc = &bimc_clk, .regmap_cfg = &qcm2290_bimc_regmap_config, + .keep_alive = true, /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ .qos_offset = 0x8000, }; @@ -1253,6 +1253,7 @@ static const struct qcom_icc_desc qcm2290_cnoc = { .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), .bus_clk_desc = &bus_1_clk, .regmap_cfg = &qcm2290_cnoc_regmap_config, + .keep_alive = true, }; static struct qcom_icc_node * const qcm2290_snoc_nodes[] = { @@ -1295,6 +1296,7 @@ static const struct qcom_icc_desc qcm2290_snoc = { .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), .bus_clk_desc = &bus_2_clk, .regmap_cfg = &qcm2290_snoc_regmap_config, + .keep_alive = true, /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */ .qos_offset = 0x15000, }; @@ -1309,6 +1311,7 @@ static const struct qcom_icc_desc qcm2290_qup_virt = { .nodes = qcm2290_qup_virt_nodes, .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), .bus_clk_desc = &qup_clk, + .keep_alive = true, }; static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { @@ -1324,6 +1327,7 @@ static const struct qcom_icc_desc qcm2290_mmnrt_virt = { .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), .bus_clk_desc = &mmaxi_0_clk, .regmap_cfg = &qcm2290_snoc_regmap_config, + .keep_alive = true, .qos_offset = 0x15000, }; @@ -1339,6 +1343,7 @@ static const struct qcom_icc_desc qcm2290_mmrt_virt = { .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), .bus_clk_desc = &mmaxi_1_clk, .regmap_cfg = &qcm2290_snoc_regmap_config, + .keep_alive = true, .qos_offset = 0x15000, }; @@ -1359,6 +1364,7 @@ static struct platform_driver qcm2290_noc_driver = { .driver = { .name = "qnoc-qcm2290", .of_match_table = qcm2290_noc_of_match, + .sync_state = icc_sync_state, }, }; module_platform_driver(qcm2290_noc_driver); diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 82fe905b74a9..9fa1da70c843 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -8,8 +8,8 @@ #include <linux/interconnect-provider.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> -#include <linux/of_device.h> #include "icc-rpm.h" diff --git a/drivers/interconnect/qcom/qdu1000.c b/drivers/interconnect/qcom/qdu1000.c index a4cf559de2b0..bf800dd7d4ba 100644 --- a/drivers/interconnect/qcom/qdu1000.c +++ b/drivers/interconnect/qcom/qdu1000.c @@ -7,8 +7,9 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> #include "bcm-voter.h" diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c index f56538669de0..ef1b5e326089 100644 --- a/drivers/interconnect/qcom/sa8775p.c +++ b/drivers/interconnect/qcom/sa8775p.c @@ -7,8 +7,9 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> #include "bcm-voter.h" diff --git a/drivers/interconnect/qcom/sc7180.c b/drivers/interconnect/qcom/sc7180.c index ef4e13fb4983..d94ab9b39f3d 100644 --- a/drivers/interconnect/qcom/sc7180.c +++ b/drivers/interconnect/qcom/sc7180.c @@ -7,176 +7,1466 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sc7180.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sc7180.h" -DEFINE_QNODE(qhm_a1noc_cfg, SC7180_MASTER_A1NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qspi, SC7180_MASTER_QSPI, 1, 4, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup_0, SC7180_MASTER_QUP_0, 1, 4, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SC7180_MASTER_SDCC_2, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_emmc, SC7180_MASTER_EMMC, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SC7180_MASTER_UFS_MEM, 1, 8, SC7180_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_a2noc_cfg, SC7180_MASTER_A2NOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SC7180_MASTER_QDSS_BAM, 1, 4, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup_1, SC7180_MASTER_QUP_1, 1, 4, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_crypto, SC7180_MASTER_CRYPTO, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SC7180_MASTER_IPA, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SC7180_MASTER_QDSS_ETR, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_usb3, SC7180_MASTER_USB3, 1, 8, SC7180_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SC7180_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SC7180_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SC7180_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC7180_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qnm_npu, SC7180_MASTER_NPU, 2, 32, SC7180_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qxm_npu_dsp, SC7180_MASTER_NPU_PROC, 1, 8, SC7180_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qnm_snoc, SC7180_MASTER_SNOC_CNOC, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, - SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(xm_qdss_dap, SC7180_MASTER_QDSS_DAP, 1, 8, SC7180_SLAVE_A1NOC_CFG, SC7180_SLAVE_A2NOC_CFG, SC7180_SLAVE_AHB2PHY_SOUTH, SC7180_SLAVE_AHB2PHY_CENTER, SC7180_SLAVE_AOP, SC7180_SLAVE_AOSS, SC7180_SLAVE_BOOT_ROM, SC7180_SLAVE_CAMERA_CFG, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, SC7180_SLAVE_CLK_CTL, SC7180_SLAVE_RBCPR_CX_CFG, SC7180_SLAVE_RBCPR_MX_CFG, SC7180_SLAVE_CRYPTO_0_CFG, SC7180_SLAVE_DCC_CFG, SC7180_SLAVE_CNOC_DDRSS, SC7180_SLAVE_DISPLAY_CFG, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, SC7180_SLAVE_EMMC_CFG, SC7180_SLAVE_GLM, SC7180_SLAVE_GFX3D_CFG, SC7180_SLAVE_IMEM_CFG, SC7180_SLAVE_IPA_CFG, SC7180_SLAVE_CNOC_MNOC_CFG, SC7180_SLAVE_CNOC_MSS, SC7180_SLAVE_NPU_CFG, SC7180_SLAVE_NPU_DMA_BWMON_CFG, -SC7180_SLAVE_NPU_PROC_BWMON_CFG, SC7180_SLAVE_PDM, SC7180_SLAVE_PIMEM_CFG, SC7180_SLAVE_PRNG, SC7180_SLAVE_QDSS_CFG, SC7180_SLAVE_QM_CFG, SC7180_SLAVE_QM_MPU_CFG, SC7180_SLAVE_QSPI_0, SC7180_SLAVE_QUP_0, SC7180_SLAVE_QUP_1, SC7180_SLAVE_SDCC_2, SC7180_SLAVE_SECURITY, SC7180_SLAVE_SNOC_CFG, SC7180_SLAVE_TCSR, SC7180_SLAVE_TLMM_WEST, SC7180_SLAVE_TLMM_NORTH, SC7180_SLAVE_TLMM_SOUTH, SC7180_SLAVE_UFS_MEM_CFG, SC7180_SLAVE_USB3, SC7180_SLAVE_VENUS_CFG, SC7180_SLAVE_VENUS_THROTTLE_CFG, SC7180_SLAVE_VSENSE_CTRL_CFG, SC7180_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qhm_cnoc_dc_noc, SC7180_MASTER_CNOC_DC_NOC, 1, 4, SC7180_SLAVE_GEM_NOC_CFG, SC7180_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_apps0, SC7180_MASTER_APPSS_PROC, 1, 16, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(acm_sys_tcu, SC7180_MASTER_SYS_TCU, 1, 8, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qhm_gemnoc_cfg, SC7180_MASTER_GEM_NOC_CFG, 1, 4, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, SC7180_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_cmpnoc, SC7180_MASTER_COMPUTE_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SC7180_MASTER_MNOC_HF_MEM_NOC, 1, 32, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SC7180_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_gc, SC7180_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SC7180_MASTER_SNOC_SF_MEM_NOC, 1, 16, SC7180_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SC7180_MASTER_GFX3D, 2, 32, SC7180_SLAVE_GEM_NOC_SNOC, SC7180_SLAVE_LLCC); -DEFINE_QNODE(llcc_mc, SC7180_MASTER_LLCC, 2, 4, SC7180_SLAVE_EBI1); -DEFINE_QNODE(qhm_mnoc_cfg, SC7180_MASTER_CNOC_MNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SC7180_MASTER_CAMNOC_HF0, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SC7180_MASTER_CAMNOC_HF1, 2, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SC7180_MASTER_CAMNOC_SF, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SC7180_MASTER_MDP0, 1, 32, SC7180_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SC7180_MASTER_ROTATOR, 1, 16, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SC7180_MASTER_VIDEO_P0, 1, 32, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SC7180_MASTER_VIDEO_PROC, 1, 8, SC7180_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SC7180_MASTER_NPU_SYS, 2, 32, SC7180_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_npu_cfg, SC7180_MASTER_NPU_NOC_CFG, 1, 4, SC7180_SLAVE_NPU_CAL_DP0, SC7180_SLAVE_NPU_CP, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, SC7180_SLAVE_NPU_DPM, SC7180_SLAVE_ISENSE_CFG, SC7180_SLAVE_NPU_LLM_CFG, SC7180_SLAVE_NPU_TCM, SC7180_SLAVE_SERVICE_NPU_NOC); -DEFINE_QNODE(qup_core_master_1, SC7180_MASTER_QUP_CORE_0, 1, 4, SC7180_SLAVE_QUP_CORE_0); -DEFINE_QNODE(qup_core_master_2, SC7180_MASTER_QUP_CORE_1, 1, 4, SC7180_SLAVE_QUP_CORE_1); -DEFINE_QNODE(qhm_snoc_cfg, SC7180_MASTER_SNOC_CFG, 1, 4, SC7180_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SC7180_MASTER_A1NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SC7180_MASTER_A2NOC_SNOC, 1, 16, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_SNOC_GEM_NOC_SF, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU); -DEFINE_QNODE(qnm_gemnoc, SC7180_MASTER_GEM_NOC_SNOC, 1, 8, SC7180_SLAVE_APPSS, SC7180_SLAVE_SNOC_CNOC, SC7180_SLAVE_IMEM, SC7180_SLAVE_PIMEM, SC7180_SLAVE_QDSS_STM, SC7180_SLAVE_TCU); -DEFINE_QNODE(qxm_pimem, SC7180_MASTER_PIMEM, 1, 8, SC7180_SLAVE_SNOC_GEM_NOC_GC, SC7180_SLAVE_IMEM); -DEFINE_QNODE(qns_a1noc_snoc, SC7180_SLAVE_A1NOC_SNOC, 1, 16, SC7180_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SC7180_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SC7180_SLAVE_A2NOC_SNOC, 1, 16, SC7180_MASTER_A2NOC_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SC7180_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SC7180_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qns_cdsp_gemnoc, SC7180_SLAVE_CDSP_GEM_NOC, 1, 32, SC7180_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SC7180_SLAVE_A1NOC_CFG, 1, 4, SC7180_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SC7180_SLAVE_A2NOC_CFG, 1, 4, SC7180_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SC7180_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy2, SC7180_SLAVE_AHB2PHY_CENTER, 1, 4); -DEFINE_QNODE(qhs_aop, SC7180_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SC7180_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_boot_rom, SC7180_SLAVE_BOOT_ROM, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SC7180_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_nrt_throttle_cfg, SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SC7180_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SC7180_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SC7180_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SC7180_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SC7180_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SC7180_SLAVE_CNOC_DDRSS, 1, 4, SC7180_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SC7180_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_display_rt_throttle_cfg, SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_display_throttle_cfg, SC7180_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SC7180_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SC7180_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SC7180_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SC7180_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SC7180_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SC7180_SLAVE_CNOC_MNOC_CFG, 1, 4, SC7180_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_mss_cfg, SC7180_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_npu_cfg, SC7180_SLAVE_NPU_CFG, 1, 4, SC7180_MASTER_NPU_NOC_CFG); -DEFINE_QNODE(qhs_npu_dma_throttle_cfg, SC7180_SLAVE_NPU_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_npu_dsp_throttle_cfg, SC7180_SLAVE_NPU_PROC_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SC7180_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SC7180_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SC7180_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SC7180_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_cfg, SC7180_SLAVE_QM_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_mpu_cfg, SC7180_SLAVE_QM_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SC7180_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SC7180_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SC7180_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SC7180_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_security, SC7180_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SC7180_SLAVE_SNOC_CFG, 1, 4, SC7180_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_tcsr, SC7180_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_1, SC7180_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tlmm_2, SC7180_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_3, SC7180_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SC7180_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3, SC7180_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SC7180_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_venus_throttle_cfg, SC7180_SLAVE_VENUS_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SC7180_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(srvc_cnoc, SC7180_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_gemnoc, SC7180_SLAVE_GEM_NOC_CFG, 1, 4, SC7180_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qhs_llcc, SC7180_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_snoc, SC7180_SLAVE_GEM_NOC_SNOC, 1, 8, SC7180_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SC7180_SLAVE_LLCC, 1, 16, SC7180_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SC7180_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SC7180_SLAVE_EBI1, 2, 4); -DEFINE_QNODE(qns_mem_noc_hf, SC7180_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SC7180_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC7180_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SC7180_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SC7180_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cp, SC7180_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SC7180_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SC7180_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SC7180_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SC7180_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SC7180_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SC7180_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qup_core_slave_1, SC7180_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(qup_core_slave_2, SC7180_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(qhs_apss, SC7180_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SC7180_SLAVE_SNOC_CNOC, 1, 8, SC7180_MASTER_SNOC_CNOC); -DEFINE_QNODE(qns_gemnoc_gc, SC7180_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC7180_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SC7180_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SC7180_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SC7180_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SC7180_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SC7180_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SC7180_MASTER_QSPI, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup_0 = { + .name = "qhm_qup_0", + .id = SC7180_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SC7180_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emmc = { + .name = "xm_emmc", + .id = SC7180_MASTER_EMMC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SC7180_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SC7180_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SC7180_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup_1 = { + .name = "qhm_qup_1", + .id = SC7180_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SC7180_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SC7180_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SC7180_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_usb3 = { + .name = "qhm_usb3", + .id = SC7180_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SC7180_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SC7180_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SC7180_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SC7180_MASTER_NPU, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qxm_npu_dsp = { + .name = "qxm_npu_dsp", + .id = SC7180_MASTER_NPU_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SC7180_MASTER_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 51, + .links = { SC7180_SLAVE_A1NOC_CFG, + SC7180_SLAVE_A2NOC_CFG, + SC7180_SLAVE_AHB2PHY_SOUTH, + SC7180_SLAVE_AHB2PHY_CENTER, + SC7180_SLAVE_AOP, + SC7180_SLAVE_AOSS, + SC7180_SLAVE_BOOT_ROM, + SC7180_SLAVE_CAMERA_CFG, + SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + SC7180_SLAVE_CLK_CTL, + SC7180_SLAVE_RBCPR_CX_CFG, + SC7180_SLAVE_RBCPR_MX_CFG, + SC7180_SLAVE_CRYPTO_0_CFG, + SC7180_SLAVE_DCC_CFG, + SC7180_SLAVE_CNOC_DDRSS, + SC7180_SLAVE_DISPLAY_CFG, + SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + SC7180_SLAVE_EMMC_CFG, + SC7180_SLAVE_GLM, + SC7180_SLAVE_GFX3D_CFG, + SC7180_SLAVE_IMEM_CFG, + SC7180_SLAVE_IPA_CFG, + SC7180_SLAVE_CNOC_MNOC_CFG, + SC7180_SLAVE_CNOC_MSS, + SC7180_SLAVE_NPU_CFG, + SC7180_SLAVE_NPU_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_PROC_BWMON_CFG, + SC7180_SLAVE_PDM, + SC7180_SLAVE_PIMEM_CFG, + SC7180_SLAVE_PRNG, + SC7180_SLAVE_QDSS_CFG, + SC7180_SLAVE_QM_CFG, + SC7180_SLAVE_QM_MPU_CFG, + SC7180_SLAVE_QSPI_0, + SC7180_SLAVE_QUP_0, + SC7180_SLAVE_QUP_1, + SC7180_SLAVE_SDCC_2, + SC7180_SLAVE_SECURITY, + SC7180_SLAVE_SNOC_CFG, + SC7180_SLAVE_TCSR, + SC7180_SLAVE_TLMM_WEST, + SC7180_SLAVE_TLMM_NORTH, + SC7180_SLAVE_TLMM_SOUTH, + SC7180_SLAVE_UFS_MEM_CFG, + SC7180_SLAVE_USB3, + SC7180_SLAVE_VENUS_CFG, + SC7180_SLAVE_VENUS_THROTTLE_CFG, + SC7180_SLAVE_VSENSE_CTRL_CFG, + SC7180_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SC7180_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 51, + .links = { SC7180_SLAVE_A1NOC_CFG, + SC7180_SLAVE_A2NOC_CFG, + SC7180_SLAVE_AHB2PHY_SOUTH, + SC7180_SLAVE_AHB2PHY_CENTER, + SC7180_SLAVE_AOP, + SC7180_SLAVE_AOSS, + SC7180_SLAVE_BOOT_ROM, + SC7180_SLAVE_CAMERA_CFG, + SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + SC7180_SLAVE_CLK_CTL, + SC7180_SLAVE_RBCPR_CX_CFG, + SC7180_SLAVE_RBCPR_MX_CFG, + SC7180_SLAVE_CRYPTO_0_CFG, + SC7180_SLAVE_DCC_CFG, + SC7180_SLAVE_CNOC_DDRSS, + SC7180_SLAVE_DISPLAY_CFG, + SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + SC7180_SLAVE_EMMC_CFG, + SC7180_SLAVE_GLM, + SC7180_SLAVE_GFX3D_CFG, + SC7180_SLAVE_IMEM_CFG, + SC7180_SLAVE_IPA_CFG, + SC7180_SLAVE_CNOC_MNOC_CFG, + SC7180_SLAVE_CNOC_MSS, + SC7180_SLAVE_NPU_CFG, + SC7180_SLAVE_NPU_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_PROC_BWMON_CFG, + SC7180_SLAVE_PDM, + SC7180_SLAVE_PIMEM_CFG, + SC7180_SLAVE_PRNG, + SC7180_SLAVE_QDSS_CFG, + SC7180_SLAVE_QM_CFG, + SC7180_SLAVE_QM_MPU_CFG, + SC7180_SLAVE_QSPI_0, + SC7180_SLAVE_QUP_0, + SC7180_SLAVE_QUP_1, + SC7180_SLAVE_SDCC_2, + SC7180_SLAVE_SECURITY, + SC7180_SLAVE_SNOC_CFG, + SC7180_SLAVE_TCSR, + SC7180_SLAVE_TLMM_WEST, + SC7180_SLAVE_TLMM_NORTH, + SC7180_SLAVE_TLMM_SOUTH, + SC7180_SLAVE_UFS_MEM_CFG, + SC7180_SLAVE_USB3, + SC7180_SLAVE_VENUS_CFG, + SC7180_SLAVE_VENUS_THROTTLE_CFG, + SC7180_SLAVE_VSENSE_CTRL_CFG, + SC7180_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SC7180_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_CFG, + SC7180_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_apps0 = { + .name = "acm_apps0", + .id = SC7180_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node acm_sys_tcu = { + .name = "acm_sys_tcu", + .id = SC7180_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SC7180_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, + SC7180_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SC7180_MASTER_COMPUTE_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SC7180_MASTER_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SC7180_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SC7180_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SC7180_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SC7180_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SC7180_SLAVE_GEM_NOC_SNOC, + SC7180_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SC7180_MASTER_LLCC, + .channels = 2, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SC7180_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SC7180_MASTER_CAMNOC_HF0, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SC7180_MASTER_CAMNOC_HF1, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SC7180_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SC7180_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SC7180_MASTER_ROTATOR, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SC7180_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SC7180_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys = { + .name = "amm_npu_sys", + .id = SC7180_MASTER_NPU_SYS, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_npu_cfg = { + .name = "qhm_npu_cfg", + .id = SC7180_MASTER_NPU_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 8, + .links = { SC7180_SLAVE_NPU_CAL_DP0, + SC7180_SLAVE_NPU_CP, + SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, + SC7180_SLAVE_NPU_DPM, + SC7180_SLAVE_ISENSE_CFG, + SC7180_SLAVE_NPU_LLM_CFG, + SC7180_SLAVE_NPU_TCM, + SC7180_SLAVE_SERVICE_NPU_NOC + }, +}; + +static struct qcom_icc_node qup_core_master_1 = { + .name = "qup_core_master_1", + .id = SC7180_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup_core_master_2 = { + .name = "qup_core_master_2", + .id = SC7180_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SC7180_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SC7180_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_SNOC_GEM_NOC_SF, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SC7180_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 7, + .links = { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_SNOC_GEM_NOC_SF, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM, + SC7180_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SC7180_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SC7180_SLAVE_APPSS, + SC7180_SLAVE_SNOC_CNOC, + SC7180_SLAVE_IMEM, + SC7180_SLAVE_PIMEM, + SC7180_SLAVE_QDSS_STM, + SC7180_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SC7180_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SC7180_SLAVE_SNOC_GEM_NOC_GC, + SC7180_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SC7180_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SC7180_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SC7180_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SC7180_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SC7180_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_cdsp_gemnoc = { + .name = "qns_cdsp_gemnoc", + .id = SC7180_SLAVE_CDSP_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SC7180_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SC7180_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SC7180_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .id = SC7180_SLAVE_AHB2PHY_CENTER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SC7180_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SC7180_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_boot_rom = { + .name = "qhs_boot_rom", + .id = SC7180_SLAVE_BOOT_ROM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SC7180_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { + .name = "qhs_camera_nrt_throttle_cfg", + .id = SC7180_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { + .name = "qhs_camera_rt_throttle_cfg", + .id = SC7180_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SC7180_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SC7180_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SC7180_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SC7180_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SC7180_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SC7180_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SC7180_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_rt_throttle_cfg = { + .name = "qhs_display_rt_throttle_cfg", + .id = SC7180_SLAVE_DISPLAY_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg = { + .name = "qhs_display_throttle_cfg", + .id = SC7180_SLAVE_DISPLAY_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg = { + .name = "qhs_emmc_cfg", + .id = SC7180_SLAVE_EMMC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SC7180_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SC7180_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SC7180_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SC7180_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SC7180_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SC7180_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SC7180_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_dma_throttle_cfg = { + .name = "qhs_npu_dma_throttle_cfg", + .id = SC7180_SLAVE_NPU_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = { + .name = "qhs_npu_dsp_throttle_cfg", + .id = SC7180_SLAVE_NPU_PROC_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SC7180_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SC7180_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SC7180_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SC7180_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_cfg = { + .name = "qhs_qm_cfg", + .id = SC7180_SLAVE_QM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg = { + .name = "qhs_qm_mpu_cfg", + .id = SC7180_SLAVE_QM_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SC7180_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SC7180_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SC7180_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SC7180_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SC7180_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SC7180_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SC7180_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_1 = { + .name = "qhs_tlmm_1", + .id = SC7180_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_2 = { + .name = "qhs_tlmm_2", + .id = SC7180_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_3 = { + .name = "qhs_tlmm_3", + .id = SC7180_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SC7180_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SC7180_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SC7180_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg = { + .name = "qhs_venus_throttle_cfg", + .id = SC7180_SLAVE_VENUS_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SC7180_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SC7180_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gemnoc = { + .name = "qhs_gemnoc", + .id = SC7180_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SC7180_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SC7180_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SC7180_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SC7180_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SC7180_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SC7180_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SC7180_SLAVE_EBI1, + .channels = 2, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SC7180_SLAVE_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SC7180_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SC7180_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SC7180_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 = { + .name = "qhs_cal_dp0", + .id = SC7180_SLAVE_NPU_CAL_DP0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cp = { + .name = "qhs_cp", + .id = SC7180_SLAVE_NPU_CP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon = { + .name = "qhs_dma_bwmon", + .id = SC7180_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dpm = { + .name = "qhs_dpm", + .id = SC7180_SLAVE_NPU_DPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_isense = { + .name = "qhs_isense", + .id = SC7180_SLAVE_ISENSE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llm = { + .name = "qhs_llm", + .id = SC7180_SLAVE_NPU_LLM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcm = { + .name = "qhs_tcm", + .id = SC7180_SLAVE_NPU_TCM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_npu_sys = { + .name = "qns_npu_sys", + .id = SC7180_SLAVE_NPU_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node srvc_noc = { + .name = "srvc_noc", + .id = SC7180_SLAVE_SERVICE_NPU_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup_core_slave_1 = { + .name = "qup_core_slave_1", + .id = SC7180_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup_core_slave_2 = { + .name = "qup_core_slave_2", + .id = SC7180_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SC7180_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SC7180_SLAVE_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SC7180_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SC7180_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SC7180_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SC7180_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SC7180_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SC7180_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SC7180_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SC7180_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 48, + .nodes = { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_aop, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_throttle_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_rt_throttle_cfg, + &qhs_display_throttle_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_npu_dma_throttle_cfg, + &qhs_npu_dsp_throttle_cfg, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm_1, + &qhs_tlmm_2, + &qhs_tlmm_3, + &qhs_ufs_mem_cfg, + &qhs_usb3, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .num_nodes = 8, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qhm_mnoc_cfg, + &qxm_mdp0, + &qxm_rot, + &qxm_venus0, + &qxm_venus_arm9 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qup_core_master_1, &qup_core_master_2 }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &acm_apps0 }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_cdsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .keepalive = false, + .num_nodes = 8, + .nodes = { &qhm_qspi, + &xm_sdc2, + &xm_emmc, + &qhs_ahb2phy2, + &qhs_emmc_cfg, + &qhs_pdm, + &qhs_qspi, + &qhs_sdc2 + }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qxm_pimem, &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_co3 = { + .name = "CO3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_npu_dsp }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_cn1, diff --git a/drivers/interconnect/qcom/sc7280.c b/drivers/interconnect/qcom/sc7280.c index 971f538bc98a..6592839b4d94 100644 --- a/drivers/interconnect/qcom/sc7280.c +++ b/drivers/interconnect/qcom/sc7280.c @@ -7,8 +7,9 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sc7280.h> #include "bcm-voter.h" diff --git a/drivers/interconnect/qcom/sc8180x.c b/drivers/interconnect/qcom/sc8180x.c index c76e3a6a98cd..0fb4898dabcf 100644 --- a/drivers/interconnect/qcom/sc8180x.c +++ b/drivers/interconnect/qcom/sc8180x.c @@ -7,7 +7,8 @@ #include <linux/device.h> #include <linux/interconnect-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sc8180x.h> diff --git a/drivers/interconnect/qcom/sc8280xp.c b/drivers/interconnect/qcom/sc8280xp.c index e56df893ec3e..b82c5493cbb5 100644 --- a/drivers/interconnect/qcom/sc8280xp.c +++ b/drivers/interconnect/qcom/sc8280xp.c @@ -7,8 +7,9 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sc8280xp.h> #include "bcm-voter.h" diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index e1aed937c86b..36962f7bd7bb 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -8,9 +8,8 @@ #include <linux/device.h> #include <linux/interconnect-provider.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_device.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/interconnect/qcom/sdm670.c b/drivers/interconnect/qcom/sdm670.c index bda955035518..540a2108b77c 100644 --- a/drivers/interconnect/qcom/sdm670.c +++ b/drivers/interconnect/qcom/sdm670.c @@ -6,155 +6,1260 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sdm670.h" -DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SOUTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670_SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DISPLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS, SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SDM670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAVE_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC_CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, SDM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM670_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM670_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_NOC_CFG, SDM670_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_GNOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC); -DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_GNOC); -DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0); -DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLAVE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); -DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); -DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER_A2NOC_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM_NOC_CFG); -DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MASTER_GNOC_SNOC); -DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MASTER_GNOC_MEM_NOC); -DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4); -DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32); -DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4); -DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CNOC); -DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic); -DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SDM670_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SDM670_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SDM670_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_emmc = { + .name = "xm_emmc", + .id = SDM670_MASTER_EMMC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SDM670_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SDM670_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SDM670_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SDM670_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDM670_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SDM670_MASTER_BLSP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SDM670_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDM670_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SDM670_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDM670_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SDM670_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SDM670_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SDM670_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SDM670_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qhm_spdm = { + .name = "qhm_spdm", + .id = SDM670_MASTER_SPDM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SDM670_MASTER_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 38, + .links = { SDM670_SLAVE_TLMM_SOUTH, + SDM670_SLAVE_CAMERA_CFG, + SDM670_SLAVE_SDCC_4, + SDM670_SLAVE_SDCC_2, + SDM670_SLAVE_CNOC_MNOC_CFG, + SDM670_SLAVE_UFS_MEM_CFG, + SDM670_SLAVE_GLM, + SDM670_SLAVE_PDM, + SDM670_SLAVE_A2NOC_CFG, + SDM670_SLAVE_QDSS_CFG, + SDM670_SLAVE_DISPLAY_CFG, + SDM670_SLAVE_TCSR, + SDM670_SLAVE_DCC_CFG, + SDM670_SLAVE_CNOC_DDRSS, + SDM670_SLAVE_SNOC_CFG, + SDM670_SLAVE_SOUTH_PHY_CFG, + SDM670_SLAVE_GRAPHICS_3D_CFG, + SDM670_SLAVE_VENUS_CFG, + SDM670_SLAVE_TSIF, + SDM670_SLAVE_CDSP_CFG, + SDM670_SLAVE_AOP, + SDM670_SLAVE_BLSP_2, + SDM670_SLAVE_SERVICE_CNOC, + SDM670_SLAVE_USB3, + SDM670_SLAVE_IPA_CFG, + SDM670_SLAVE_RBCPR_CX_CFG, + SDM670_SLAVE_A1NOC_CFG, + SDM670_SLAVE_AOSS, + SDM670_SLAVE_PRNG, + SDM670_SLAVE_VSENSE_CTRL_CFG, + SDM670_SLAVE_EMMC_CFG, + SDM670_SLAVE_BLSP_1, + SDM670_SLAVE_SPDM_WRAPPER, + SDM670_SLAVE_CRYPTO_0_CFG, + SDM670_SLAVE_PIMEM_CFG, + SDM670_SLAVE_TLMM_NORTH, + SDM670_SLAVE_CLK_CTL, + SDM670_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_cnoc = { + .name = "qhm_cnoc", + .id = SDM670_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM670_SLAVE_MEM_NOC_CFG, + SDM670_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_l3 = { + .name = "acm_l3", + .id = SDM670_MASTER_AMPSS_M0, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDM670_SLAVE_SERVICE_GNOC, + SDM670_SLAVE_GNOC_SNOC, + SDM670_SLAVE_GNOC_MEM_NOC + }, +}; + +static struct qcom_icc_node pm_gnoc_cfg = { + .name = "pm_gnoc_cfg", + .id = SDM670_MASTER_GNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_GNOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDM670_MASTER_LLCC, + .channels = 2, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDM670_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_memnoc_cfg = { + .name = "qhm_memnoc_cfg", + .id = SDM670_MASTER_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM670_SLAVE_SERVICE_MEM_NOC, + SDM670_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_apps = { + .name = "qnm_apps", + .id = SDM670_MASTER_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SDM670_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SDM670_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 3, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDM670_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SDM670_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SDM670_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SDM670_SLAVE_MEM_NOC_GNOC, + SDM670_SLAVE_LLCC, + SDM670_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SDM670_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SDM670_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SDM670_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SDM670_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SDM670_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SDM670_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SDM670_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SDM670_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 = { + .name = "qxm_venus1", + .id = SDM670_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SDM670_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDM670_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SDM670_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_SF, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SDM670_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 7, + .links = { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_SF, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_TCU, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gladiator_sodv = { + .name = "qnm_gladiator_sodv", + .id = SDM670_MASTER_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SDM670_SLAVE_PIMEM, + SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_TCU, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDM670_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 5, + .links = { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_APPSS, + SDM670_SLAVE_PIMEM, + SDM670_SLAVE_SNOC_CNOC, + SDM670_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SDM670_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_GC + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SDM670_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM670_SLAVE_OCIMEM, + SDM670_SLAVE_SNOC_MEM_NOC_GC + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SDM670_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SDM670_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SDM670_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SDM670_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SDM670_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SDM670_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SDM670_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SDM670_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDM670_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SDM670_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDM670_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg = { + .name = "qhs_compute_dsp_cfg", + .id = SDM670_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SDM670_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDM670_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SDM670_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDM670_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SDM670_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg = { + .name = "qhs_emmc_cfg", + .id = SDM670_SLAVE_EMMC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SDM670_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SDM670_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDM670_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDM670_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SDM670_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDM670_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_south = { + .name = "qhs_phy_refgen_south", + .id = SDM670_SLAVE_SOUTH_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SDM670_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDM670_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDM670_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_north = { + .name = "qhs_qupv3_north", + .id = SDM670_SLAVE_BLSP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_south = { + .name = "qhs_qupv3_south", + .id = SDM670_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SDM670_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SDM670_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDM670_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm = { + .name = "qhs_spdm", + .id = SDM670_SLAVE_SPDM_WRAPPER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDM670_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_north = { + .name = "qhs_tlmm_north", + .id = SDM670_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_south = { + .name = "qhs_tlmm_south", + .id = SDM670_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SDM670_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SDM670_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SDM670_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SDM670_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SDM670_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SDM670_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SDM670_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SDM670_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SDM670_SLAVE_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM670_MASTER_MEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gladiator_sodv = { + .name = "qns_gladiator_sodv", + .id = SDM670_SLAVE_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_GNOC_SNOC }, +}; + +static struct qcom_icc_node qns_gnoc_memnoc = { + .name = "qns_gnoc_memnoc", + .id = SDM670_SLAVE_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_MASTER_GNOC_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_gnoc = { + .name = "srvc_gnoc", + .id = SDM670_SLAVE_SERVICE_GNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDM670_SLAVE_EBI_CH0, + .channels = 2, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apps_io = { + .name = "qns_apps_io", + .id = SDM670_SLAVE_MEM_NOC_GNOC, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDM670_SLAVE_LLCC, + .channels = 2, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDM670_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_memnoc = { + .name = "srvc_memnoc", + .id = SDM670_SLAVE_SERVICE_MEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns2_mem_noc = { + .name = "qns2_mem_noc", + .id = SDM670_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SDM670_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM670_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SDM670_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDM670_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SDM670_SLAVE_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_memnoc_gc = { + .name = "qns_memnoc_gc", + .id = SDM670_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_memnoc_sf = { + .name = "qns_memnoc_sf", + .id = SDM670_SLAVE_SNOC_MEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM670_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDM670_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SDM670_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDM670_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDM670_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDM670_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_apps_io }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = true, + .num_nodes = 7, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &acm_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .num_nodes = 5, + .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh5 = { + .name = "SH5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 41, + .nodes = { &qhm_spdm, + &qnm_snoc, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_emmc_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_memnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qxm_pimem, &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qnm_gladiator_sodv, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn13 = { + .name = "SN13", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index 954e7bd13fc4..b9243c0aa626 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -7,7 +7,8 @@ #include <linux/interconnect.h> #include <linux/interconnect-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sdm845.h> @@ -15,165 +16,1502 @@ #include "icc-rpmh.h" #include "sdm845.h" -DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_tsif, SDM845_MASTER_TSIF, 1, 4, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SDM845_MASTER_SDCC_2, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_sdc4, SDM845_MASTER_SDCC_4, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_card, SDM845_MASTER_UFS_CARD, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SDM845_MASTER_UFS_MEM, 1, 8, SDM845_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_pcie_0, SDM845_MASTER_PCIE_0, 1, 8, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC); -DEFINE_QNODE(qhm_a2noc_cfg, SDM845_MASTER_A2NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SDM845_MASTER_QDSS_BAM, 1, 4, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup2, SDM845_MASTER_BLSP_2, 1, 4, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_cnoc, SDM845_MASTER_CNOC_A2NOC, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_crypto, SDM845_MASTER_CRYPTO, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SDM845_MASTER_IPA, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_pcie3_1, SDM845_MASTER_PCIE_1, 1, 8, SDM845_SLAVE_ANOC_PCIE_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDM845_MASTER_QDSS_ETR, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_usb3_0, SDM845_MASTER_USB3_0, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_usb3_1, SDM845_MASTER_USB3_1, 1, 8, SDM845_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM845_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM845_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM845_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM845_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qhm_spdm, SDM845_MASTER_SPDM, 1, 4, SDM845_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qhm_tic, SDM845_MASTER_TIC, 1, 4, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qnm_snoc, SDM845_MASTER_SNOC_CNOC, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(xm_qdss_dap, SDM845_MASTER_QDSS_DAP, 1, 8, SDM845_SLAVE_A1NOC_CFG, SDM845_SLAVE_A2NOC_CFG, SDM845_SLAVE_AOP, SDM845_SLAVE_AOSS, SDM845_SLAVE_CAMERA_CFG, SDM845_SLAVE_CLK_CTL, SDM845_SLAVE_CDSP_CFG, SDM845_SLAVE_RBCPR_CX_CFG, SDM845_SLAVE_CRYPTO_0_CFG, SDM845_SLAVE_DCC_CFG, SDM845_SLAVE_CNOC_DDRSS, SDM845_SLAVE_DISPLAY_CFG, SDM845_SLAVE_GLM, SDM845_SLAVE_GFX3D_CFG, SDM845_SLAVE_IMEM_CFG, SDM845_SLAVE_IPA_CFG, SDM845_SLAVE_CNOC_MNOC_CFG, SDM845_SLAVE_PCIE_0_CFG, SDM845_SLAVE_PCIE_1_CFG, SDM845_SLAVE_PDM, SDM845_SLAVE_SOUTH_PHY_CFG, SDM845_SLAVE_PIMEM_CFG, SDM845_SLAVE_PRNG, SDM845_SLAVE_QDSS_CFG, SDM845_SLAVE_BLSP_2, SDM845_SLAVE_BLSP_1, SDM845_SLAVE_SDCC_2, SDM845_SLAVE_SDCC_4, SDM845_SLAVE_SNOC_CFG, SDM845_SLAVE_SPDM_WRAPPER, SDM845_SLAVE_SPSS_CFG, SDM845_SLAVE_TCSR, SDM845_SLAVE_TLMM_NORTH, SDM845_SLAVE_TLMM_SOUTH, SDM845_SLAVE_TSIF, SDM845_SLAVE_UFS_CARD_CFG, SDM845_SLAVE_UFS_MEM_CFG, SDM845_SLAVE_USB3_0, SDM845_SLAVE_USB3_1, SDM845_SLAVE_VENUS_CFG, SDM845_SLAVE_VSENSE_CTRL_CFG, SDM845_SLAVE_CNOC_A2NOC, SDM845_SLAVE_SERVICE_CNOC); -DEFINE_QNODE(qhm_cnoc, SDM845_MASTER_CNOC_DC_NOC, 1, 4, SDM845_SLAVE_LLCC_CFG, SDM845_SLAVE_MEM_NOC_CFG); -DEFINE_QNODE(acm_l3, SDM845_MASTER_APPSS_PROC, 1, 16, SDM845_SLAVE_GNOC_SNOC, SDM845_SLAVE_GNOC_MEM_NOC, SDM845_SLAVE_SERVICE_GNOC); -DEFINE_QNODE(pm_gnoc_cfg, SDM845_MASTER_GNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_GNOC); -DEFINE_QNODE(llcc_mc, SDM845_MASTER_LLCC, 4, 4, SDM845_SLAVE_EBI1); -DEFINE_QNODE(acm_tcu, SDM845_MASTER_TCU_0, 1, 8, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_memnoc_cfg, SDM845_MASTER_MEM_NOC_CFG, 1, 4, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, SDM845_SLAVE_SERVICE_MEM_NOC); -DEFINE_QNODE(qnm_apps, SDM845_MASTER_GNOC_MEM_NOC, 2, 32, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SDM845_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SDM845_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDM845_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SDM845_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SDM845_MASTER_GFX3D, 2, 32, SDM845_SLAVE_MEM_NOC_GNOC, SDM845_SLAVE_LLCC, SDM845_SLAVE_MEM_NOC_SNOC); -DEFINE_QNODE(qhm_mnoc_cfg, SDM845_MASTER_CNOC_MNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SDM845_MASTER_CAMNOC_HF0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SDM845_MASTER_CAMNOC_HF1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SDM845_MASTER_CAMNOC_SF, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SDM845_MASTER_MDP0, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SDM845_MASTER_MDP1, 1, 32, SDM845_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SDM845_MASTER_ROTATOR, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SDM845_MASTER_VIDEO_P0, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SDM845_MASTER_VIDEO_P1, 1, 32, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SDM845_MASTER_VIDEO_PROC, 1, 8, SDM845_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SDM845_MASTER_SNOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SDM845_MASTER_A1NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SDM845_MASTER_A2NOC_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU); -DEFINE_QNODE(qnm_gladiator_sodv, SDM845_MASTER_GNOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PCIE_0, SDM845_SLAVE_PCIE_1, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM, SDM845_SLAVE_TCU); -DEFINE_QNODE(qnm_memnoc, SDM845_MASTER_MEM_NOC_SNOC, 1, 8, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_IMEM, SDM845_SLAVE_PIMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_pcie_anoc, SDM845_MASTER_ANOC_PCIE_SNOC, 1, 16, SDM845_SLAVE_APPSS, SDM845_SLAVE_SNOC_CNOC, SDM845_SLAVE_SNOC_MEM_NOC_SF, SDM845_SLAVE_IMEM, SDM845_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SDM845_MASTER_PIMEM, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM); -DEFINE_QNODE(xm_gic, SDM845_MASTER_GIC, 1, 8, SDM845_SLAVE_SNOC_MEM_NOC_GC, SDM845_SLAVE_IMEM); -DEFINE_QNODE(qns_a1noc_snoc, SDM845_SLAVE_A1NOC_SNOC, 1, 16, SDM845_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SDM845_SLAVE_SERVICE_A1NOC, 1, 4, 0); -DEFINE_QNODE(qns_pcie_a1noc_snoc, SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC); -DEFINE_QNODE(qns_a2noc_snoc, SDM845_SLAVE_A2NOC_SNOC, 1, 16, SDM845_MASTER_A2NOC_SNOC); -DEFINE_QNODE(qns_pcie_snoc, SDM845_SLAVE_ANOC_PCIE_SNOC, 1, 16, SDM845_MASTER_ANOC_PCIE_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SDM845_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SDM845_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qhs_a1_noc_cfg, SDM845_SLAVE_A1NOC_CFG, 1, 4, SDM845_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SDM845_SLAVE_A2NOC_CFG, 1, 4, SDM845_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_aop, SDM845_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDM845_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SDM845_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDM845_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp_cfg, SDM845_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SDM845_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDM845_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SDM845_SLAVE_DCC_CFG, 1, 4, SDM845_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_ddrss_cfg, SDM845_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SDM845_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SDM845_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SDM845_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SDM845_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDM845_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SDM845_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM845_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_pcie0_cfg, SDM845_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie_gen3_cfg, SDM845_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SDM845_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_south, SDM845_SLAVE_SOUTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SDM845_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SDM845_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDM845_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SDM845_SLAVE_BLSP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SDM845_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SDM845_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SDM845_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDM845_SLAVE_SNOC_CFG, 1, 4, SDM845_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spdm, SDM845_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SDM845_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDM845_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SDM845_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SDM845_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tsif, SDM845_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SDM845_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SDM845_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SDM845_SLAVE_USB3_0, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SDM845_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SDM845_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM845_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SDM845_SLAVE_CNOC_A2NOC, 1, 8, SDM845_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SDM845_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SDM845_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SDM845_SLAVE_MEM_NOC_CFG, 1, 4, SDM845_MASTER_MEM_NOC_CFG); -DEFINE_QNODE(qns_gladiator_sodv, SDM845_SLAVE_GNOC_SNOC, 1, 8, SDM845_MASTER_GNOC_SNOC); -DEFINE_QNODE(qns_gnoc_memnoc, SDM845_SLAVE_GNOC_MEM_NOC, 2, 32, SDM845_MASTER_GNOC_MEM_NOC); -DEFINE_QNODE(srvc_gnoc, SDM845_SLAVE_SERVICE_GNOC, 1, 4); -DEFINE_QNODE(ebi, SDM845_SLAVE_EBI1, 4, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_apps_io, SDM845_SLAVE_MEM_NOC_GNOC, 1, 32); -DEFINE_QNODE(qns_llcc, SDM845_SLAVE_LLCC, 4, 16, SDM845_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDM845_SLAVE_MEM_NOC_SNOC, 1, 8, SDM845_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(srvc_memnoc, SDM845_SLAVE_SERVICE_MEM_NOC, 1, 4); -DEFINE_QNODE(qns2_mem_noc, SDM845_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM845_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SDM845_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM845_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SDM845_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SDM845_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SDM845_SLAVE_SNOC_CNOC, 1, 8, SDM845_MASTER_SNOC_CNOC); -DEFINE_QNODE(qns_memnoc_gc, SDM845_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM845_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_memnoc_sf, SDM845_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM845_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDM845_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pcie, SDM845_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(qxs_pcie_gen3, SDM845_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(qxs_pimem, SDM845_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDM845_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SDM845_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDM845_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", false, &qhm_spdm, &qhm_tic, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pcie0_cfg, &qhs_pcie_gen3_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qxs_pcie); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qxs_pcie_gen3); -DEFINE_QBCM(bcm_sn9, "SN9", false, &srvc_aggre1_noc, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &srvc_aggre2_noc, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gladiator_sodv, &xm_gic); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qnm_pcie_anoc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SDM845_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SDM845_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SDM845_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SDM845_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SDM845_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SDM845_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SDM845_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie_0 = { + .name = "xm_pcie_0", + .id = SDM845_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SDM845_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDM845_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SDM845_MASTER_BLSP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SDM845_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDM845_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SDM845_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SDM845_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDM845_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SDM845_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SDM845_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SDM845_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SDM845_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SDM845_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qhm_spdm = { + .name = "qhm_spdm", + .id = SDM845_MASTER_SPDM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qhm_tic = { + .name = "qhm_tic", + .id = SDM845_MASTER_TIC, + .channels = 1, + .buswidth = 4, + .num_links = 43, + .links = { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_CNOC_A2NOC, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SDM845_MASTER_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 42, + .links = { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SDM845_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 43, + .links = { SDM845_SLAVE_A1NOC_CFG, + SDM845_SLAVE_A2NOC_CFG, + SDM845_SLAVE_AOP, + SDM845_SLAVE_AOSS, + SDM845_SLAVE_CAMERA_CFG, + SDM845_SLAVE_CLK_CTL, + SDM845_SLAVE_CDSP_CFG, + SDM845_SLAVE_RBCPR_CX_CFG, + SDM845_SLAVE_CRYPTO_0_CFG, + SDM845_SLAVE_DCC_CFG, + SDM845_SLAVE_CNOC_DDRSS, + SDM845_SLAVE_DISPLAY_CFG, + SDM845_SLAVE_GLM, + SDM845_SLAVE_GFX3D_CFG, + SDM845_SLAVE_IMEM_CFG, + SDM845_SLAVE_IPA_CFG, + SDM845_SLAVE_CNOC_MNOC_CFG, + SDM845_SLAVE_PCIE_0_CFG, + SDM845_SLAVE_PCIE_1_CFG, + SDM845_SLAVE_PDM, + SDM845_SLAVE_SOUTH_PHY_CFG, + SDM845_SLAVE_PIMEM_CFG, + SDM845_SLAVE_PRNG, + SDM845_SLAVE_QDSS_CFG, + SDM845_SLAVE_BLSP_2, + SDM845_SLAVE_BLSP_1, + SDM845_SLAVE_SDCC_2, + SDM845_SLAVE_SDCC_4, + SDM845_SLAVE_SNOC_CFG, + SDM845_SLAVE_SPDM_WRAPPER, + SDM845_SLAVE_SPSS_CFG, + SDM845_SLAVE_TCSR, + SDM845_SLAVE_TLMM_NORTH, + SDM845_SLAVE_TLMM_SOUTH, + SDM845_SLAVE_TSIF, + SDM845_SLAVE_UFS_CARD_CFG, + SDM845_SLAVE_UFS_MEM_CFG, + SDM845_SLAVE_USB3_0, + SDM845_SLAVE_USB3_1, + SDM845_SLAVE_VENUS_CFG, + SDM845_SLAVE_VSENSE_CTRL_CFG, + SDM845_SLAVE_CNOC_A2NOC, + SDM845_SLAVE_SERVICE_CNOC + }, +}; + +static struct qcom_icc_node qhm_cnoc = { + .name = "qhm_cnoc", + .id = SDM845_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM845_SLAVE_LLCC_CFG, + SDM845_SLAVE_MEM_NOC_CFG + }, +}; + +static struct qcom_icc_node acm_l3 = { + .name = "acm_l3", + .id = SDM845_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDM845_SLAVE_GNOC_SNOC, + SDM845_SLAVE_GNOC_MEM_NOC, + SDM845_SLAVE_SERVICE_GNOC + }, +}; + +static struct qcom_icc_node pm_gnoc_cfg = { + .name = "pm_gnoc_cfg", + .id = SDM845_MASTER_GNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_GNOC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDM845_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDM845_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_memnoc_cfg = { + .name = "qhm_memnoc_cfg", + .id = SDM845_MASTER_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, + SDM845_SLAVE_SERVICE_MEM_NOC + }, +}; + +static struct qcom_icc_node qnm_apps = { + .name = "qnm_apps", + .id = SDM845_MASTER_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SDM845_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SDM845_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 3, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDM845_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SDM845_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SDM845_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SDM845_SLAVE_MEM_NOC_GNOC, + SDM845_SLAVE_LLCC, + SDM845_SLAVE_MEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SDM845_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SDM845_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SDM845_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SDM845_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SDM845_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SDM845_MASTER_MDP1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SDM845_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SDM845_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 = { + .name = "qxm_venus1", + .id = SDM845_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SDM845_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDM845_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SDM845_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SDM845_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 9, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PCIE_0, + SDM845_SLAVE_PCIE_1, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM, + SDM845_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gladiator_sodv = { + .name = "qnm_gladiator_sodv", + .id = SDM845_MASTER_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 8, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PCIE_0, + SDM845_SLAVE_PCIE_1, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM, + SDM845_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDM845_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 5, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_PIMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_pcie_anoc = { + .name = "qnm_pcie_anoc", + .id = SDM845_MASTER_ANOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 5, + .links = { SDM845_SLAVE_APPSS, + SDM845_SLAVE_SNOC_CNOC, + SDM845_SLAVE_SNOC_MEM_NOC_SF, + SDM845_SLAVE_IMEM, + SDM845_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SDM845_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, + SDM845_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SDM845_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDM845_SLAVE_SNOC_MEM_NOC_GC, + SDM845_SLAVE_IMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SDM845_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SDM845_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { 0 }, +}; + +static struct qcom_icc_node qns_pcie_a1noc_snoc = { + .name = "qns_pcie_a1noc_snoc", + .id = SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SDM845_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_snoc = { + .name = "qns_pcie_snoc", + .id = SDM845_SLAVE_ANOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_ANOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SDM845_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SDM845_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SDM845_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SDM845_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SDM845_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDM845_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SDM845_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDM845_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp_cfg = { + .name = "qhs_compute_dsp_cfg", + .id = SDM845_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SDM845_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDM845_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SDM845_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDM845_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SDM845_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SDM845_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SDM845_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDM845_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDM845_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SDM845_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SDM845_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_gen3_cfg = { + .name = "qhs_pcie_gen3_cfg", + .id = SDM845_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDM845_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_south = { + .name = "qhs_phy_refgen_south", + .id = SDM845_SLAVE_SOUTH_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SDM845_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDM845_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDM845_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_north = { + .name = "qhs_qupv3_north", + .id = SDM845_SLAVE_BLSP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_south = { + .name = "qhs_qupv3_south", + .id = SDM845_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SDM845_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SDM845_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDM845_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm = { + .name = "qhs_spdm", + .id = SDM845_SLAVE_SPDM_WRAPPER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SDM845_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDM845_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_north = { + .name = "qhs_tlmm_north", + .id = SDM845_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_south = { + .name = "qhs_tlmm_south", + .id = SDM845_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SDM845_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SDM845_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SDM845_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SDM845_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SDM845_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SDM845_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SDM845_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SDM845_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SDM845_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SDM845_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SDM845_SLAVE_MEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDM845_MASTER_MEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gladiator_sodv = { + .name = "qns_gladiator_sodv", + .id = SDM845_SLAVE_GNOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_GNOC_SNOC }, +}; + +static struct qcom_icc_node qns_gnoc_memnoc = { + .name = "qns_gnoc_memnoc", + .id = SDM845_SLAVE_GNOC_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_MASTER_GNOC_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_gnoc = { + .name = "srvc_gnoc", + .id = SDM845_SLAVE_SERVICE_GNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDM845_SLAVE_EBI1, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SDM845_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_apps_io = { + .name = "qns_apps_io", + .id = SDM845_SLAVE_MEM_NOC_GNOC, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDM845_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDM845_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_memnoc = { + .name = "srvc_memnoc", + .id = SDM845_SLAVE_SERVICE_MEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns2_mem_noc = { + .name = "qns2_mem_noc", + .id = SDM845_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SDM845_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SDM845_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SDM845_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDM845_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SDM845_SLAVE_SNOC_CNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_CNOC }, +}; + +static struct qcom_icc_node qns_memnoc_gc = { + .name = "qns_memnoc_gc", + .id = SDM845_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_memnoc_sf = { + .name = "qns_memnoc_sf", + .id = SDM845_SLAVE_SNOC_MEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDM845_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDM845_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pcie = { + .name = "qxs_pcie", + .id = SDM845_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pcie_gen3 = { + .name = "qxs_pcie_gen3", + .id = SDM845_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SDM845_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDM845_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDM845_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDM845_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_apps_io }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = true, + .num_nodes = 7, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &acm_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .num_nodes = 5, + .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh5 = { + .name = "SH5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_memnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = false, + .num_nodes = 47, + .nodes = { &qhm_spdm, + &qhm_tic, + &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp_cfg, + &qhs_cpr_cx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_pcie0_cfg, + &qhs_pcie_gen3_cfg, + &qhs_pdm, + &qhs_phy_refgen_south, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_memnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .num_nodes = 3, + .nodes = { &qhs_apss, &srvc_snoc, &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_pcie_gen3 }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .num_nodes = 2, + .nodes = { &srvc_aggre1_noc, &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .num_nodes = 2, + .nodes = { &srvc_aggre2_noc, &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qnm_gladiator_sodv, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_pcie_anoc }, +}; + +static struct qcom_icc_bcm bcm_sn15 = { + .name = "SN15", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_sn9, diff --git a/drivers/interconnect/qcom/sdx55.c b/drivers/interconnect/qcom/sdx55.c index 130a828c3873..4117db046fa0 100644 --- a/drivers/interconnect/qcom/sdx55.c +++ b/drivers/interconnect/qcom/sdx55.c @@ -10,94 +10,778 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sdx55.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sdx55.h" -DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0); -DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC); -DEFINE_QNODE(xm_apps_rdwr, SDX55_MASTER_AMPSS_M0, 1, 16, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_audio, SDX55_MASTER_AUDIO, 1, 4, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_blsp1, SDX55_MASTER_BLSP_1, 1, 4, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SDX55_MASTER_QDSS_BAM, 1, 4, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_qpic, SDX55_MASTER_QPIC, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); -DEFINE_QNODE(qhm_snoc_cfg, SDX55_MASTER_SNOC_CFG, 1, 4, SDX55_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qhm_spmi_fetcher1, SDX55_MASTER_SPMI_FETCHER, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); -DEFINE_QNODE(qnm_aggre_noc, SDX55_MASTER_ANOC_SNOC, 1, 8, SDX55_SLAVE_PCIE_0, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_USB3, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_ipa, SDX55_MASTER_IPA, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_TLMM, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_memnoc, SDX55_MASTER_MEM_NOC_SNOC, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(qnm_memnoc_pcie, SDX55_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_SLAVE_PCIE_0); -DEFINE_QNODE(qxm_crypto, SDX55_MASTER_CRYPTO_CORE_0, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP); -DEFINE_QNODE(xm_emac, SDX55_MASTER_EMAC, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_ipa2pcie_slv, SDX55_MASTER_IPA_PCIE, 1, 8, SDX55_SLAVE_PCIE_0); -DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG); -DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO); -DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC); -DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4); -DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0); -DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(qns_sys_pcie, SDX55_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhs_aop, SDX55_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SDX55_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SDX55_SLAVE_APPSS, 1, 4); -DEFINE_QNODE(qhs_audio, SDX55_SLAVE_AUDIO, 1, 4); -DEFINE_QNODE(qhs_blsp1, SDX55_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDX55_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDX55_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SDX55_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_ecc_cfg, SDX55_SLAVE_ECC_CFG, 1, 4); -DEFINE_QNODE(qhs_emac_cfg, SDX55_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SDX55_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDX55_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mss_cfg, SDX55_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_pcie_parf, SDX55_SLAVE_PCIE_PARF, 1, 4); -DEFINE_QNODE(qhs_pdm, SDX55_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_prng, SDX55_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDX55_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qpic, SDX55_SLAVE_QPIC, 1, 4); -DEFINE_QNODE(qhs_sdc1, SDX55_SLAVE_SDCC_1, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDX55_SLAVE_SNOC_CFG, 1, 4, SDX55_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spmi_fetcher, SDX55_SLAVE_SPMI_FETCHER, 1, 4); -DEFINE_QNODE(qhs_spmi_vgi_coex, SDX55_SLAVE_SPMI_VGI_COEX, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDX55_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SDX55_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_usb3, SDX55_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_phy, SDX55_SLAVE_USB3_PHY_CFG, 1, 4); -DEFINE_QNODE(qns_aggre_noc, SDX55_SLAVE_ANOC_SNOC, 1, 8, SDX55_MASTER_ANOC_SNOC); -DEFINE_QNODE(qns_snoc_memnoc, SDX55_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDX55_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDX55_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDX55_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie, SDX55_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SDX55_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg); -DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); -DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); -DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); -DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_pn5, "PN5", false, &qxm_crypto); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, - &qns_aggre_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qhm_qdss_bam, &xm_qdss_etr); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv); +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDX55_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDX55_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDX55_SLAVE_LLCC, + SDX55_SLAVE_MEM_NOC_SNOC, + SDX55_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDX55_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_apps_rdwr = { + .name = "xm_apps_rdwr", + .id = SDX55_MASTER_AMPSS_M0, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX55_SLAVE_LLCC, + SDX55_SLAVE_MEM_NOC_SNOC, + SDX55_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_audio = { + .name = "qhm_audio", + .id = SDX55_MASTER_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_blsp1 = { + .name = "qhm_blsp1", + .id = SDX55_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDX55_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 28, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_qpic = { + .name = "qhm_qpic", + .id = SDX55_MASTER_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 5, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP, + SDX55_SLAVE_AUDIO + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDX55_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qhm_spmi_fetcher1 = { + .name = "qhm_spmi_fetcher1", + .id = SDX55_MASTER_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP + }, +}; + +static struct qcom_icc_node qnm_aggre_noc = { + .name = "qnm_aggre_noc", + .id = SDX55_MASTER_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 30, + .links = { SDX55_SLAVE_PCIE_0, + SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_USB3, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_APPSS, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_ipa = { + .name = "qnm_ipa", + .id = SDX55_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 27, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDX55_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 29, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_TLMM, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QDSS_STM, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_APPSS, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie = { + .name = "qnm_memnoc_pcie", + .id = SDX55_MASTER_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDX55_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP + }, +}; + +static struct qcom_icc_node xm_emac = { + .name = "xm_emac", + .id = SDX55_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_ipa2pcie_slv = { + .name = "xm_ipa2pcie_slv", + .id = SDX55_MASTER_IPA_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .id = SDX55_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDX55_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 28, + .links = { SDX55_SLAVE_SNOC_CFG, + SDX55_SLAVE_EMAC_CFG, + SDX55_SLAVE_USB3, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_SPMI_FETCHER, + SDX55_SLAVE_QDSS_CFG, + SDX55_SLAVE_PDM, + SDX55_SLAVE_SNOC_MEM_NOC_GC, + SDX55_SLAVE_TCSR, + SDX55_SLAVE_CNOC_DDRSS, + SDX55_SLAVE_SPMI_VGI_COEX, + SDX55_SLAVE_QPIC, + SDX55_SLAVE_OCIMEM, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_USB3_PHY_CFG, + SDX55_SLAVE_AOP, + SDX55_SLAVE_BLSP_1, + SDX55_SLAVE_SDCC_1, + SDX55_SLAVE_CNOC_MSS, + SDX55_SLAVE_PCIE_PARF, + SDX55_SLAVE_ECC_CFG, + SDX55_SLAVE_AUDIO, + SDX55_SLAVE_AOSS, + SDX55_SLAVE_PRNG, + SDX55_SLAVE_CRYPTO_0_CFG, + SDX55_SLAVE_TCU, + SDX55_SLAVE_CLK_CTL, + SDX55_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .id = SDX55_MASTER_SDCC_1, + .channels = 1, + .buswidth = 8, + .num_links = 5, + .links = { SDX55_SLAVE_AOSS, + SDX55_SLAVE_IPA_CFG, + SDX55_SLAVE_ANOC_SNOC, + SDX55_SLAVE_AOP, + SDX55_SLAVE_AUDIO + }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .id = SDX55_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDX55_SLAVE_EBI_CH0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDX55_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX55_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDX55_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_sys_pcie = { + .name = "qns_sys_pcie", + .id = SDX55_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SDX55_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDX55_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDX55_SLAVE_APPSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_audio = { + .name = "qhs_audio", + .id = SDX55_SLAVE_AUDIO, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_blsp1 = { + .name = "qhs_blsp1", + .id = SDX55_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDX55_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDX55_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDX55_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ecc_cfg = { + .name = "qhs_ecc_cfg", + .id = SDX55_SLAVE_ECC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac_cfg = { + .name = "qhs_emac_cfg", + .id = SDX55_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDX55_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDX55_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SDX55_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_parf = { + .name = "qhs_pcie_parf", + .id = SDX55_SLAVE_PCIE_PARF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDX55_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDX55_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDX55_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qpic = { + .name = "qhs_qpic", + .id = SDX55_SLAVE_QPIC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .id = SDX55_SLAVE_SDCC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDX55_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX55_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spmi_fetcher = { + .name = "qhs_spmi_fetcher", + .id = SDX55_SLAVE_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex = { + .name = "qhs_spmi_vgi_coex", + .id = SDX55_SLAVE_SPMI_VGI_COEX, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDX55_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SDX55_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SDX55_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_phy = { + .name = "qhs_usb3_phy", + .id = SDX55_SLAVE_USB3_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_aggre_noc = { + .name = "qns_aggre_noc", + .id = SDX55_SLAVE_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_snoc_memnoc = { + .name = "qns_snoc_memnoc", + .id = SDX55_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX55_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDX55_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDX55_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .id = SDX55_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDX55_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDX55_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_pn0 = { + .name = "PN0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qhm_snoc_cfg }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xm_apps_rdwr }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qns_memnoc_snoc, &qns_sys_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_snoc_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_pn1 = { + .name = "PN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xm_sdc1 }, +}; + +static struct qcom_icc_bcm bcm_pn2 = { + .name = "PN2", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_audio, &qhm_spmi_fetcher1 }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_pn3 = { + .name = "PN3", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_blsp1, &qhm_qpic }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_pn5 = { + .name = "PN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .num_nodes = 5, + .nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_qdss_bam, &xm_qdss_etr }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qnm_ipa, &xm_ipa2pcie_slv }, +}; static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, diff --git a/drivers/interconnect/qcom/sdx65.c b/drivers/interconnect/qcom/sdx65.c index b16d31d53e9b..d3a6c6c148e5 100644 --- a/drivers/interconnect/qcom/sdx65.c +++ b/drivers/interconnect/qcom/sdx65.c @@ -6,90 +6,769 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sdx65.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sdx65.h" -DEFINE_QNODE(llcc_mc, SDX65_MASTER_LLCC, 1, 4, SDX65_SLAVE_EBI1); -DEFINE_QNODE(acm_tcu, SDX65_MASTER_TCU_0, 1, 8, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SDX65_MASTER_SNOC_GC_MEM_NOC, 1, 16, SDX65_SLAVE_LLCC); -DEFINE_QNODE(xm_apps_rdwr, SDX65_MASTER_APPSS_PROC, 1, 16, SDX65_SLAVE_LLCC, SDX65_SLAVE_MEM_NOC_SNOC, SDX65_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_audio, SDX65_MASTER_AUDIO, 1, 4, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_blsp1, SDX65_MASTER_BLSP_1, 1, 4, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SDX65_MASTER_QDSS_BAM, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qhm_qpic, SDX65_MASTER_QPIC, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qhm_snoc_cfg, SDX65_MASTER_SNOC_CFG, 1, 4, SDX65_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qhm_spmi_fetcher1, SDX65_MASTER_SPMI_FETCHER, 1, 4, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(qnm_aggre_noc, SDX65_MASTER_ANOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qnm_ipa, SDX65_MASTER_IPA, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_PCIE_0, SDX65_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_memnoc, SDX65_MASTER_MEM_NOC_SNOC, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_APPSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_IMEM, SDX65_SLAVE_QDSS_STM, SDX65_SLAVE_TCU); -DEFINE_QNODE(qnm_memnoc_pcie, SDX65_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_SLAVE_PCIE_0); -DEFINE_QNODE(qxm_crypto, SDX65_MASTER_CRYPTO, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_ipa2pcie_slv, SDX65_MASTER_IPA_PCIE, 1, 8, SDX65_SLAVE_PCIE_0); -DEFINE_QNODE(xm_pcie, SDX65_MASTER_PCIE_0, 1, 8, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_qdss_etr, SDX65_MASTER_QDSS_ETR, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_BLSP_1, SDX65_SLAVE_CLK_CTL, SDX65_SLAVE_CRYPTO_0_CFG, SDX65_SLAVE_CNOC_DDRSS, SDX65_SLAVE_ECC_CFG, SDX65_SLAVE_IMEM_CFG, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_CNOC_MSS, SDX65_SLAVE_PCIE_PARF, SDX65_SLAVE_PDM, SDX65_SLAVE_PRNG, SDX65_SLAVE_QDSS_CFG, SDX65_SLAVE_QPIC, SDX65_SLAVE_SDCC_1, SDX65_SLAVE_SNOC_CFG, SDX65_SLAVE_SPMI_FETCHER, SDX65_SLAVE_SPMI_VGI_COEX, SDX65_SLAVE_TCSR, SDX65_SLAVE_TLMM, SDX65_SLAVE_USB3, SDX65_SLAVE_USB3_PHY_CFG, SDX65_SLAVE_SNOC_MEM_NOC_GC, SDX65_SLAVE_IMEM, SDX65_SLAVE_TCU); -DEFINE_QNODE(xm_sdc1, SDX65_MASTER_SDCC_1, 1, 8, SDX65_SLAVE_AOSS, SDX65_SLAVE_AUDIO, SDX65_SLAVE_IPA_CFG, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(xm_usb3, SDX65_MASTER_USB3, 1, 8, SDX65_SLAVE_ANOC_SNOC); -DEFINE_QNODE(ebi, SDX65_SLAVE_EBI1, 1, 4); -DEFINE_QNODE(qns_llcc, SDX65_SLAVE_LLCC, 1, 16, SDX65_MASTER_LLCC); -DEFINE_QNODE(qns_memnoc_snoc, SDX65_SLAVE_MEM_NOC_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_SNOC); -DEFINE_QNODE(qns_sys_pcie, SDX65_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX65_MASTER_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhs_aoss, SDX65_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SDX65_SLAVE_APPSS, 1, 4); -DEFINE_QNODE(qhs_audio, SDX65_SLAVE_AUDIO, 1, 4); -DEFINE_QNODE(qhs_blsp1, SDX65_SLAVE_BLSP_1, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SDX65_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SDX65_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SDX65_SLAVE_CNOC_DDRSS, 1, 4); -DEFINE_QNODE(qhs_ecc_cfg, SDX65_SLAVE_ECC_CFG, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SDX65_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SDX65_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mss_cfg, SDX65_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_pcie_parf, SDX65_SLAVE_PCIE_PARF, 1, 4); -DEFINE_QNODE(qhs_pdm, SDX65_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_prng, SDX65_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SDX65_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qpic, SDX65_SLAVE_QPIC, 1, 4); -DEFINE_QNODE(qhs_sdc1, SDX65_SLAVE_SDCC_1, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SDX65_SLAVE_SNOC_CFG, 1, 4, SDX65_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spmi_fetcher, SDX65_SLAVE_SPMI_FETCHER, 1, 4); -DEFINE_QNODE(qhs_spmi_vgi_coex, SDX65_SLAVE_SPMI_VGI_COEX, 1, 4); -DEFINE_QNODE(qhs_tcsr, SDX65_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SDX65_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_usb3, SDX65_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_phy, SDX65_SLAVE_USB3_PHY_CFG, 1, 4); -DEFINE_QNODE(qns_aggre_noc, SDX65_SLAVE_ANOC_SNOC, 1, 8, SDX65_MASTER_ANOC_SNOC); -DEFINE_QNODE(qns_snoc_memnoc, SDX65_SLAVE_SNOC_MEM_NOC_GC, 1, 16, SDX65_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qxs_imem, SDX65_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SDX65_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie, SDX65_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SDX65_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SDX65_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_pn0, "PN0", true, &qhm_snoc_cfg, &qhs_aoss, &qhs_apss, &qhs_audio, &qhs_blsp1, &qhs_clk_ctl, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_ecc_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mss_cfg, &qhs_pcie_parf, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_sdc1, &qhs_snoc_cfg, &qhs_spmi_fetcher, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &srvc_snoc); -DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1); -DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1); -DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic); -DEFINE_QBCM(bcm_pn4, "PN4", false, &qxm_crypto); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_memnoc_snoc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_sys_tcu_cfg); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qhm_qdss_bam, &xm_qdss_etr); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_memnoc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc_pcie); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_ipa, &xm_ipa2pcie_slv); +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SDX65_MASTER_LLCC, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node acm_tcu = { + .name = "acm_tcu", + .id = SDX65_MASTER_TCU_0, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SDX65_SLAVE_LLCC, + SDX65_SLAVE_MEM_NOC_SNOC, + SDX65_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SDX65_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX65_SLAVE_LLCC }, +}; + +static struct qcom_icc_node xm_apps_rdwr = { + .name = "xm_apps_rdwr", + .id = SDX65_MASTER_APPSS_PROC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SDX65_SLAVE_LLCC, + SDX65_SLAVE_MEM_NOC_SNOC, + SDX65_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_audio = { + .name = "qhm_audio", + .id = SDX65_MASTER_AUDIO, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_blsp1 = { + .name = "qhm_blsp1", + .id = SDX65_MASTER_BLSP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SDX65_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 26, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qhm_qpic = { + .name = "qhm_qpic", + .id = SDX65_MASTER_QPIC, + .channels = 1, + .buswidth = 4, + .num_links = 4, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SDX65_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qhm_spmi_fetcher1 = { + .name = "qhm_spmi_fetcher1", + .id = SDX65_MASTER_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_aggre_noc = { + .name = "qnm_aggre_noc", + .id = SDX65_MASTER_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 29, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_APPSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_PCIE_0, + SDX65_SLAVE_QDSS_STM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_ipa = { + .name = "qnm_ipa", + .id = SDX65_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 26, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_PCIE_0, + SDX65_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_memnoc = { + .name = "qnm_memnoc", + .id = SDX65_MASTER_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 27, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_APPSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_QDSS_STM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_memnoc_pcie = { + .name = "qnm_memnoc_pcie", + .id = SDX65_MASTER_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SDX65_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node xm_ipa2pcie_slv = { + .name = "xm_ipa2pcie_slv", + .id = SDX65_MASTER_IPA_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_PCIE_0 }, +}; + +static struct qcom_icc_node xm_pcie = { + .name = "xm_pcie", + .id = SDX65_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SDX65_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 26, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_BLSP_1, + SDX65_SLAVE_CLK_CTL, + SDX65_SLAVE_CRYPTO_0_CFG, + SDX65_SLAVE_CNOC_DDRSS, + SDX65_SLAVE_ECC_CFG, + SDX65_SLAVE_IMEM_CFG, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_CNOC_MSS, + SDX65_SLAVE_PCIE_PARF, + SDX65_SLAVE_PDM, + SDX65_SLAVE_PRNG, + SDX65_SLAVE_QDSS_CFG, + SDX65_SLAVE_QPIC, + SDX65_SLAVE_SDCC_1, + SDX65_SLAVE_SNOC_CFG, + SDX65_SLAVE_SPMI_FETCHER, + SDX65_SLAVE_SPMI_VGI_COEX, + SDX65_SLAVE_TCSR, + SDX65_SLAVE_TLMM, + SDX65_SLAVE_USB3, + SDX65_SLAVE_USB3_PHY_CFG, + SDX65_SLAVE_SNOC_MEM_NOC_GC, + SDX65_SLAVE_IMEM, + SDX65_SLAVE_TCU + }, +}; + +static struct qcom_icc_node xm_sdc1 = { + .name = "xm_sdc1", + .id = SDX65_MASTER_SDCC_1, + .channels = 1, + .buswidth = 8, + .num_links = 4, + .links = { SDX65_SLAVE_AOSS, + SDX65_SLAVE_AUDIO, + SDX65_SLAVE_IPA_CFG, + SDX65_SLAVE_ANOC_SNOC + }, +}; + +static struct qcom_icc_node xm_usb3 = { + .name = "xm_usb3", + .id = SDX65_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_SLAVE_ANOC_SNOC }, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SDX65_SLAVE_EBI1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SDX65_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX65_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_memnoc_snoc = { + .name = "qns_memnoc_snoc", + .id = SDX65_SLAVE_MEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_MASTER_MEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_sys_pcie = { + .name = "qns_sys_pcie", + .id = SDX65_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_MASTER_MEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SDX65_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SDX65_SLAVE_APPSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_audio = { + .name = "qhs_audio", + .id = SDX65_SLAVE_AUDIO, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_blsp1 = { + .name = "qhs_blsp1", + .id = SDX65_SLAVE_BLSP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SDX65_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SDX65_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SDX65_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ecc_cfg = { + .name = "qhs_ecc_cfg", + .id = SDX65_SLAVE_ECC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SDX65_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SDX65_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SDX65_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_parf = { + .name = "qhs_pcie_parf", + .id = SDX65_SLAVE_PCIE_PARF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SDX65_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SDX65_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SDX65_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qpic = { + .name = "qhs_qpic", + .id = SDX65_SLAVE_QPIC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc1 = { + .name = "qhs_sdc1", + .id = SDX65_SLAVE_SDCC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SDX65_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SDX65_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spmi_fetcher = { + .name = "qhs_spmi_fetcher", + .id = SDX65_SLAVE_SPMI_FETCHER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spmi_vgi_coex = { + .name = "qhs_spmi_vgi_coex", + .id = SDX65_SLAVE_SPMI_VGI_COEX, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SDX65_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SDX65_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3 = { + .name = "qhs_usb3", + .id = SDX65_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_phy = { + .name = "qhs_usb3_phy", + .id = SDX65_SLAVE_USB3_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_aggre_noc = { + .name = "qns_aggre_noc", + .id = SDX65_SLAVE_ANOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SDX65_MASTER_ANOC_SNOC }, +}; + +static struct qcom_icc_node qns_snoc_memnoc = { + .name = "qns_snoc_memnoc", + .id = SDX65_SLAVE_SNOC_MEM_NOC_GC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SDX65_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SDX65_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SDX65_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie = { + .name = "xs_pcie", + .id = SDX65_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SDX65_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SDX65_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_pn0 = { + .name = "PN0", + .keepalive = true, + .num_nodes = 26, + .nodes = { &qhm_snoc_cfg, + &qhs_aoss, + &qhs_apss, + &qhs_audio, + &qhs_blsp1, + &qhs_clk_ctl, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_ecc_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mss_cfg, + &qhs_pcie_parf, + &qhs_pdm, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qpic, + &qhs_sdc1, + &qhs_snoc_cfg, + &qhs_spmi_fetcher, + &qhs_spmi_vgi_coex, + &qhs_tcsr, + &qhs_tlmm, + &qhs_usb3, + &qhs_usb3_phy, + &srvc_snoc + }, +}; + +static struct qcom_icc_bcm bcm_pn1 = { + .name = "PN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xm_sdc1 }, +}; + +static struct qcom_icc_bcm bcm_pn2 = { + .name = "PN2", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_audio, &qhm_spmi_fetcher1 }, +}; + +static struct qcom_icc_bcm bcm_pn3 = { + .name = "PN3", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_blsp1, &qhm_qpic }, +}; + +static struct qcom_icc_bcm bcm_pn4 = { + .name = "PN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 = { + .name = "SH1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_memnoc_snoc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xm_apps_rdwr }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_snoc_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_sys_tcu_cfg }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qhm_qdss_bam, &xm_qdss_etr }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .num_nodes = 4, + .nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_memnoc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_memnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qnm_ipa, &xm_ipa2pcie_slv }, +}; static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_mc0, diff --git a/drivers/interconnect/qcom/sm6350.c b/drivers/interconnect/qcom/sm6350.c index a3d46e59444e..49aed492e9b8 100644 --- a/drivers/interconnect/qcom/sm6350.c +++ b/drivers/interconnect/qcom/sm6350.c @@ -6,167 +6,1388 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sm6350.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sm6350.h" -DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32, SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAVE_QUP_CORE_0); -DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAVE_QUP_CORE_1); -DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_GEM_NOC); -DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); -DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAVE_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE_MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLAVE_LLCC); -DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM6350_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC, SM6350_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SNOC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SNOC_MAS); -DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4); -DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4); -DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4); -DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4); -DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NOC_CFG); -DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4); -DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SM6350_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup_0 = { + .name = "qhm_qup_0", + .id = SM6350_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emmc = { + .name = "xm_emmc", + .id = SM6350_MASTER_EMMC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM6350_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SM6350_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM6350_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup_1 = { + .name = "qhm_qup_1", + .id = SM6350_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM6350_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM6350_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM6350_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM6350_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM6350_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SM6350_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_icp_uncomp = { + .name = "qxm_camnoc_icp_uncomp", + .id = SM6350_MASTER_CAMNOC_ICP_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SM6350_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SM6350_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SM6350_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SM6350_MASTER_NPU, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qxm_npu_dsp = { + .name = "qxm_npu_dsp", + .id = SM6350_MASTER_NPU_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_CDSP_GEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SM6350_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 42, + .links = { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM6350_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 42, + .links = { SM6350_SLAVE_CAMERA_CFG, + SM6350_SLAVE_SDCC_2, + SM6350_SLAVE_CNOC_MNOC_CFG, + SM6350_SLAVE_UFS_MEM_CFG, + SM6350_SLAVE_QM_CFG, + SM6350_SLAVE_SNOC_CFG, + SM6350_SLAVE_QM_MPU_CFG, + SM6350_SLAVE_GLM, + SM6350_SLAVE_PDM, + SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6350_SLAVE_A2NOC_CFG, + SM6350_SLAVE_QDSS_CFG, + SM6350_SLAVE_VSENSE_CTRL_CFG, + SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6350_SLAVE_DISPLAY_CFG, + SM6350_SLAVE_TCSR, + SM6350_SLAVE_DCC_CFG, + SM6350_SLAVE_CNOC_DDRSS, + SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + SM6350_SLAVE_NPU_CFG, + SM6350_SLAVE_AHB2PHY, + SM6350_SLAVE_GRAPHICS_3D_CFG, + SM6350_SLAVE_BOOT_ROM, + SM6350_SLAVE_VENUS_CFG, + SM6350_SLAVE_IPA_CFG, + SM6350_SLAVE_SECURITY, + SM6350_SLAVE_IMEM_CFG, + SM6350_SLAVE_CNOC_MSS, + SM6350_SLAVE_SERVICE_CNOC, + SM6350_SLAVE_USB3, + SM6350_SLAVE_VENUS_THROTTLE_CFG, + SM6350_SLAVE_RBCPR_CX_CFG, + SM6350_SLAVE_A1NOC_CFG, + SM6350_SLAVE_AOSS, + SM6350_SLAVE_PRNG, + SM6350_SLAVE_EMMC_CFG, + SM6350_SLAVE_CRYPTO_0_CFG, + SM6350_SLAVE_PIMEM_CFG, + SM6350_SLAVE_RBCPR_MX_CFG, + SM6350_SLAVE_QUP_0, + SM6350_SLAVE_QUP_1, + SM6350_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SM6350_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC_CFG, + SM6350_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node acm_apps = { + .name = "acm_apps", + .id = SM6350_MASTER_AMPSS_M0, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu = { + .name = "acm_sys_tcu", + .id = SM6350_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SM6350_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SM6350_SLAVE_MCDMA_MS_MPU_CFG, + SM6350_SLAVE_SERVICE_GEM_NOC, + SM6350_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM6350_MASTER_COMPUTE_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM6350_MASTER_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM6350_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM6350_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM6350_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_gpu = { + .name = "qxm_gpu", + .id = SM6350_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM6350_SLAVE_LLCC, + SM6350_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM6350_MASTER_LLCC, + .channels = 2, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SM6350_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SM6350_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SM6350_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf = { + .name = "qxm_camnoc_hf", + .id = SM6350_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_icp = { + .name = "qxm_camnoc_icp", + .id = SM6350_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SM6350_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM6350_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys = { + .name = "amm_npu_sys", + .id = SM6350_MASTER_NPU_SYS, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_npu_cfg = { + .name = "qhm_npu_cfg", + .id = SM6350_MASTER_NPU_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 8, + .links = { SM6350_SLAVE_SERVICE_NPU_NOC, + SM6350_SLAVE_ISENSE_CFG, + SM6350_SLAVE_NPU_LLM_CFG, + SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM6350_SLAVE_NPU_CP, + SM6350_SLAVE_NPU_TCM, + SM6350_SLAVE_NPU_CAL_DP0, + SM6350_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SM6350_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM6350_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM6350_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 7, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_SF, + SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SM6350_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SM6350_SLAVE_PIMEM, + SM6350_SLAVE_OCIMEM, + SM6350_SLAVE_APPSS, + SM6350_SNOC_CNOC_SLV, + SM6350_SLAVE_TCU, + SM6350_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM6350_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC, + SM6350_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM6350_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM6350_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM6350_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM6350_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM6350_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SM6350_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SM6350_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SM6350_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cdsp_gemnoc = { + .name = "qns_cdsp_gemnoc", + .id = SM6350_SLAVE_CDSP_GEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SM6350_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SM6350_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SM6350_SLAVE_AHB2PHY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 = { + .name = "qhs_ahb2phy2", + .id = SM6350_SLAVE_AHB2PHY_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM6350_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_boot_rom = { + .name = "qhs_boot_rom", + .id = SM6350_SLAVE_BOOT_ROM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM6350_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { + .name = "qhs_camera_nrt_thrott_cfg", + .id = SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { + .name = "qhs_camera_rt_throttle_cfg", + .id = SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM6350_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM6350_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM6350_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM6350_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SM6350_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SM6350_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM6350_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg = { + .name = "qhs_display_throttle_cfg", + .id = SM6350_SLAVE_DISPLAY_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emmc_cfg = { + .name = "qhs_emmc_cfg", + .id = SM6350_SLAVE_EMMC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SM6350_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM6350_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM6350_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM6350_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SM6350_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SM6350_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SM6350_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SM6350_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM6350_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SM6350_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM6350_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_cfg = { + .name = "qhs_qm_cfg", + .id = SM6350_SLAVE_QM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg = { + .name = "qhs_qm_mpu_cfg", + .id = SM6350_SLAVE_QM_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SM6350_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SM6350_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM6350_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SM6350_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SM6350_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM6350_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM6350_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM6350_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM6350_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg = { + .name = "qhs_venus_throttle_cfg", + .id = SM6350_SLAVE_VENUS_THROTTLE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM6350_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM6350_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gemnoc = { + .name = "qhs_gemnoc", + .id = SM6350_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM6350_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM6350_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = { + .name = "qhs_mcdma_ms_mpu_cfg", + .id = SM6350_SLAVE_MCDMA_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SM6350_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM6350_SLAVE_LLCC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SM6350_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM6350_SLAVE_EBI_CH0, + .channels = 2, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM6350_SLAVE_MNOC_HF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SM6350_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM6350_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM6350_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 = { + .name = "qhs_cal_dp0", + .id = SM6350_SLAVE_NPU_CAL_DP0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cp = { + .name = "qhs_cp", + .id = SM6350_SLAVE_NPU_CP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon = { + .name = "qhs_dma_bwmon", + .id = SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dpm = { + .name = "qhs_dpm", + .id = SM6350_SLAVE_NPU_DPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_isense = { + .name = "qhs_isense", + .id = SM6350_SLAVE_ISENSE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llm = { + .name = "qhs_llm", + .id = SM6350_SLAVE_NPU_LLM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcm = { + .name = "qhs_tcm", + .id = SM6350_SLAVE_NPU_TCM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_npu_sys = { + .name = "qns_npu_sys", + .id = SM6350_SLAVE_NPU_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node srvc_noc = { + .name = "srvc_noc", + .id = SM6350_SLAVE_SERVICE_NPU_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM6350_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SM6350_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM6350_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM6350_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM6350_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM6350_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM6350_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM6350_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM6350_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM6350_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM6350_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 41, + .nodes = { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_aoss, + &qhs_boot_rom, + &qhs_camera_cfg, + &qhs_camera_nrt_thrott_cfg, + &qhs_camera_rt_throttle_cfg, + &qhs_clk_ctl, + &qhs_cpr_cx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_display_throttle_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_mss_cfg, + &qhs_npu_cfg, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qm_cfg, + &qhs_qm_mpu_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_security, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_venus_cfg, + &qhs_venus_throttle_cfg, + &qhs_vsense_ctrl_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .keepalive = false, + .num_nodes = 6, + .nodes = { &xm_emmc, + &xm_sdc2, + &qhs_ahb2phy2, + &qhs_emmc_cfg, + &qhs_pdm, + &qhs_sdc2 + }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_cdsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_co3 = { + .name = "CO3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_npu_dsp }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = true, + .num_nodes = 5, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_icp_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf, + &qxm_mdp0 + }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .num_nodes = 4, + .nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .num_nodes = 4, + .nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &acm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn10 = { + .name = "SN10", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_cn1, diff --git a/drivers/interconnect/qcom/sm8150.c b/drivers/interconnect/qcom/sm8150.c index c5ab29322164..c7c9cf7f746b 100644 --- a/drivers/interconnect/qcom/sm8150.c +++ b/drivers/interconnect/qcom/sm8150.c @@ -7,181 +7,1534 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sm8150.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sm8150.h" -DEFINE_QNODE(qhm_a1noc_cfg, SM8150_MASTER_A1NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qup0, SM8150_MASTER_QUP_0, 1, 4, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_emac, SM8150_MASTER_EMAC, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8150_MASTER_UFS_MEM, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM8150_MASTER_USB3, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8150_MASTER_USB3_1, 1, 8, SM8150_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8150_MASTER_A2NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8150_MASTER_QDSS_BAM, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qspi, SM8150_MASTER_QSPI, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8150_MASTER_QUP_1, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8150_MASTER_QUP_2, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_sensorss_ahb, SM8150_MASTER_SENSORS_AHB, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8150_MASTER_TSIF, 1, 4, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8150_MASTER_CNOC_A2NOC, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM8150_MASTER_CRYPTO_CORE_0, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8150_MASTER_IPA, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8150_MASTER_PCIE, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8150_MASTER_PCIE_1, 1, 8, SM8150_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8150_MASTER_QDSS_ETR, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc2, SM8150_MASTER_SDCC_2, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc4, SM8150_MASTER_SDCC_4, 1, 8, SM8150_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM8150_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SM8150_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM8150_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM8150_SLAVE_CAMNOC_UNCOMP); -DEFINE_QNODE(qnm_npu, SM8150_MASTER_NPU, 1, 32, SM8150_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qhm_spdm, SM8150_MASTER_SPDM, 1, 4, SM8150_SLAVE_CNOC_A2NOC); -DEFINE_QNODE(qnm_snoc, SM8150_SNOC_CNOC_MAS, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG); -DEFINE_QNODE(xm_qdss_dap, SM8150_MASTER_QDSS_DAP, 1, 8, SM8150_SLAVE_TLMM_SOUTH, SM8150_SLAVE_CDSP_CFG, SM8150_SLAVE_SPSS_CFG, SM8150_SLAVE_CAMERA_CFG, SM8150_SLAVE_SDCC_4, SM8150_SLAVE_SDCC_2, SM8150_SLAVE_CNOC_MNOC_CFG, SM8150_SLAVE_EMAC_CFG, SM8150_SLAVE_UFS_MEM_CFG, SM8150_SLAVE_TLMM_EAST, SM8150_SLAVE_SSC_CFG, SM8150_SLAVE_SNOC_CFG, SM8150_SLAVE_NORTH_PHY_CFG, SM8150_SLAVE_QUP_0, SM8150_SLAVE_GLM, SM8150_SLAVE_PCIE_1_CFG, SM8150_SLAVE_A2NOC_CFG, SM8150_SLAVE_QDSS_CFG, SM8150_SLAVE_DISPLAY_CFG, SM8150_SLAVE_TCSR, SM8150_SLAVE_CNOC_DDRSS, SM8150_SLAVE_CNOC_A2NOC, SM8150_SLAVE_RBCPR_MMCX_CFG, SM8150_SLAVE_NPU_CFG, SM8150_SLAVE_PCIE_0_CFG, SM8150_SLAVE_GRAPHICS_3D_CFG, SM8150_SLAVE_VENUS_CFG, SM8150_SLAVE_TSIF, SM8150_SLAVE_IPA_CFG, SM8150_SLAVE_CLK_CTL, SM8150_SLAVE_AOP, SM8150_SLAVE_QUP_1, SM8150_SLAVE_AHB2PHY_SOUTH, SM8150_SLAVE_USB3_1, SM8150_SLAVE_SERVICE_CNOC, SM8150_SLAVE_UFS_CARD_CFG, SM8150_SLAVE_QUP_2, SM8150_SLAVE_RBCPR_CX_CFG, SM8150_SLAVE_TLMM_WEST, SM8150_SLAVE_A1NOC_CFG, SM8150_SLAVE_AOSS, SM8150_SLAVE_PRNG, SM8150_SLAVE_VSENSE_CTRL_CFG, SM8150_SLAVE_QSPI, SM8150_SLAVE_USB3, SM8150_SLAVE_SPDM_WRAPPER, SM8150_SLAVE_CRYPTO_0_CFG, SM8150_SLAVE_PIMEM_CFG, SM8150_SLAVE_TLMM_NORTH, SM8150_SLAVE_RBCPR_MX_CFG, SM8150_SLAVE_IMEM_CFG); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8150_MASTER_CNOC_DC_NOC, 1, 4, SM8150_SLAVE_GEM_NOC_CFG, SM8150_SLAVE_LLCC_CFG); -DEFINE_QNODE(acm_apps, SM8150_MASTER_AMPSS_M0, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_gpu_tcu, SM8150_MASTER_GPU_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(acm_sys_tcu, SM8150_MASTER_SYS_TCU, 1, 8, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8150_MASTER_GEM_NOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_GEM_NOC, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG); -DEFINE_QNODE(qnm_cmpnoc, SM8150_MASTER_COMPUTE_NOC, 2, 32, SM8150_SLAVE_ECC, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8150_MASTER_GRAPHICS_3D, 2, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8150_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8150_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8150_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8150_MASTER_GEM_NOC_PCIE_SNOC, 1, 16, SM8150_SLAVE_LLCC, SM8150_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8150_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8150_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8150_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8150_SLAVE_LLCC); -DEFINE_QNODE(qxm_ecc, SM8150_MASTER_ECC, 2, 32, SM8150_SLAVE_LLCC); -DEFINE_QNODE(llcc_mc, SM8150_MASTER_LLCC, 4, 4, SM8150_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8150_MASTER_CNOC_MNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qxm_camnoc_hf0, SM8150_MASTER_CAMNOC_HF0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_hf1, SM8150_MASTER_CAMNOC_HF1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_camnoc_sf, SM8150_MASTER_CAMNOC_SF, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8150_MASTER_MDP_PORT0, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8150_MASTER_MDP_PORT1, 1, 32, SM8150_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8150_MASTER_ROTATOR, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus0, SM8150_MASTER_VIDEO_P0, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus1, SM8150_MASTER_VIDEO_P1, 1, 32, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_venus_arm9, SM8150_MASTER_VIDEO_PROC, 1, 8, SM8150_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_snoc_cfg, SM8150_MASTER_SNOC_CFG, 1, 4, SM8150_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8150_A1NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_aggre2_noc, SM8150_A2NOC_SNOC_MAS, 1, 16, SM8150_SLAVE_SNOC_GEM_NOC_SF, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_PCIE_0, SM8150_SLAVE_PCIE_1, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc, SM8150_MASTER_GEM_NOC_SNOC, 1, 8, SM8150_SLAVE_PIMEM, SM8150_SLAVE_OCIMEM, SM8150_SLAVE_APPSS, SM8150_SNOC_CNOC_SLV, SM8150_SLAVE_TCU, SM8150_SLAVE_QDSS_STM); -DEFINE_QNODE(qxm_pimem, SM8150_MASTER_PIMEM, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(xm_gic, SM8150_MASTER_GIC, 1, 8, SM8150_SLAVE_SNOC_GEM_NOC_GC, SM8150_SLAVE_OCIMEM); -DEFINE_QNODE(qns_a1noc_snoc, SM8150_A1NOC_SNOC_SLV, 1, 16, SM8150_A1NOC_SNOC_MAS); -DEFINE_QNODE(srvc_aggre1_noc, SM8150_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8150_A2NOC_SNOC_SLV, 1, 16, SM8150_A2NOC_SNOC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8150_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8150_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8150_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_camnoc_uncomp, SM8150_SLAVE_CAMNOC_UNCOMP, 1, 32); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8150_SLAVE_CDSP_MEM_NOC, 2, 32, SM8150_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8150_SLAVE_A1NOC_CFG, 1, 4, SM8150_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8150_SLAVE_A2NOC_CFG, 1, 4, SM8150_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy_south, SM8150_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_aop, SM8150_SLAVE_AOP, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8150_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8150_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8150_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8150_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8150_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8150_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8150_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8150_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8150_SLAVE_CNOC_DDRSS, 1, 4, SM8150_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8150_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_emac_cfg, SM8150_SLAVE_EMAC_CFG, 1, 4); -DEFINE_QNODE(qhs_glm, SM8150_SLAVE_GLM, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8150_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8150_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8150_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8150_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8150_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8150_SLAVE_NPU_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie0_cfg, SM8150_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8150_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_phy_refgen_north, SM8150_SLAVE_NORTH_PHY_CFG, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8150_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8150_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8150_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8150_SLAVE_QSPI, 1, 4); -DEFINE_QNODE(qhs_qupv3_east, SM8150_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_qupv3_north, SM8150_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qupv3_south, SM8150_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8150_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8150_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8150_SLAVE_SNOC_CFG, 1, 4, SM8150_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_spdm, SM8150_SLAVE_SPDM_WRAPPER, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SM8150_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_ssc_cfg, SM8150_SLAVE_SSC_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SM8150_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm_east, SM8150_SLAVE_TLMM_EAST, 1, 4); -DEFINE_QNODE(qhs_tlmm_north, SM8150_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_south, SM8150_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm_west, SM8150_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8150_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8150_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8150_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8150_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8150_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8150_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8150_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8150_SLAVE_CNOC_A2NOC, 1, 8, SM8150_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8150_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8150_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8150_SLAVE_GEM_NOC_CFG, 1, 4, SM8150_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_ecc, SM8150_SLAVE_ECC, 1, 32); -DEFINE_QNODE(qns_gem_noc_snoc, SM8150_SLAVE_GEM_NOC_SNOC, 1, 8, SM8150_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8150_SLAVE_LLCC, 4, 16, SM8150_MASTER_LLCC); -DEFINE_QNODE(srvc_gemnoc, SM8150_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8150_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns2_mem_noc, SM8150_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM8150_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_hf, SM8150_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8150_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8150_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8150_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8150_SNOC_CNOC_SLV, 1, 8, SM8150_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8150_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8150_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8150_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8150_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8150_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8150_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8150_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8150_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8150_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8150_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8150_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_gem_noc_snoc); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qxm_camnoc_sf, &qns2_mem_noc); -DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_gpu_tcu, &acm_sys_tcu); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); -DEFINE_QBCM(bcm_sh4, "SH4", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh5, "SH5", false, &acm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_co1, "CO1", false, &qnm_npu); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy_south, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emac_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_phy_refgen_north, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qupv3_east, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_spss_cfg, &qhs_ssc_cfg, &qhs_tcsr, &qhs_tlmm_east, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tlmm_west, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup0, &qhm_qup1, &qhm_qup2); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc); -DEFINE_QBCM(bcm_sn4, "SN4", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn8, "SN8", false, &xs_pcie_0, &xs_pcie_1); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qxm_pimem, &xm_gic); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); -DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_gemnoc); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SM8150_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SM8150_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_emac = { + .name = "xm_emac", + .id = SM8150_MASTER_EMAC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM8150_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM8150_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SM8150_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SM8150_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM8150_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SM8150_MASTER_QSPI, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SM8150_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SM8150_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_sensorss_ahb = { + .name = "qhm_sensorss_ahb", + .id = SM8150_MASTER_SENSORS_AHB, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SM8150_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SM8150_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM8150_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM8150_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SM8150_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SM8150_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM8150_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM8150_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SM8150_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { + .name = "qxm_camnoc_hf0_uncomp", + .id = SM8150_MASTER_CAMNOC_HF0_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { + .name = "qxm_camnoc_hf1_uncomp", + .id = SM8150_MASTER_CAMNOC_HF1_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qxm_camnoc_sf_uncomp = { + .name = "qxm_camnoc_sf_uncomp", + .id = SM8150_MASTER_CAMNOC_SF_UNCOMP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CAMNOC_UNCOMP }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SM8150_MASTER_NPU, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_spdm = { + .name = "qhm_spdm", + .id = SM8150_MASTER_SPDM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_CNOC_A2NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SM8150_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 50, + .links = { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM8150_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 51, + .links = { SM8150_SLAVE_TLMM_SOUTH, + SM8150_SLAVE_CDSP_CFG, + SM8150_SLAVE_SPSS_CFG, + SM8150_SLAVE_CAMERA_CFG, + SM8150_SLAVE_SDCC_4, + SM8150_SLAVE_SDCC_2, + SM8150_SLAVE_CNOC_MNOC_CFG, + SM8150_SLAVE_EMAC_CFG, + SM8150_SLAVE_UFS_MEM_CFG, + SM8150_SLAVE_TLMM_EAST, + SM8150_SLAVE_SSC_CFG, + SM8150_SLAVE_SNOC_CFG, + SM8150_SLAVE_NORTH_PHY_CFG, + SM8150_SLAVE_QUP_0, + SM8150_SLAVE_GLM, + SM8150_SLAVE_PCIE_1_CFG, + SM8150_SLAVE_A2NOC_CFG, + SM8150_SLAVE_QDSS_CFG, + SM8150_SLAVE_DISPLAY_CFG, + SM8150_SLAVE_TCSR, + SM8150_SLAVE_CNOC_DDRSS, + SM8150_SLAVE_CNOC_A2NOC, + SM8150_SLAVE_RBCPR_MMCX_CFG, + SM8150_SLAVE_NPU_CFG, + SM8150_SLAVE_PCIE_0_CFG, + SM8150_SLAVE_GRAPHICS_3D_CFG, + SM8150_SLAVE_VENUS_CFG, + SM8150_SLAVE_TSIF, + SM8150_SLAVE_IPA_CFG, + SM8150_SLAVE_CLK_CTL, + SM8150_SLAVE_AOP, + SM8150_SLAVE_QUP_1, + SM8150_SLAVE_AHB2PHY_SOUTH, + SM8150_SLAVE_USB3_1, + SM8150_SLAVE_SERVICE_CNOC, + SM8150_SLAVE_UFS_CARD_CFG, + SM8150_SLAVE_QUP_2, + SM8150_SLAVE_RBCPR_CX_CFG, + SM8150_SLAVE_TLMM_WEST, + SM8150_SLAVE_A1NOC_CFG, + SM8150_SLAVE_AOSS, + SM8150_SLAVE_PRNG, + SM8150_SLAVE_VSENSE_CTRL_CFG, + SM8150_SLAVE_QSPI, + SM8150_SLAVE_USB3, + SM8150_SLAVE_SPDM_WRAPPER, + SM8150_SLAVE_CRYPTO_0_CFG, + SM8150_SLAVE_PIMEM_CFG, + SM8150_SLAVE_TLMM_NORTH, + SM8150_SLAVE_RBCPR_MX_CFG, + SM8150_SLAVE_IMEM_CFG + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SM8150_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8150_SLAVE_GEM_NOC_CFG, + SM8150_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node acm_apps = { + .name = "acm_apps", + .id = SM8150_MASTER_AMPSS_M0, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_gpu_tcu = { + .name = "acm_gpu_tcu", + .id = SM8150_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node acm_sys_tcu = { + .name = "acm_sys_tcu", + .id = SM8150_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SM8150_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8150_SLAVE_SERVICE_GEM_NOC, + SM8150_SLAVE_MSS_PROC_MS_MPU_CFG + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM8150_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8150_SLAVE_ECC, + SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SM8150_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM8150_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM8150_MASTER_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SM8150_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM8150_SLAVE_LLCC, + SM8150_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM8150_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM8150_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qxm_ecc = { + .name = "qxm_ecc", + .id = SM8150_MASTER_ECC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_LLCC }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM8150_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SM8150_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf0 = { + .name = "qxm_camnoc_hf0", + .id = SM8150_MASTER_CAMNOC_HF0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_hf1 = { + .name = "qxm_camnoc_hf1", + .id = SM8150_MASTER_CAMNOC_HF1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_camnoc_sf = { + .name = "qxm_camnoc_sf", + .id = SM8150_MASTER_CAMNOC_SF, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM8150_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SM8150_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SM8150_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus0 = { + .name = "qxm_venus0", + .id = SM8150_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus1 = { + .name = "qxm_venus1", + .id = SM8150_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_venus_arm9 = { + .name = "qxm_venus_arm9", + .id = SM8150_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SM8150_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM8150_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM8150_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 9, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_SF, + SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_PCIE_0, + SM8150_SLAVE_PCIE_1, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SM8150_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 6, + .links = { SM8150_SLAVE_PIMEM, + SM8150_SLAVE_OCIMEM, + SM8150_SLAVE_APPSS, + SM8150_SNOC_CNOC_SLV, + SM8150_SLAVE_TCU, + SM8150_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM8150_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM8150_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8150_SLAVE_SNOC_GEM_NOC_GC, + SM8150_SLAVE_OCIMEM + }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM8150_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM8150_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM8150_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SM8150_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM8150_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_camnoc_uncomp = { + .name = "qns_camnoc_uncomp", + .id = SM8150_SLAVE_CAMNOC_UNCOMP, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc = { + .name = "qns_cdsp_mem_noc", + .id = SM8150_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SM8150_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SM8150_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy_south = { + .name = "qhs_ahb2phy_south", + .id = SM8150_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aop = { + .name = "qhs_aop", + .id = SM8150_SLAVE_AOP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM8150_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM8150_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM8150_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp = { + .name = "qhs_compute_dsp", + .id = SM8150_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM8150_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SM8150_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM8150_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM8150_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SM8150_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM8150_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_emac_cfg = { + .name = "qhs_emac_cfg", + .id = SM8150_SLAVE_EMAC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_glm = { + .name = "qhs_glm", + .id = SM8150_SLAVE_GLM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM8150_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM8150_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM8150_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SM8150_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SM8150_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SM8150_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SM8150_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_phy_refgen_north = { + .name = "qhs_phy_refgen_north", + .id = SM8150_SLAVE_NORTH_PHY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM8150_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SM8150_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM8150_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SM8150_SLAVE_QSPI, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_east = { + .name = "qhs_qupv3_east", + .id = SM8150_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_north = { + .name = "qhs_qupv3_north", + .id = SM8150_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qupv3_south = { + .name = "qhs_qupv3_south", + .id = SM8150_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM8150_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SM8150_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SM8150_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_spdm = { + .name = "qhs_spdm", + .id = SM8150_SLAVE_SPDM_WRAPPER, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SM8150_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ssc_cfg = { + .name = "qhs_ssc_cfg", + .id = SM8150_SLAVE_SSC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM8150_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_east = { + .name = "qhs_tlmm_east", + .id = SM8150_SLAVE_TLMM_EAST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_north = { + .name = "qhs_tlmm_north", + .id = SM8150_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_south = { + .name = "qhs_tlmm_south", + .id = SM8150_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm_west = { + .name = "qhs_tlmm_west", + .id = SM8150_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SM8150_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SM8150_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM8150_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM8150_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SM8150_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM8150_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM8150_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SM8150_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM8150_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM8150_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SM8150_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8150_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SM8150_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ecc = { + .name = "qns_ecc", + .id = SM8150_SLAVE_ECC, + .channels = 1, + .buswidth = 32, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SM8150_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM8150_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_MASTER_LLCC }, +}; + +static struct qcom_icc_node srvc_gemnoc = { + .name = "srvc_gemnoc", + .id = SM8150_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM8150_SLAVE_EBI_CH0, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns2_mem_noc = { + .name = "qns2_mem_noc", + .id = SM8150_SLAVE_MNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM8150_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8150_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM8150_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM8150_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SM8150_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM8150_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8150_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM8150_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8150_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM8150_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM8150_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM8150_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SM8150_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SM8150_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM8150_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM8150_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .num_nodes = 7, + .nodes = { &qxm_camnoc_hf0_uncomp, + &qxm_camnoc_hf1_uncomp, + &qxm_camnoc_sf_uncomp, + &qxm_camnoc_hf0, + &qxm_camnoc_hf1, + &qxm_mdp0, + &qxm_mdp1 + }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_gem_noc_snoc }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 2, + .nodes = { &acm_gpu_tcu, &acm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .num_nodes = 4, + .nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh5 = { + .name = "SH5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &acm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_cdsp_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_co1 = { + .name = "CO1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 53, + .nodes = { &qhm_spdm, + &qnm_snoc, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy_south, + &qhs_aop, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_emac_cfg, + &qhs_glm, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_mnoc_cfg, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_phy_refgen_north, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qupv3_east, + &qhs_qupv3_north, + &qhs_qupv3_south, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_spdm, + &qhs_spss_cfg, + &qhs_ssc_cfg, + &qhs_tcsr, + &qhs_tlmm_east, + &qhs_tlmm_north, + &qhs_tlmm_south, + &qhs_tlmm_west, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .num_nodes = 3, + .nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2 }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 3, + .nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .num_nodes = 2, + .nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qxm_pimem, &xm_gic }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_sn15 = { + .name = "SN15", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_qup0, diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index e3bb008cb219..d4a4ecef11f0 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -7,193 +7,1636 @@ #include <linux/device.h> #include <linux/interconnect.h> #include <linux/interconnect-provider.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sm8250.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sm8250.h" -DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup1, SM8250_MASTER_QUP_1, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup2, SM8250_MASTER_QUP_2, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_tsif, SM8250_MASTER_TSIF, 1, 4, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_modem, SM8250_MASTER_PCIE_2, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1); -DEFINE_QNODE(xm_sdc4, SM8250_MASTER_SDCC_4, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_mem, SM8250_MASTER_UFS_MEM, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_0, SM8250_MASTER_USB3, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(xm_usb3_1, SM8250_MASTER_USB3_1, 1, 8, SM8250_A1NOC_SNOC_SLV); -DEFINE_QNODE(qhm_a2noc_cfg, SM8250_MASTER_A2NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qhm_qdss_bam, SM8250_MASTER_QDSS_BAM, 1, 4, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qhm_qup0, SM8250_MASTER_QUP_0, 1, 4, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_cnoc, SM8250_MASTER_CNOC_A2NOC, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_crypto, SM8250_MASTER_CRYPTO_CORE_0, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qxm_ipa, SM8250_MASTER_IPA, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_pcie3_0, SM8250_MASTER_PCIE, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8250_MASTER_PCIE_1, 1, 8, SM8250_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8250_MASTER_QDSS_ETR, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_sdc2, SM8250_MASTER_SDCC_2, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(xm_ufs_card, SM8250_MASTER_UFS_CARD, 1, 8, SM8250_A2NOC_SNOC_SLV); -DEFINE_QNODE(qnm_npu, SM8250_MASTER_NPU, 2, 32, SM8250_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qnm_snoc, SM8250_SNOC_CNOC_MAS, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(xm_qdss_dap, SM8250_MASTER_QDSS_DAP, 1, 8, SM8250_SLAVE_CDSP_CFG, SM8250_SLAVE_CAMERA_CFG, SM8250_SLAVE_TLMM_SOUTH, SM8250_SLAVE_TLMM_NORTH, SM8250_SLAVE_SDCC_4, SM8250_SLAVE_TLMM_WEST, SM8250_SLAVE_SDCC_2, SM8250_SLAVE_CNOC_MNOC_CFG, SM8250_SLAVE_UFS_MEM_CFG, SM8250_SLAVE_SNOC_CFG, SM8250_SLAVE_PDM, SM8250_SLAVE_CX_RDPM, SM8250_SLAVE_PCIE_1_CFG, SM8250_SLAVE_A2NOC_CFG, SM8250_SLAVE_QDSS_CFG, SM8250_SLAVE_DISPLAY_CFG, SM8250_SLAVE_PCIE_2_CFG, SM8250_SLAVE_TCSR, SM8250_SLAVE_DCC_CFG, SM8250_SLAVE_CNOC_DDRSS, SM8250_SLAVE_IPC_ROUTER_CFG, SM8250_SLAVE_CNOC_A2NOC, SM8250_SLAVE_PCIE_0_CFG, SM8250_SLAVE_RBCPR_MMCX_CFG, SM8250_SLAVE_NPU_CFG, SM8250_SLAVE_AHB2PHY_SOUTH, SM8250_SLAVE_AHB2PHY_NORTH, SM8250_SLAVE_GRAPHICS_3D_CFG, SM8250_SLAVE_VENUS_CFG, SM8250_SLAVE_TSIF, SM8250_SLAVE_IPA_CFG, SM8250_SLAVE_IMEM_CFG, SM8250_SLAVE_USB3, SM8250_SLAVE_SERVICE_CNOC, SM8250_SLAVE_UFS_CARD_CFG, SM8250_SLAVE_USB3_1, SM8250_SLAVE_LPASS, SM8250_SLAVE_RBCPR_CX_CFG, SM8250_SLAVE_A1NOC_CFG, SM8250_SLAVE_AOSS, SM8250_SLAVE_PRNG, SM8250_SLAVE_VSENSE_CTRL_CFG, SM8250_SLAVE_QSPI_0, SM8250_SLAVE_CRYPTO_0_CFG, SM8250_SLAVE_PIMEM_CFG, SM8250_SLAVE_RBCPR_MX_CFG, SM8250_SLAVE_QUP_0, SM8250_SLAVE_QUP_1, SM8250_SLAVE_QUP_2, SM8250_SLAVE_CLK_CTL); -DEFINE_QNODE(qhm_cnoc_dc_noc, SM8250_MASTER_CNOC_DC_NOC, 1, 4, SM8250_SLAVE_GEM_NOC_CFG, SM8250_SLAVE_LLCC_CFG); -DEFINE_QNODE(alm_gpu_tcu, SM8250_MASTER_GPU_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(alm_sys_tcu, SM8250_MASTER_SYS_TCU, 1, 8, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(chm_apps, SM8250_MASTER_AMPSS_M0, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_gemnoc_cfg, SM8250_MASTER_GEM_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_GEM_NOC_2, SM8250_SLAVE_SERVICE_GEM_NOC_1, SM8250_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_cmpnoc, SM8250_MASTER_COMPUTE_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_gpu, SM8250_MASTER_GRAPHICS_3D, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_mnoc_hf, SM8250_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8250_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_pcie, SM8250_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC); -DEFINE_QNODE(qnm_snoc_gc, SM8250_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8250_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8250_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8250_SLAVE_LLCC, SM8250_SLAVE_GEM_NOC_SNOC, SM8250_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(llcc_mc, SM8250_MASTER_LLCC, 4, 4, SM8250_SLAVE_EBI_CH0); -DEFINE_QNODE(qhm_mnoc_cfg, SM8250_MASTER_CNOC_MNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qnm_camnoc_hf, SM8250_MASTER_CAMNOC_HF, 2, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, SM8250_MASTER_CAMNOC_ICP, 1, 8, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, SM8250_MASTER_CAMNOC_SF, 2, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video0, SM8250_MASTER_VIDEO_P0, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, SM8250_MASTER_VIDEO_P1, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM8250_MASTER_VIDEO_PROC, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8250_MASTER_MDP_PORT0, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8250_MASTER_MDP_PORT1, 1, 32, SM8250_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8250_MASTER_ROTATOR, 1, 32, SM8250_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(amm_npu_sys, SM8250_MASTER_NPU_SYS, 4, 32, SM8250_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(amm_npu_sys_cdp_w, SM8250_MASTER_NPU_CDP, 2, 16, SM8250_SLAVE_NPU_COMPUTE_NOC); -DEFINE_QNODE(qhm_cfg, SM8250_MASTER_NPU_NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_NPU_NOC, SM8250_SLAVE_ISENSE_CFG, SM8250_SLAVE_NPU_LLM_CFG, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, SM8250_SLAVE_NPU_CP, SM8250_SLAVE_NPU_TCM, SM8250_SLAVE_NPU_CAL_DP0, SM8250_SLAVE_NPU_CAL_DP1, SM8250_SLAVE_NPU_DPM); -DEFINE_QNODE(qhm_snoc_cfg, SM8250_MASTER_SNOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8250_A1NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, SM8250_A2NOC_SNOC_MAS, 1, 16, SM8250_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_gemnoc, SM8250_MASTER_GEM_NOC_SNOC, 1, 16, SM8250_SLAVE_PIMEM, SM8250_SLAVE_OCIMEM, SM8250_SLAVE_APPSS, SM8250_SNOC_CNOC_SLV, SM8250_SLAVE_TCU, SM8250_SLAVE_QDSS_STM); -DEFINE_QNODE(qnm_gemnoc_pcie, SM8250_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8250_SLAVE_PCIE_2, SM8250_SLAVE_PCIE_0, SM8250_SLAVE_PCIE_1); -DEFINE_QNODE(qxm_pimem, SM8250_MASTER_PIMEM, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(xm_gic, SM8250_MASTER_GIC, 1, 8, SM8250_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(qns_a1noc_snoc, SM8250_A1NOC_SNOC_SLV, 1, 16, SM8250_A1NOC_SNOC_MAS); -DEFINE_QNODE(qns_pcie_modem_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre1_noc, SM8250_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8250_A2NOC_SNOC_SLV, 1, 16, SM8250_A2NOC_SNOC_MAS); -DEFINE_QNODE(qns_pcie_mem_noc, SM8250_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8250_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8250_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qns_cdsp_mem_noc, SM8250_SLAVE_CDSP_MEM_NOC, 2, 32, SM8250_MASTER_COMPUTE_NOC); -DEFINE_QNODE(qhs_a1_noc_cfg, SM8250_SLAVE_A1NOC_CFG, 1, 4, SM8250_MASTER_A1NOC_CFG); -DEFINE_QNODE(qhs_a2_noc_cfg, SM8250_SLAVE_A2NOC_CFG, 1, 4, SM8250_MASTER_A2NOC_CFG); -DEFINE_QNODE(qhs_ahb2phy0, SM8250_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy1, SM8250_SLAVE_AHB2PHY_NORTH, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8250_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_camera_cfg, SM8250_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8250_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_dsp, SM8250_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8250_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8250_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8250_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8250_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_cx_rdpm, SM8250_SLAVE_CX_RDPM, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM8250_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_ddrss_cfg, SM8250_SLAVE_CNOC_DDRSS, 1, 4, SM8250_MASTER_CNOC_DC_NOC); -DEFINE_QNODE(qhs_display_cfg, SM8250_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8250_SLAVE_GRAPHICS_3D_CFG, 1, 8); -DEFINE_QNODE(qhs_imem_cfg, SM8250_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8250_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_ipc_router, SM8250_SLAVE_IPC_ROUTER_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_cfg, SM8250_SLAVE_LPASS, 1, 4); -DEFINE_QNODE(qhs_mnoc_cfg, SM8250_SLAVE_CNOC_MNOC_CFG, 1, 4, SM8250_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(qhs_npu_cfg, SM8250_SLAVE_NPU_CFG, 1, 4, SM8250_MASTER_NPU_NOC_CFG); -DEFINE_QNODE(qhs_pcie0_cfg, SM8250_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8250_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie_modem_cfg, SM8250_SLAVE_PCIE_2_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SM8250_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8250_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_prng, SM8250_SLAVE_PRNG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8250_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8250_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SM8250_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM8250_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qup2, SM8250_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8250_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8250_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_snoc_cfg, SM8250_SLAVE_SNOC_CFG, 1, 4, SM8250_MASTER_SNOC_CFG); -DEFINE_QNODE(qhs_tcsr, SM8250_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm0, SM8250_SLAVE_TLMM_NORTH, 1, 4); -DEFINE_QNODE(qhs_tlmm1, SM8250_SLAVE_TLMM_SOUTH, 1, 4); -DEFINE_QNODE(qhs_tlmm2, SM8250_SLAVE_TLMM_WEST, 1, 4); -DEFINE_QNODE(qhs_tsif, SM8250_SLAVE_TSIF, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8250_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8250_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8250_SLAVE_USB3, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8250_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8250_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8250_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_cnoc_a2noc, SM8250_SLAVE_CNOC_A2NOC, 1, 8, SM8250_MASTER_CNOC_A2NOC); -DEFINE_QNODE(srvc_cnoc, SM8250_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(qhs_llcc, SM8250_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qhs_memnoc, SM8250_SLAVE_GEM_NOC_CFG, 1, 4, SM8250_MASTER_GEM_NOC_CFG); -DEFINE_QNODE(qns_gem_noc_snoc, SM8250_SLAVE_GEM_NOC_SNOC, 1, 16, SM8250_MASTER_GEM_NOC_SNOC); -DEFINE_QNODE(qns_llcc, SM8250_SLAVE_LLCC, 4, 16, SM8250_MASTER_LLCC); -DEFINE_QNODE(qns_sys_pcie, SM8250_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SM8250_MASTER_GEM_NOC_PCIE_SNOC); -DEFINE_QNODE(srvc_even_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(srvc_odd_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC_2, 1, 4); -DEFINE_QNODE(srvc_sys_gemnoc, SM8250_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8250_SLAVE_EBI_CH0, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM8250_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM8250_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8250_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8250_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qhs_cal_dp0, SM8250_SLAVE_NPU_CAL_DP0, 1, 4); -DEFINE_QNODE(qhs_cal_dp1, SM8250_SLAVE_NPU_CAL_DP1, 1, 4); -DEFINE_QNODE(qhs_cp, SM8250_SLAVE_NPU_CP, 1, 4); -DEFINE_QNODE(qhs_dma_bwmon, SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); -DEFINE_QNODE(qhs_dpm, SM8250_SLAVE_NPU_DPM, 1, 4); -DEFINE_QNODE(qhs_isense, SM8250_SLAVE_ISENSE_CFG, 1, 4); -DEFINE_QNODE(qhs_llm, SM8250_SLAVE_NPU_LLM_CFG, 1, 4); -DEFINE_QNODE(qhs_tcm, SM8250_SLAVE_NPU_TCM, 1, 4); -DEFINE_QNODE(qns_npu_sys, SM8250_SLAVE_NPU_COMPUTE_NOC, 2, 32); -DEFINE_QNODE(srvc_noc, SM8250_SLAVE_SERVICE_NPU_NOC, 1, 4); -DEFINE_QNODE(qhs_apss, SM8250_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qns_cnoc, SM8250_SNOC_CNOC_SLV, 1, 8, SM8250_SNOC_CNOC_MAS); -DEFINE_QNODE(qns_gemnoc_gc, SM8250_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8250_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8250_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8250_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(qxs_imem, SM8250_SLAVE_OCIMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8); - -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); -DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp); -DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); -DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_pcie_modem); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie); -DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc); -DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc); +static struct qcom_icc_node qhm_a1noc_cfg = { + .name = "qhm_a1noc_cfg", + .id = SM8250_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SM8250_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SM8250_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SM8250_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_tsif = { + .name = "qhm_tsif", + .id = SM8250_MASTER_TSIF, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_modem = { + .name = "xm_pcie3_modem", + .id = SM8250_MASTER_PCIE_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SM8250_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM8250_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM8250_MASTER_USB3, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SM8250_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_a2noc_cfg = { + .name = "qhm_a2noc_cfg", + .id = SM8250_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM8250_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SM8250_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_cnoc = { + .name = "qnm_cnoc", + .id = SM8250_MASTER_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM8250_MASTER_CRYPTO_CORE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM8250_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SM8250_MASTER_PCIE, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SM8250_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM8250_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM8250_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SM8250_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_SLV }, +}; + +static struct qcom_icc_node qnm_npu = { + .name = "qnm_npu", + .id = SM8250_MASTER_NPU, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_snoc = { + .name = "qnm_snoc", + .id = SM8250_SNOC_CNOC_MAS, + .channels = 1, + .buswidth = 8, + .num_links = 49, + .links = { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM8250_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 50, + .links = { SM8250_SLAVE_CDSP_CFG, + SM8250_SLAVE_CAMERA_CFG, + SM8250_SLAVE_TLMM_SOUTH, + SM8250_SLAVE_TLMM_NORTH, + SM8250_SLAVE_SDCC_4, + SM8250_SLAVE_TLMM_WEST, + SM8250_SLAVE_SDCC_2, + SM8250_SLAVE_CNOC_MNOC_CFG, + SM8250_SLAVE_UFS_MEM_CFG, + SM8250_SLAVE_SNOC_CFG, + SM8250_SLAVE_PDM, + SM8250_SLAVE_CX_RDPM, + SM8250_SLAVE_PCIE_1_CFG, + SM8250_SLAVE_A2NOC_CFG, + SM8250_SLAVE_QDSS_CFG, + SM8250_SLAVE_DISPLAY_CFG, + SM8250_SLAVE_PCIE_2_CFG, + SM8250_SLAVE_TCSR, + SM8250_SLAVE_DCC_CFG, + SM8250_SLAVE_CNOC_DDRSS, + SM8250_SLAVE_IPC_ROUTER_CFG, + SM8250_SLAVE_CNOC_A2NOC, + SM8250_SLAVE_PCIE_0_CFG, + SM8250_SLAVE_RBCPR_MMCX_CFG, + SM8250_SLAVE_NPU_CFG, + SM8250_SLAVE_AHB2PHY_SOUTH, + SM8250_SLAVE_AHB2PHY_NORTH, + SM8250_SLAVE_GRAPHICS_3D_CFG, + SM8250_SLAVE_VENUS_CFG, + SM8250_SLAVE_TSIF, + SM8250_SLAVE_IPA_CFG, + SM8250_SLAVE_IMEM_CFG, + SM8250_SLAVE_USB3, + SM8250_SLAVE_SERVICE_CNOC, + SM8250_SLAVE_UFS_CARD_CFG, + SM8250_SLAVE_USB3_1, + SM8250_SLAVE_LPASS, + SM8250_SLAVE_RBCPR_CX_CFG, + SM8250_SLAVE_A1NOC_CFG, + SM8250_SLAVE_AOSS, + SM8250_SLAVE_PRNG, + SM8250_SLAVE_VSENSE_CTRL_CFG, + SM8250_SLAVE_QSPI_0, + SM8250_SLAVE_CRYPTO_0_CFG, + SM8250_SLAVE_PIMEM_CFG, + SM8250_SLAVE_RBCPR_MX_CFG, + SM8250_SLAVE_QUP_0, + SM8250_SLAVE_QUP_1, + SM8250_SLAVE_QUP_2, + SM8250_SLAVE_CLK_CTL + }, +}; + +static struct qcom_icc_node qhm_cnoc_dc_noc = { + .name = "qhm_cnoc_dc_noc", + .id = SM8250_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8250_SLAVE_GEM_NOC_CFG, + SM8250_SLAVE_LLCC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = SM8250_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SM8250_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SM8250_MASTER_AMPSS_M0, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_gemnoc_cfg = { + .name = "qhm_gemnoc_cfg", + .id = SM8250_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 3, + .links = { SM8250_SLAVE_SERVICE_GEM_NOC_2, + SM8250_SLAVE_SERVICE_GEM_NOC_1, + SM8250_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM8250_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SM8250_MASTER_GRAPHICS_3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM8250_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM8250_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SM8250_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM8250_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM8250_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SM8250_SLAVE_LLCC, + SM8250_SLAVE_GEM_NOC_SNOC, + SM8250_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM8250_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_EBI_CH0 }, +}; + +static struct qcom_icc_node qhm_mnoc_cfg = { + .name = "qhm_mnoc_cfg", + .id = SM8250_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = SM8250_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .id = SM8250_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .id = SM8250_MASTER_CAMNOC_SF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SM8250_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 = { + .name = "qnm_video1", + .id = SM8250_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SM8250_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM8250_MASTER_MDP_PORT0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SM8250_MASTER_MDP_PORT1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SM8250_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys = { + .name = "amm_npu_sys", + .id = SM8250_MASTER_NPU_SYS, + .channels = 4, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node amm_npu_sys_cdp_w = { + .name = "amm_npu_sys_cdp_w", + .id = SM8250_MASTER_NPU_CDP, + .channels = 2, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_SLAVE_NPU_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhm_cfg = { + .name = "qhm_cfg", + .id = SM8250_MASTER_NPU_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 9, + .links = { SM8250_SLAVE_SERVICE_NPU_NOC, + SM8250_SLAVE_ISENSE_CFG, + SM8250_SLAVE_NPU_LLM_CFG, + SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + SM8250_SLAVE_NPU_CP, + SM8250_SLAVE_NPU_TCM, + SM8250_SLAVE_NPU_CAL_DP0, + SM8250_SLAVE_NPU_CAL_DP1, + SM8250_SLAVE_NPU_DPM + }, +}; + +static struct qcom_icc_node qhm_snoc_cfg = { + .name = "qhm_snoc_cfg", + .id = SM8250_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM8250_A1NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM8250_A2NOC_SNOC_MAS, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_gemnoc = { + .name = "qnm_gemnoc", + .id = SM8250_MASTER_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 6, + .links = { SM8250_SLAVE_PIMEM, + SM8250_SLAVE_OCIMEM, + SM8250_SLAVE_APPSS, + SM8250_SNOC_CNOC_SLV, + SM8250_SLAVE_TCU, + SM8250_SLAVE_QDSS_STM + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SM8250_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 3, + .links = { SM8250_SLAVE_PCIE_2, + SM8250_SLAVE_PCIE_0, + SM8250_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM8250_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM8250_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM8250_A1NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_A1NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_modem_mem_noc = { + .name = "qns_pcie_modem_mem_noc", + .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM8250_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM8250_A2NOC_SNOC_SLV, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_A2NOC_SNOC_MAS }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SM8250_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM8250_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cdsp_mem_noc = { + .name = "qns_cdsp_mem_noc", + .id = SM8250_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node qhs_a1_noc_cfg = { + .name = "qhs_a1_noc_cfg", + .id = SM8250_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_A1NOC_CFG }, +}; + +static struct qcom_icc_node qhs_a2_noc_cfg = { + .name = "qhs_a2_noc_cfg", + .id = SM8250_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_A2NOC_CFG }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SM8250_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SM8250_SLAVE_AHB2PHY_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM8250_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM8250_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM8250_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_dsp = { + .name = "qhs_compute_dsp", + .id = SM8250_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM8250_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SM8250_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM8250_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM8250_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SM8250_SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SM8250_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ddrss_cfg = { + .name = "qhs_ddrss_cfg", + .id = SM8250_SLAVE_CNOC_DDRSS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_CNOC_DC_NOC }, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM8250_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM8250_SLAVE_GRAPHICS_3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM8250_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM8250_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SM8250_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SM8250_SLAVE_LPASS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mnoc_cfg = { + .name = "qhs_mnoc_cfg", + .id = SM8250_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_CNOC_MNOC_CFG }, +}; + +static struct qcom_icc_node qhs_npu_cfg = { + .name = "qhs_npu_cfg", + .id = SM8250_SLAVE_NPU_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_NPU_NOC_CFG }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SM8250_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SM8250_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie_modem_cfg = { + .name = "qhs_pcie_modem_cfg", + .id = SM8250_SLAVE_PCIE_2_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SM8250_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM8250_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_prng = { + .name = "qhs_prng", + .id = SM8250_SLAVE_PRNG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM8250_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SM8250_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SM8250_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SM8250_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SM8250_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM8250_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SM8250_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_snoc_cfg = { + .name = "qhs_snoc_cfg", + .id = SM8250_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_SNOC_CFG }, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM8250_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm0 = { + .name = "qhs_tlmm0", + .id = SM8250_SLAVE_TLMM_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm1 = { + .name = "qhs_tlmm1", + .id = SM8250_SLAVE_TLMM_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm2 = { + .name = "qhs_tlmm2", + .id = SM8250_SLAVE_TLMM_WEST, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tsif = { + .name = "qhs_tsif", + .id = SM8250_SLAVE_TSIF, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SM8250_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM8250_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM8250_SLAVE_USB3, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SM8250_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM8250_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM8250_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_cnoc_a2noc = { + .name = "qns_cnoc_a2noc", + .id = SM8250_SLAVE_CNOC_A2NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_MASTER_CNOC_A2NOC }, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM8250_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM8250_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_memnoc = { + .name = "qhs_memnoc", + .id = SM8250_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_MASTER_GEM_NOC_CFG }, +}; + +static struct qcom_icc_node qns_gem_noc_snoc = { + .name = "qns_gem_noc_snoc", + .id = SM8250_SLAVE_GEM_NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_GEM_NOC_SNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM8250_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_sys_pcie = { + .name = "qns_sys_pcie", + .id = SM8250_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_MASTER_GEM_NOC_PCIE_SNOC }, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .id = SM8250_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .id = SM8250_SLAVE_SERVICE_GEM_NOC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .id = SM8250_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM8250_SLAVE_EBI_CH0, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM8250_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SM8250_SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8250_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM8250_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp0 = { + .name = "qhs_cal_dp0", + .id = SM8250_SLAVE_NPU_CAL_DP0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cal_dp1 = { + .name = "qhs_cal_dp1", + .id = SM8250_SLAVE_NPU_CAL_DP1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cp = { + .name = "qhs_cp", + .id = SM8250_SLAVE_NPU_CP, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dma_bwmon = { + .name = "qhs_dma_bwmon", + .id = SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dpm = { + .name = "qhs_dpm", + .id = SM8250_SLAVE_NPU_DPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_isense = { + .name = "qhs_isense", + .id = SM8250_SLAVE_ISENSE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_llm = { + .name = "qhs_llm", + .id = SM8250_SLAVE_NPU_LLM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcm = { + .name = "qhs_tcm", + .id = SM8250_SLAVE_NPU_TCM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_npu_sys = { + .name = "qns_npu_sys", + .id = SM8250_SLAVE_NPU_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, +}; + +static struct qcom_icc_node srvc_noc = { + .name = "srvc_noc", + .id = SM8250_SLAVE_SERVICE_NPU_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM8250_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qns_cnoc = { + .name = "qns_cnoc", + .id = SM8250_SNOC_CNOC_SLV, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_SNOC_CNOC_MAS }, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM8250_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8250_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM8250_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8250_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM8250_SLAVE_OCIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM8250_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM8250_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SM8250_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SM8250_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_modem = { + .name = "xs_pcie_modem", + .id = SM8250_SLAVE_PCIE_2, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM8250_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM8250_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SM8250_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SM8250_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .id = SM8250_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SM8250_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SM8250_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .id = SM8250_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .num_nodes = 3, + .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .num_nodes = 2, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_mm2 = { + .name = "MM2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 = { + .name = "QUP0", + .keepalive = false, + .num_nodes = 3, + .nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_mm3 = { + .name = "MM3", + .keepalive = false, + .num_nodes = 5, + .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_cdsp_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 52, + .nodes = { &qnm_snoc, + &xm_qdss_dap, + &qhs_a1_noc_cfg, + &qhs_a2_noc_cfg, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_dsp, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_ddrss_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_lpass_cfg, + &qhs_mnoc_cfg, + &qhs_npu_cfg, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pcie_modem_cfg, + &qhs_pdm, + &qhs_pimem_cfg, + &qhs_prng, + &qhs_qdss_cfg, + &qhs_qspi, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_sdc2, + &qhs_sdc4, + &qhs_snoc_cfg, + &qhs_tcsr, + &qhs_tlmm0, + &qhs_tlmm1, + &qhs_tlmm2, + &qhs_tsif, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_cnoc_a2noc, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_sn1 = { + .name = "SN1", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_imem }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_co2 = { + .name = "CO2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_npu }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_pcie_modem }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .num_nodes = 2, + .nodes = { &xs_pcie_0, &xs_pcie_1 }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn9 = { + .name = "SN9", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn11 = { + .name = "SN11", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_sn12 = { + .name = "SN12", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { - &bcm_qup0, &bcm_sn12, }; @@ -222,10 +1665,29 @@ static const struct qcom_icc_desc sm8250_aggre1_noc = { static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, - &bcm_qup0, &bcm_sn12, }; +static struct qcom_icc_bcm * const qup_virt_bcms[] = { + &bcm_qup0, +}; + +static struct qcom_icc_node *qup_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, +}; + +static const struct qcom_icc_desc sm8250_qup_virt = { + .nodes = qup_virt_nodes, + .num_nodes = ARRAY_SIZE(qup_virt_nodes), + .bcms = qup_virt_bcms, + .num_bcms = ARRAY_SIZE(qup_virt_bcms), +}; + static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, @@ -518,6 +1980,8 @@ static const struct of_device_id qnoc_of_match[] = { .data = &sm8250_mmss_noc}, { .compatible = "qcom,sm8250-npu-noc", .data = &sm8250_npu_noc}, + { .compatible = "qcom,sm8250-qup-virt", + .data = &sm8250_qup_virt }, { .compatible = "qcom,sm8250-system-noc", .data = &sm8250_system_noc}, { } diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h index 209ab195f21f..032665093c5b 100644 --- a/drivers/interconnect/qcom/sm8250.h +++ b/drivers/interconnect/qcom/sm8250.h @@ -158,5 +158,11 @@ #define SM8250_SLAVE_VSENSE_CTRL_CFG 147 #define SM8250_SNOC_CNOC_MAS 148 #define SM8250_SNOC_CNOC_SLV 149 +#define SM8250_MASTER_QUP_CORE_0 150 +#define SM8250_MASTER_QUP_CORE_1 151 +#define SM8250_MASTER_QUP_CORE_2 152 +#define SM8250_SLAVE_QUP_CORE_0 153 +#define SM8250_SLAVE_QUP_CORE_1 154 +#define SM8250_SLAVE_QUP_CORE_2 155 #endif diff --git a/drivers/interconnect/qcom/sm8350.c b/drivers/interconnect/qcom/sm8350.c index 5398e7c8d826..bdf75839e6d1 100644 --- a/drivers/interconnect/qcom/sm8350.c +++ b/drivers/interconnect/qcom/sm8350.c @@ -7,196 +7,1629 @@ #include <linux/interconnect-provider.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> #include <dt-bindings/interconnect/qcom,sm8350.h> #include "bcm-voter.h" #include "icc-rpmh.h" #include "sm8350.h" -DEFINE_QNODE(qhm_qspi, SM8350_MASTER_QSPI_0, 1, 4, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup0, SM8350_MASTER_QUP_0, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qhm_qup1, SM8350_MASTER_QUP_1, 1, 4, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qup2, SM8350_MASTER_QUP_2, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_a1noc_cfg, SM8350_MASTER_A1NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A1NOC); -DEFINE_QNODE(xm_sdc4, SM8350_MASTER_SDCC_4, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_ufs_mem, SM8350_MASTER_UFS_MEM, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_usb3_0, SM8350_MASTER_USB3_0, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(xm_usb3_1, SM8350_MASTER_USB3_1, 1, 8, SM8350_SLAVE_A1NOC_SNOC); -DEFINE_QNODE(qhm_qdss_bam, SM8350_MASTER_QDSS_BAM, 1, 4, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_a2noc_cfg, SM8350_MASTER_A2NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_A2NOC); -DEFINE_QNODE(qxm_crypto, SM8350_MASTER_CRYPTO, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qxm_ipa, SM8350_MASTER_IPA, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_pcie3_0, SM8350_MASTER_PCIE_0, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_pcie3_1, SM8350_MASTER_PCIE_1, 1, 8, SM8350_SLAVE_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(xm_qdss_etr, SM8350_MASTER_QDSS_ETR, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_sdc2, SM8350_MASTER_SDCC_2, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(xm_ufs_card, SM8350_MASTER_UFS_CARD, 1, 8, SM8350_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(qnm_gemnoc_cnoc, SM8350_MASTER_GEM_NOC_CNOC, 1, 16, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU); -DEFINE_QNODE(qnm_gemnoc_pcie, SM8350_MASTER_GEM_NOC_PCIE_SNOC, 1, 8, SM8350_SLAVE_PCIE_0, SM8350_SLAVE_PCIE_1); -DEFINE_QNODE(xm_qdss_dap, SM8350_MASTER_QDSS_DAP, 1, 8, SM8350_SLAVE_AHB2PHY_SOUTH, SM8350_SLAVE_AHB2PHY_NORTH, SM8350_SLAVE_AOSS, SM8350_SLAVE_APPSS, SM8350_SLAVE_CAMERA_CFG, SM8350_SLAVE_CLK_CTL, SM8350_SLAVE_CDSP_CFG, SM8350_SLAVE_RBCPR_CX_CFG, SM8350_SLAVE_RBCPR_MMCX_CFG, SM8350_SLAVE_RBCPR_MX_CFG, SM8350_SLAVE_CRYPTO_0_CFG, SM8350_SLAVE_CX_RDPM, SM8350_SLAVE_DCC_CFG, SM8350_SLAVE_DISPLAY_CFG, SM8350_SLAVE_GFX3D_CFG, SM8350_SLAVE_HWKM, SM8350_SLAVE_IMEM_CFG, SM8350_SLAVE_IPA_CFG, SM8350_SLAVE_IPC_ROUTER_CFG, SM8350_SLAVE_LPASS, SM8350_SLAVE_CNOC_MSS, SM8350_SLAVE_MX_RDPM, SM8350_SLAVE_PCIE_0_CFG, SM8350_SLAVE_PCIE_1_CFG, SM8350_SLAVE_PDM, SM8350_SLAVE_PIMEM_CFG, SM8350_SLAVE_PKA_WRAPPER_CFG, SM8350_SLAVE_PMU_WRAPPER_CFG, SM8350_SLAVE_QDSS_CFG, SM8350_SLAVE_QSPI_0, SM8350_SLAVE_QUP_0, SM8350_SLAVE_QUP_1, SM8350_SLAVE_QUP_2, SM8350_SLAVE_SDCC_2, SM8350_SLAVE_SDCC_4, SM8350_SLAVE_SECURITY, SM8350_SLAVE_SPSS_CFG, SM8350_SLAVE_TCSR, SM8350_SLAVE_TLMM, SM8350_SLAVE_UFS_CARD_CFG, SM8350_SLAVE_UFS_MEM_CFG, SM8350_SLAVE_USB3_0, SM8350_SLAVE_USB3_1, SM8350_SLAVE_VENUS_CFG, SM8350_SLAVE_VSENSE_CTRL_CFG, SM8350_SLAVE_A1NOC_CFG, SM8350_SLAVE_A2NOC_CFG, SM8350_SLAVE_DDRSS_CFG, SM8350_SLAVE_CNOC_MNOC_CFG, SM8350_SLAVE_SNOC_CFG, SM8350_SLAVE_BOOT_IMEM, SM8350_SLAVE_IMEM, SM8350_SLAVE_PIMEM, SM8350_SLAVE_SERVICE_CNOC, SM8350_SLAVE_QDSS_STM, SM8350_SLAVE_TCU); -DEFINE_QNODE(qnm_cnoc_dc_noc, SM8350_MASTER_CNOC_DC_NOC, 1, 4, SM8350_SLAVE_LLCC_CFG, SM8350_SLAVE_GEM_NOC_CFG); -DEFINE_QNODE(alm_gpu_tcu, SM8350_MASTER_GPU_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(alm_sys_tcu, SM8350_MASTER_SYS_TCU, 1, 8, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(chm_apps, SM8350_MASTER_APPSS_PROC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qnm_cmpnoc, SM8350_MASTER_COMPUTE_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_gemnoc_cfg, SM8350_MASTER_GEM_NOC_CFG, 1, 4, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, SM8350_SLAVE_MCDMA_MS_MPU_CFG, SM8350_SLAVE_SERVICE_GEM_NOC_1, SM8350_SLAVE_SERVICE_GEM_NOC_2, SM8350_SLAVE_SERVICE_GEM_NOC); -DEFINE_QNODE(qnm_gpu, SM8350_MASTER_GFX3D, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_hf, SM8350_MASTER_MNOC_HF_MEM_NOC, 2, 32, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_mnoc_sf, SM8350_MASTER_MNOC_SF_MEM_NOC, 2, 32, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_pcie, SM8350_MASTER_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_gc, SM8350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM8350_SLAVE_LLCC); -DEFINE_QNODE(qnm_snoc_sf, SM8350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM8350_SLAVE_GEM_NOC_CNOC, SM8350_SLAVE_LLCC, SM8350_SLAVE_MEM_NOC_PCIE_SNOC); -DEFINE_QNODE(qhm_config_noc, SM8350_MASTER_CNOC_LPASS_AG_NOC, 1, 4, SM8350_SLAVE_LPASS_CORE_CFG, SM8350_SLAVE_LPASS_LPI_CFG, SM8350_SLAVE_LPASS_MPU_CFG, SM8350_SLAVE_LPASS_TOP_CFG, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, SM8350_SLAVE_SERVICE_LPASS_AG_NOC); -DEFINE_QNODE(llcc_mc, SM8350_MASTER_LLCC, 4, 4, SM8350_SLAVE_EBI1); -DEFINE_QNODE(qnm_camnoc_hf, SM8350_MASTER_CAMNOC_HF, 2, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_icp, SM8350_MASTER_CAMNOC_ICP, 1, 8, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_camnoc_sf, SM8350_MASTER_CAMNOC_SF, 2, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_mnoc_cfg, SM8350_MASTER_CNOC_MNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_MNOC); -DEFINE_QNODE(qnm_video0, SM8350_MASTER_VIDEO_P0, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video1, SM8350_MASTER_VIDEO_P1, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qnm_video_cvp, SM8350_MASTER_VIDEO_PROC, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qxm_mdp0, SM8350_MASTER_MDP0, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_mdp1, SM8350_MASTER_MDP1, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qxm_rot, SM8350_MASTER_ROTATOR, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC); -DEFINE_QNODE(qhm_nsp_noc_config, SM8350_MASTER_CDSP_NOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_NSP_NOC); -DEFINE_QNODE(qxm_nsp, SM8350_MASTER_CDSP_PROC, 2, 32, SM8350_SLAVE_CDSP_MEM_NOC); -DEFINE_QNODE(qnm_aggre1_noc, SM8350_MASTER_A1NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_aggre2_noc, SM8350_MASTER_A2NOC_SNOC, 1, 16, SM8350_SLAVE_SNOC_GEM_NOC_SF); -DEFINE_QNODE(qnm_snoc_cfg, SM8350_MASTER_SNOC_CFG, 1, 4, SM8350_SLAVE_SERVICE_SNOC); -DEFINE_QNODE(qxm_pimem, SM8350_MASTER_PIMEM, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(xm_gic, SM8350_MASTER_GIC, 1, 8, SM8350_SLAVE_SNOC_GEM_NOC_GC); -DEFINE_QNODE(qnm_mnoc_hf_disp, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP); -DEFINE_QNODE(qnm_mnoc_sf_disp, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_SLAVE_LLCC_DISP); -DEFINE_QNODE(llcc_mc_disp, SM8350_MASTER_LLCC_DISP, 4, 4, SM8350_SLAVE_EBI1_DISP); -DEFINE_QNODE(qxm_mdp0_disp, SM8350_MASTER_MDP0_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_mdp1_disp, SM8350_MASTER_MDP1_DISP, 1, 32, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qxm_rot_disp, SM8350_MASTER_ROTATOR_DISP, 1, 32, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP); -DEFINE_QNODE(qns_a1noc_snoc, SM8350_SLAVE_A1NOC_SNOC, 1, 16, SM8350_MASTER_A1NOC_SNOC); -DEFINE_QNODE(srvc_aggre1_noc, SM8350_SLAVE_SERVICE_A1NOC, 1, 4); -DEFINE_QNODE(qns_a2noc_snoc, SM8350_SLAVE_A2NOC_SNOC, 1, 16, SM8350_MASTER_A2NOC_SNOC); -DEFINE_QNODE(qns_pcie_mem_noc, SM8350_SLAVE_ANOC_PCIE_GEM_NOC, 1, 16, SM8350_MASTER_ANOC_PCIE_GEM_NOC); -DEFINE_QNODE(srvc_aggre2_noc, SM8350_SLAVE_SERVICE_A2NOC, 1, 4); -DEFINE_QNODE(qhs_ahb2phy0, SM8350_SLAVE_AHB2PHY_SOUTH, 1, 4); -DEFINE_QNODE(qhs_ahb2phy1, SM8350_SLAVE_AHB2PHY_NORTH, 1, 4); -DEFINE_QNODE(qhs_aoss, SM8350_SLAVE_AOSS, 1, 4); -DEFINE_QNODE(qhs_apss, SM8350_SLAVE_APPSS, 1, 8); -DEFINE_QNODE(qhs_camera_cfg, SM8350_SLAVE_CAMERA_CFG, 1, 4); -DEFINE_QNODE(qhs_clk_ctl, SM8350_SLAVE_CLK_CTL, 1, 4); -DEFINE_QNODE(qhs_compute_cfg, SM8350_SLAVE_CDSP_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_cx, SM8350_SLAVE_RBCPR_CX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mmcx, SM8350_SLAVE_RBCPR_MMCX_CFG, 1, 4); -DEFINE_QNODE(qhs_cpr_mx, SM8350_SLAVE_RBCPR_MX_CFG, 1, 4); -DEFINE_QNODE(qhs_crypto0_cfg, SM8350_SLAVE_CRYPTO_0_CFG, 1, 4); -DEFINE_QNODE(qhs_cx_rdpm, SM8350_SLAVE_CX_RDPM, 1, 4); -DEFINE_QNODE(qhs_dcc_cfg, SM8350_SLAVE_DCC_CFG, 1, 4); -DEFINE_QNODE(qhs_display_cfg, SM8350_SLAVE_DISPLAY_CFG, 1, 4); -DEFINE_QNODE(qhs_gpuss_cfg, SM8350_SLAVE_GFX3D_CFG, 1, 8); -DEFINE_QNODE(qhs_hwkm, SM8350_SLAVE_HWKM, 1, 4); -DEFINE_QNODE(qhs_imem_cfg, SM8350_SLAVE_IMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_ipa, SM8350_SLAVE_IPA_CFG, 1, 4); -DEFINE_QNODE(qhs_ipc_router, SM8350_SLAVE_IPC_ROUTER_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_cfg, SM8350_SLAVE_LPASS, 1, 4, SM8350_MASTER_CNOC_LPASS_AG_NOC); -DEFINE_QNODE(qhs_mss_cfg, SM8350_SLAVE_CNOC_MSS, 1, 4); -DEFINE_QNODE(qhs_mx_rdpm, SM8350_SLAVE_MX_RDPM, 1, 4); -DEFINE_QNODE(qhs_pcie0_cfg, SM8350_SLAVE_PCIE_0_CFG, 1, 4); -DEFINE_QNODE(qhs_pcie1_cfg, SM8350_SLAVE_PCIE_1_CFG, 1, 4); -DEFINE_QNODE(qhs_pdm, SM8350_SLAVE_PDM, 1, 4); -DEFINE_QNODE(qhs_pimem_cfg, SM8350_SLAVE_PIMEM_CFG, 1, 4); -DEFINE_QNODE(qhs_pka_wrapper_cfg, SM8350_SLAVE_PKA_WRAPPER_CFG, 1, 4); -DEFINE_QNODE(qhs_pmu_wrapper_cfg, SM8350_SLAVE_PMU_WRAPPER_CFG, 1, 4); -DEFINE_QNODE(qhs_qdss_cfg, SM8350_SLAVE_QDSS_CFG, 1, 4); -DEFINE_QNODE(qhs_qspi, SM8350_SLAVE_QSPI_0, 1, 4); -DEFINE_QNODE(qhs_qup0, SM8350_SLAVE_QUP_0, 1, 4); -DEFINE_QNODE(qhs_qup1, SM8350_SLAVE_QUP_1, 1, 4); -DEFINE_QNODE(qhs_qup2, SM8350_SLAVE_QUP_2, 1, 4); -DEFINE_QNODE(qhs_sdc2, SM8350_SLAVE_SDCC_2, 1, 4); -DEFINE_QNODE(qhs_sdc4, SM8350_SLAVE_SDCC_4, 1, 4); -DEFINE_QNODE(qhs_security, SM8350_SLAVE_SECURITY, 1, 4); -DEFINE_QNODE(qhs_spss_cfg, SM8350_SLAVE_SPSS_CFG, 1, 4); -DEFINE_QNODE(qhs_tcsr, SM8350_SLAVE_TCSR, 1, 4); -DEFINE_QNODE(qhs_tlmm, SM8350_SLAVE_TLMM, 1, 4); -DEFINE_QNODE(qhs_ufs_card_cfg, SM8350_SLAVE_UFS_CARD_CFG, 1, 4); -DEFINE_QNODE(qhs_ufs_mem_cfg, SM8350_SLAVE_UFS_MEM_CFG, 1, 4); -DEFINE_QNODE(qhs_usb3_0, SM8350_SLAVE_USB3_0, 1, 4); -DEFINE_QNODE(qhs_usb3_1, SM8350_SLAVE_USB3_1, 1, 4); -DEFINE_QNODE(qhs_venus_cfg, SM8350_SLAVE_VENUS_CFG, 1, 4); -DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM8350_SLAVE_VSENSE_CTRL_CFG, 1, 4); -DEFINE_QNODE(qns_a1_noc_cfg, SM8350_SLAVE_A1NOC_CFG, 1, 4); -DEFINE_QNODE(qns_a2_noc_cfg, SM8350_SLAVE_A2NOC_CFG, 1, 4); -DEFINE_QNODE(qns_ddrss_cfg, SM8350_SLAVE_DDRSS_CFG, 1, 4); -DEFINE_QNODE(qns_mnoc_cfg, SM8350_SLAVE_CNOC_MNOC_CFG, 1, 4); -DEFINE_QNODE(qns_snoc_cfg, SM8350_SLAVE_SNOC_CFG, 1, 4); -DEFINE_QNODE(qxs_boot_imem, SM8350_SLAVE_BOOT_IMEM, 1, 8); -DEFINE_QNODE(qxs_imem, SM8350_SLAVE_IMEM, 1, 8); -DEFINE_QNODE(qxs_pimem, SM8350_SLAVE_PIMEM, 1, 8); -DEFINE_QNODE(srvc_cnoc, SM8350_SLAVE_SERVICE_CNOC, 1, 4); -DEFINE_QNODE(xs_pcie_0, SM8350_SLAVE_PCIE_0, 1, 8); -DEFINE_QNODE(xs_pcie_1, SM8350_SLAVE_PCIE_1, 1, 8); -DEFINE_QNODE(xs_qdss_stm, SM8350_SLAVE_QDSS_STM, 1, 4); -DEFINE_QNODE(xs_sys_tcu_cfg, SM8350_SLAVE_TCU, 1, 8); -DEFINE_QNODE(qhs_llcc, SM8350_SLAVE_LLCC_CFG, 1, 4); -DEFINE_QNODE(qns_gemnoc, SM8350_SLAVE_GEM_NOC_CFG, 1, 4); -DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_modem_ms_mpu_cfg, SM8350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); -DEFINE_QNODE(qns_gem_noc_cnoc, SM8350_SLAVE_GEM_NOC_CNOC, 1, 16, SM8350_MASTER_GEM_NOC_CNOC); -DEFINE_QNODE(qns_llcc, SM8350_SLAVE_LLCC, 4, 16, SM8350_MASTER_LLCC); -DEFINE_QNODE(qns_pcie, SM8350_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8); -DEFINE_QNODE(srvc_even_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_1, 1, 4); -DEFINE_QNODE(srvc_odd_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC_2, 1, 4); -DEFINE_QNODE(srvc_sys_gemnoc, SM8350_SLAVE_SERVICE_GEM_NOC, 1, 4); -DEFINE_QNODE(qhs_lpass_core, SM8350_SLAVE_LPASS_CORE_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_lpi, SM8350_SLAVE_LPASS_LPI_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_mpu, SM8350_SLAVE_LPASS_MPU_CFG, 1, 4); -DEFINE_QNODE(qhs_lpass_top, SM8350_SLAVE_LPASS_TOP_CFG, 1, 4); -DEFINE_QNODE(srvc_niu_aml_noc, SM8350_SLAVE_SERVICES_LPASS_AML_NOC, 1, 4); -DEFINE_QNODE(srvc_niu_lpass_agnoc, SM8350_SLAVE_SERVICE_LPASS_AG_NOC, 1, 4); -DEFINE_QNODE(ebi, SM8350_SLAVE_EBI1, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf, SM8350_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC); -DEFINE_QNODE(qns_mem_noc_sf, SM8350_SLAVE_MNOC_SF_MEM_NOC, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_mnoc, SM8350_SLAVE_SERVICE_MNOC, 1, 4); -DEFINE_QNODE(qns_nsp_gemnoc, SM8350_SLAVE_CDSP_MEM_NOC, 2, 32, SM8350_MASTER_COMPUTE_NOC); -DEFINE_QNODE(service_nsp_noc, SM8350_SLAVE_SERVICE_NSP_NOC, 1, 4); -DEFINE_QNODE(qns_gemnoc_gc, SM8350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM8350_MASTER_SNOC_GC_MEM_NOC); -DEFINE_QNODE(qns_gemnoc_sf, SM8350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM8350_MASTER_SNOC_SF_MEM_NOC); -DEFINE_QNODE(srvc_snoc, SM8350_SLAVE_SERVICE_SNOC, 1, 4); -DEFINE_QNODE(qns_llcc_disp, SM8350_SLAVE_LLCC_DISP, 4, 16, SM8350_MASTER_LLCC_DISP); -DEFINE_QNODE(ebi_disp, SM8350_SLAVE_EBI1_DISP, 4, 4); -DEFINE_QNODE(qns_mem_noc_hf_disp, SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_HF_MEM_NOC_DISP); -DEFINE_QNODE(qns_mem_noc_sf_disp, SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, 2, 32, SM8350_MASTER_MNOC_SF_MEM_NOC_DISP); - -DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); -DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); -DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie); -DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_qdss_dap, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_apss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_cfg, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_hwkm, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mx_rdpm, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_security, &qhs_spss_cfg, &qhs_tcsr, &qhs_tlmm, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, &qns_a2_noc_cfg, &qns_ddrss_cfg, &qns_mnoc_cfg, &qns_snoc_cfg, &srvc_cnoc); -DEFINE_QBCM(bcm_cn2, "CN2", false, &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4); -DEFINE_QBCM(bcm_co0, "CO0", false, &qns_nsp_gemnoc); -DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_nsp); -DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); -DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); -DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); -DEFINE_QBCM(bcm_mm4, "MM4", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_mm5, "MM5", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp, &qxm_rot); -DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); -DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); -DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); -DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); -DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); -DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); -DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); -DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); -DEFINE_QBCM(bcm_sn5, "SN5", false, &xm_pcie3_0); -DEFINE_QBCM(bcm_sn6, "SN6", false, &xm_pcie3_1); -DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc); -DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc); -DEFINE_QBCM(bcm_sn14, "SN14", false, &qns_pcie_mem_noc); -DEFINE_QBCM(bcm_acv_disp, "ACV", false, &ebi_disp); -DEFINE_QBCM(bcm_mc0_disp, "MC0", false, &ebi_disp); -DEFINE_QBCM(bcm_mm0_disp, "MM0", false, &qns_mem_noc_hf_disp); -DEFINE_QBCM(bcm_mm1_disp, "MM1", false, &qxm_mdp0_disp, &qxm_mdp1_disp); -DEFINE_QBCM(bcm_mm4_disp, "MM4", false, &qns_mem_noc_sf_disp); -DEFINE_QBCM(bcm_mm5_disp, "MM5", false, &qxm_rot_disp); -DEFINE_QBCM(bcm_sh0_disp, "SH0", false, &qns_llcc_disp); +static struct qcom_icc_node qhm_qspi = { + .name = "qhm_qspi", + .id = SM8350_MASTER_QSPI_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup0 = { + .name = "qhm_qup0", + .id = SM8350_MASTER_QUP_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup1 = { + .name = "qhm_qup1", + .id = SM8350_MASTER_QUP_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qup2 = { + .name = "qhm_qup2", + .id = SM8350_MASTER_QUP_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a1noc_cfg = { + .name = "qnm_a1noc_cfg", + .id = SM8350_MASTER_A1NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_A1NOC }, +}; + +static struct qcom_icc_node xm_sdc4 = { + .name = "xm_sdc4", + .id = SM8350_MASTER_SDCC_4, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_mem = { + .name = "xm_ufs_mem", + .id = SM8350_MASTER_UFS_MEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_0 = { + .name = "xm_usb3_0", + .id = SM8350_MASTER_USB3_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node xm_usb3_1 = { + .name = "xm_usb3_1", + .id = SM8350_MASTER_USB3_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A1NOC_SNOC }, +}; + +static struct qcom_icc_node qhm_qdss_bam = { + .name = "qhm_qdss_bam", + .id = SM8350_MASTER_QDSS_BAM, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_a2noc_cfg = { + .name = "qnm_a2noc_cfg", + .id = SM8350_MASTER_A2NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_A2NOC }, +}; + +static struct qcom_icc_node qxm_crypto = { + .name = "qxm_crypto", + .id = SM8350_MASTER_CRYPTO, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qxm_ipa = { + .name = "qxm_ipa", + .id = SM8350_MASTER_IPA, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_pcie3_0 = { + .name = "xm_pcie3_0", + .id = SM8350_MASTER_PCIE_0, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_pcie3_1 = { + .name = "xm_pcie3_1", + .id = SM8350_MASTER_PCIE_1, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node xm_qdss_etr = { + .name = "xm_qdss_etr", + .id = SM8350_MASTER_QDSS_ETR, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_sdc2 = { + .name = "xm_sdc2", + .id = SM8350_MASTER_SDCC_2, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node xm_ufs_card = { + .name = "xm_ufs_card", + .id = SM8350_MASTER_UFS_CARD, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc = { + .name = "qnm_gemnoc_cnoc", + .id = SM8350_MASTER_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 56, + .links = { SM8350_SLAVE_AHB2PHY_SOUTH, + SM8350_SLAVE_AHB2PHY_NORTH, + SM8350_SLAVE_AOSS, + SM8350_SLAVE_APPSS, + SM8350_SLAVE_CAMERA_CFG, + SM8350_SLAVE_CLK_CTL, + SM8350_SLAVE_CDSP_CFG, + SM8350_SLAVE_RBCPR_CX_CFG, + SM8350_SLAVE_RBCPR_MMCX_CFG, + SM8350_SLAVE_RBCPR_MX_CFG, + SM8350_SLAVE_CRYPTO_0_CFG, + SM8350_SLAVE_CX_RDPM, + SM8350_SLAVE_DCC_CFG, + SM8350_SLAVE_DISPLAY_CFG, + SM8350_SLAVE_GFX3D_CFG, + SM8350_SLAVE_HWKM, + SM8350_SLAVE_IMEM_CFG, + SM8350_SLAVE_IPA_CFG, + SM8350_SLAVE_IPC_ROUTER_CFG, + SM8350_SLAVE_LPASS, + SM8350_SLAVE_CNOC_MSS, + SM8350_SLAVE_MX_RDPM, + SM8350_SLAVE_PCIE_0_CFG, + SM8350_SLAVE_PCIE_1_CFG, + SM8350_SLAVE_PDM, + SM8350_SLAVE_PIMEM_CFG, + SM8350_SLAVE_PKA_WRAPPER_CFG, + SM8350_SLAVE_PMU_WRAPPER_CFG, + SM8350_SLAVE_QDSS_CFG, + SM8350_SLAVE_QSPI_0, + SM8350_SLAVE_QUP_0, + SM8350_SLAVE_QUP_1, + SM8350_SLAVE_QUP_2, + SM8350_SLAVE_SDCC_2, + SM8350_SLAVE_SDCC_4, + SM8350_SLAVE_SECURITY, + SM8350_SLAVE_SPSS_CFG, + SM8350_SLAVE_TCSR, + SM8350_SLAVE_TLMM, + SM8350_SLAVE_UFS_CARD_CFG, + SM8350_SLAVE_UFS_MEM_CFG, + SM8350_SLAVE_USB3_0, + SM8350_SLAVE_USB3_1, + SM8350_SLAVE_VENUS_CFG, + SM8350_SLAVE_VSENSE_CTRL_CFG, + SM8350_SLAVE_A1NOC_CFG, + SM8350_SLAVE_A2NOC_CFG, + SM8350_SLAVE_DDRSS_CFG, + SM8350_SLAVE_CNOC_MNOC_CFG, + SM8350_SLAVE_SNOC_CFG, + SM8350_SLAVE_BOOT_IMEM, + SM8350_SLAVE_IMEM, + SM8350_SLAVE_PIMEM, + SM8350_SLAVE_SERVICE_CNOC, + SM8350_SLAVE_QDSS_STM, + SM8350_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie = { + .name = "qnm_gemnoc_pcie", + .id = SM8350_MASTER_GEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8350_SLAVE_PCIE_0, + SM8350_SLAVE_PCIE_1 + }, +}; + +static struct qcom_icc_node xm_qdss_dap = { + .name = "xm_qdss_dap", + .id = SM8350_MASTER_QDSS_DAP, + .channels = 1, + .buswidth = 8, + .num_links = 56, + .links = { SM8350_SLAVE_AHB2PHY_SOUTH, + SM8350_SLAVE_AHB2PHY_NORTH, + SM8350_SLAVE_AOSS, + SM8350_SLAVE_APPSS, + SM8350_SLAVE_CAMERA_CFG, + SM8350_SLAVE_CLK_CTL, + SM8350_SLAVE_CDSP_CFG, + SM8350_SLAVE_RBCPR_CX_CFG, + SM8350_SLAVE_RBCPR_MMCX_CFG, + SM8350_SLAVE_RBCPR_MX_CFG, + SM8350_SLAVE_CRYPTO_0_CFG, + SM8350_SLAVE_CX_RDPM, + SM8350_SLAVE_DCC_CFG, + SM8350_SLAVE_DISPLAY_CFG, + SM8350_SLAVE_GFX3D_CFG, + SM8350_SLAVE_HWKM, + SM8350_SLAVE_IMEM_CFG, + SM8350_SLAVE_IPA_CFG, + SM8350_SLAVE_IPC_ROUTER_CFG, + SM8350_SLAVE_LPASS, + SM8350_SLAVE_CNOC_MSS, + SM8350_SLAVE_MX_RDPM, + SM8350_SLAVE_PCIE_0_CFG, + SM8350_SLAVE_PCIE_1_CFG, + SM8350_SLAVE_PDM, + SM8350_SLAVE_PIMEM_CFG, + SM8350_SLAVE_PKA_WRAPPER_CFG, + SM8350_SLAVE_PMU_WRAPPER_CFG, + SM8350_SLAVE_QDSS_CFG, + SM8350_SLAVE_QSPI_0, + SM8350_SLAVE_QUP_0, + SM8350_SLAVE_QUP_1, + SM8350_SLAVE_QUP_2, + SM8350_SLAVE_SDCC_2, + SM8350_SLAVE_SDCC_4, + SM8350_SLAVE_SECURITY, + SM8350_SLAVE_SPSS_CFG, + SM8350_SLAVE_TCSR, + SM8350_SLAVE_TLMM, + SM8350_SLAVE_UFS_CARD_CFG, + SM8350_SLAVE_UFS_MEM_CFG, + SM8350_SLAVE_USB3_0, + SM8350_SLAVE_USB3_1, + SM8350_SLAVE_VENUS_CFG, + SM8350_SLAVE_VSENSE_CTRL_CFG, + SM8350_SLAVE_A1NOC_CFG, + SM8350_SLAVE_A2NOC_CFG, + SM8350_SLAVE_DDRSS_CFG, + SM8350_SLAVE_CNOC_MNOC_CFG, + SM8350_SLAVE_SNOC_CFG, + SM8350_SLAVE_BOOT_IMEM, + SM8350_SLAVE_IMEM, + SM8350_SLAVE_PIMEM, + SM8350_SLAVE_SERVICE_CNOC, + SM8350_SLAVE_QDSS_STM, + SM8350_SLAVE_TCU + }, +}; + +static struct qcom_icc_node qnm_cnoc_dc_noc = { + .name = "qnm_cnoc_dc_noc", + .id = SM8350_MASTER_CNOC_DC_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 2, + .links = { SM8350_SLAVE_LLCC_CFG, + SM8350_SLAVE_GEM_NOC_CFG + }, +}; + +static struct qcom_icc_node alm_gpu_tcu = { + .name = "alm_gpu_tcu", + .id = SM8350_MASTER_GPU_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node alm_sys_tcu = { + .name = "alm_sys_tcu", + .id = SM8350_MASTER_SYS_TCU, + .channels = 1, + .buswidth = 8, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node chm_apps = { + .name = "chm_apps", + .id = SM8350_MASTER_APPSS_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 3, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC, + SM8350_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qnm_cmpnoc = { + .name = "qnm_cmpnoc", + .id = SM8350_MASTER_COMPUTE_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_gemnoc_cfg = { + .name = "qnm_gemnoc_cfg", + .id = SM8350_MASTER_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 5, + .links = { SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, + SM8350_SLAVE_MCDMA_MS_MPU_CFG, + SM8350_SLAVE_SERVICE_GEM_NOC_1, + SM8350_SLAVE_SERVICE_GEM_NOC_2, + SM8350_SLAVE_SERVICE_GEM_NOC + }, +}; + +static struct qcom_icc_node qnm_gpu = { + .name = "qnm_gpu", + .id = SM8350_MASTER_GFX3D, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_mnoc_hf = { + .name = "qnm_mnoc_hf", + .id = SM8350_MASTER_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_mnoc_sf = { + .name = "qnm_mnoc_sf", + .id = SM8350_MASTER_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_pcie = { + .name = "qnm_pcie", + .id = SM8350_MASTER_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 2, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC + }, +}; + +static struct qcom_icc_node qnm_snoc_gc = { + .name = "qnm_snoc_gc", + .id = SM8350_MASTER_SNOC_GC_MEM_NOC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC }, +}; + +static struct qcom_icc_node qnm_snoc_sf = { + .name = "qnm_snoc_sf", + .id = SM8350_MASTER_SNOC_SF_MEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 3, + .links = { SM8350_SLAVE_GEM_NOC_CNOC, + SM8350_SLAVE_LLCC, + SM8350_SLAVE_MEM_NOC_PCIE_SNOC + }, +}; + +static struct qcom_icc_node qhm_config_noc = { + .name = "qhm_config_noc", + .id = SM8350_MASTER_CNOC_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, + .num_links = 6, + .links = { SM8350_SLAVE_LPASS_CORE_CFG, + SM8350_SLAVE_LPASS_LPI_CFG, + SM8350_SLAVE_LPASS_MPU_CFG, + SM8350_SLAVE_LPASS_TOP_CFG, + SM8350_SLAVE_SERVICES_LPASS_AML_NOC, + SM8350_SLAVE_SERVICE_LPASS_AG_NOC + }, +}; + +static struct qcom_icc_node llcc_mc = { + .name = "llcc_mc", + .id = SM8350_MASTER_LLCC, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_EBI1 }, +}; + +static struct qcom_icc_node qnm_camnoc_hf = { + .name = "qnm_camnoc_hf", + .id = SM8350_MASTER_CAMNOC_HF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_icp = { + .name = "qnm_camnoc_icp", + .id = SM8350_MASTER_CAMNOC_ICP, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_camnoc_sf = { + .name = "qnm_camnoc_sf", + .id = SM8350_MASTER_CAMNOC_SF, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_mnoc_cfg = { + .name = "qnm_mnoc_cfg", + .id = SM8350_MASTER_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_MNOC }, +}; + +static struct qcom_icc_node qnm_video0 = { + .name = "qnm_video0", + .id = SM8350_MASTER_VIDEO_P0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video1 = { + .name = "qnm_video1", + .id = SM8350_MASTER_VIDEO_P1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_video_cvp = { + .name = "qnm_video_cvp", + .id = SM8350_MASTER_VIDEO_PROC, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp0 = { + .name = "qxm_mdp0", + .id = SM8350_MASTER_MDP0, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_mdp1 = { + .name = "qxm_mdp1", + .id = SM8350_MASTER_MDP1, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qxm_rot = { + .name = "qxm_rot", + .id = SM8350_MASTER_ROTATOR, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node qhm_nsp_noc_config = { + .name = "qhm_nsp_noc_config", + .id = SM8350_MASTER_CDSP_NOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_NSP_NOC }, +}; + +static struct qcom_icc_node qxm_nsp = { + .name = "qxm_nsp", + .id = SM8350_MASTER_CDSP_PROC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_CDSP_MEM_NOC }, +}; + +static struct qcom_icc_node qnm_aggre1_noc = { + .name = "qnm_aggre1_noc", + .id = SM8350_MASTER_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_aggre2_noc = { + .name = "qnm_aggre2_noc", + .id = SM8350_MASTER_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_SF }, +}; + +static struct qcom_icc_node qnm_snoc_cfg = { + .name = "qnm_snoc_cfg", + .id = SM8350_MASTER_SNOC_CFG, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_SERVICE_SNOC }, +}; + +static struct qcom_icc_node qxm_pimem = { + .name = "qxm_pimem", + .id = SM8350_MASTER_PIMEM, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node xm_gic = { + .name = "xm_gic", + .id = SM8350_MASTER_GIC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_SLAVE_SNOC_GEM_NOC_GC }, +}; + +static struct qcom_icc_node qnm_mnoc_hf_disp = { + .name = "qnm_mnoc_hf_disp", + .id = SM8350_MASTER_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node qnm_mnoc_sf_disp = { + .name = "qnm_mnoc_sf_disp", + .id = SM8350_MASTER_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_LLCC_DISP }, +}; + +static struct qcom_icc_node llcc_mc_disp = { + .name = "llcc_mc_disp", + .id = SM8350_MASTER_LLCC_DISP, + .channels = 4, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_SLAVE_EBI1_DISP }, +}; + +static struct qcom_icc_node qxm_mdp0_disp = { + .name = "qxm_mdp0_disp", + .id = SM8350_MASTER_MDP0_DISP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_mdp1_disp = { + .name = "qxm_mdp1_disp", + .id = SM8350_MASTER_MDP1_DISP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qxm_rot_disp = { + .name = "qxm_rot_disp", + .id = SM8350_MASTER_ROTATOR_DISP, + .channels = 1, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_a1noc_snoc = { + .name = "qns_a1noc_snoc", + .id = SM8350_SLAVE_A1NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_A1NOC_SNOC }, +}; + +static struct qcom_icc_node srvc_aggre1_noc = { + .name = "srvc_aggre1_noc", + .id = SM8350_SLAVE_SERVICE_A1NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2noc_snoc = { + .name = "qns_a2noc_snoc", + .id = SM8350_SLAVE_A2NOC_SNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_A2NOC_SNOC }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc = { + .name = "qns_pcie_mem_noc", + .id = SM8350_SLAVE_ANOC_PCIE_GEM_NOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_ANOC_PCIE_GEM_NOC }, +}; + +static struct qcom_icc_node srvc_aggre2_noc = { + .name = "srvc_aggre2_noc", + .id = SM8350_SLAVE_SERVICE_A2NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 = { + .name = "qhs_ahb2phy0", + .id = SM8350_SLAVE_AHB2PHY_SOUTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 = { + .name = "qhs_ahb2phy1", + .id = SM8350_SLAVE_AHB2PHY_NORTH, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_aoss = { + .name = "qhs_aoss", + .id = SM8350_SLAVE_AOSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_apss = { + .name = "qhs_apss", + .id = SM8350_SLAVE_APPSS, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_camera_cfg = { + .name = "qhs_camera_cfg", + .id = SM8350_SLAVE_CAMERA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_clk_ctl = { + .name = "qhs_clk_ctl", + .id = SM8350_SLAVE_CLK_CTL, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_compute_cfg = { + .name = "qhs_compute_cfg", + .id = SM8350_SLAVE_CDSP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_cx = { + .name = "qhs_cpr_cx", + .id = SM8350_SLAVE_RBCPR_CX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mmcx = { + .name = "qhs_cpr_mmcx", + .id = SM8350_SLAVE_RBCPR_MMCX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cpr_mx = { + .name = "qhs_cpr_mx", + .id = SM8350_SLAVE_RBCPR_MX_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg = { + .name = "qhs_crypto0_cfg", + .id = SM8350_SLAVE_CRYPTO_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_cx_rdpm = { + .name = "qhs_cx_rdpm", + .id = SM8350_SLAVE_CX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_dcc_cfg = { + .name = "qhs_dcc_cfg", + .id = SM8350_SLAVE_DCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_display_cfg = { + .name = "qhs_display_cfg", + .id = SM8350_SLAVE_DISPLAY_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_gpuss_cfg = { + .name = "qhs_gpuss_cfg", + .id = SM8350_SLAVE_GFX3D_CFG, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_hwkm = { + .name = "qhs_hwkm", + .id = SM8350_SLAVE_HWKM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_imem_cfg = { + .name = "qhs_imem_cfg", + .id = SM8350_SLAVE_IMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipa = { + .name = "qhs_ipa", + .id = SM8350_SLAVE_IPA_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ipc_router = { + .name = "qhs_ipc_router", + .id = SM8350_SLAVE_IPC_ROUTER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_cfg = { + .name = "qhs_lpass_cfg", + .id = SM8350_SLAVE_LPASS, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8350_MASTER_CNOC_LPASS_AG_NOC }, +}; + +static struct qcom_icc_node qhs_mss_cfg = { + .name = "qhs_mss_cfg", + .id = SM8350_SLAVE_CNOC_MSS, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mx_rdpm = { + .name = "qhs_mx_rdpm", + .id = SM8350_SLAVE_MX_RDPM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie0_cfg = { + .name = "qhs_pcie0_cfg", + .id = SM8350_SLAVE_PCIE_0_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pcie1_cfg = { + .name = "qhs_pcie1_cfg", + .id = SM8350_SLAVE_PCIE_1_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pdm = { + .name = "qhs_pdm", + .id = SM8350_SLAVE_PDM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pimem_cfg = { + .name = "qhs_pimem_cfg", + .id = SM8350_SLAVE_PIMEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pka_wrapper_cfg = { + .name = "qhs_pka_wrapper_cfg", + .id = SM8350_SLAVE_PKA_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_pmu_wrapper_cfg = { + .name = "qhs_pmu_wrapper_cfg", + .id = SM8350_SLAVE_PMU_WRAPPER_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg = { + .name = "qhs_qdss_cfg", + .id = SM8350_SLAVE_QDSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qspi = { + .name = "qhs_qspi", + .id = SM8350_SLAVE_QSPI_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup0 = { + .name = "qhs_qup0", + .id = SM8350_SLAVE_QUP_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup1 = { + .name = "qhs_qup1", + .id = SM8350_SLAVE_QUP_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_qup2 = { + .name = "qhs_qup2", + .id = SM8350_SLAVE_QUP_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc2 = { + .name = "qhs_sdc2", + .id = SM8350_SLAVE_SDCC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_sdc4 = { + .name = "qhs_sdc4", + .id = SM8350_SLAVE_SDCC_4, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_security = { + .name = "qhs_security", + .id = SM8350_SLAVE_SECURITY, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_spss_cfg = { + .name = "qhs_spss_cfg", + .id = SM8350_SLAVE_SPSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tcsr = { + .name = "qhs_tcsr", + .id = SM8350_SLAVE_TCSR, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_tlmm = { + .name = "qhs_tlmm", + .id = SM8350_SLAVE_TLMM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_card_cfg = { + .name = "qhs_ufs_card_cfg", + .id = SM8350_SLAVE_UFS_CARD_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg = { + .name = "qhs_ufs_mem_cfg", + .id = SM8350_SLAVE_UFS_MEM_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_0 = { + .name = "qhs_usb3_0", + .id = SM8350_SLAVE_USB3_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_usb3_1 = { + .name = "qhs_usb3_1", + .id = SM8350_SLAVE_USB3_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_venus_cfg = { + .name = "qhs_venus_cfg", + .id = SM8350_SLAVE_VENUS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg = { + .name = "qhs_vsense_ctrl_cfg", + .id = SM8350_SLAVE_VSENSE_CTRL_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a1_noc_cfg = { + .name = "qns_a1_noc_cfg", + .id = SM8350_SLAVE_A1NOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_a2_noc_cfg = { + .name = "qns_a2_noc_cfg", + .id = SM8350_SLAVE_A2NOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_ddrss_cfg = { + .name = "qns_ddrss_cfg", + .id = SM8350_SLAVE_DDRSS_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mnoc_cfg = { + .name = "qns_mnoc_cfg", + .id = SM8350_SLAVE_CNOC_MNOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_snoc_cfg = { + .name = "qns_snoc_cfg", + .id = SM8350_SLAVE_SNOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qxs_boot_imem = { + .name = "qxs_boot_imem", + .id = SM8350_SLAVE_BOOT_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_imem = { + .name = "qxs_imem", + .id = SM8350_SLAVE_IMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qxs_pimem = { + .name = "qxs_pimem", + .id = SM8350_SLAVE_PIMEM, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_cnoc = { + .name = "srvc_cnoc", + .id = SM8350_SLAVE_SERVICE_CNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_pcie_0 = { + .name = "xs_pcie_0", + .id = SM8350_SLAVE_PCIE_0, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_pcie_1 = { + .name = "xs_pcie_1", + .id = SM8350_SLAVE_PCIE_1, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node xs_qdss_stm = { + .name = "xs_qdss_stm", + .id = SM8350_SLAVE_QDSS_STM, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg = { + .name = "xs_sys_tcu_cfg", + .id = SM8350_SLAVE_TCU, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node qhs_llcc = { + .name = "qhs_llcc", + .id = SM8350_SLAVE_LLCC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc = { + .name = "qns_gemnoc", + .id = SM8350_SLAVE_GEM_NOC_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { + .name = "qhs_mdsp_ms_mpu_cfg", + .id = SM8350_SLAVE_MSS_PROC_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { + .name = "qhs_modem_ms_mpu_cfg", + .id = SM8350_SLAVE_MCDMA_MS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc = { + .name = "qns_gem_noc_cnoc", + .id = SM8350_SLAVE_GEM_NOC_CNOC, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_GEM_NOC_CNOC }, +}; + +static struct qcom_icc_node qns_llcc = { + .name = "qns_llcc", + .id = SM8350_SLAVE_LLCC, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_LLCC }, +}; + +static struct qcom_icc_node qns_pcie = { + .name = "qns_pcie", + .id = SM8350_SLAVE_MEM_NOC_PCIE_SNOC, + .channels = 1, + .buswidth = 8, +}; + +static struct qcom_icc_node srvc_even_gemnoc = { + .name = "srvc_even_gemnoc", + .id = SM8350_SLAVE_SERVICE_GEM_NOC_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_odd_gemnoc = { + .name = "srvc_odd_gemnoc", + .id = SM8350_SLAVE_SERVICE_GEM_NOC_2, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_sys_gemnoc = { + .name = "srvc_sys_gemnoc", + .id = SM8350_SLAVE_SERVICE_GEM_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_core = { + .name = "qhs_lpass_core", + .id = SM8350_SLAVE_LPASS_CORE_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_lpi = { + .name = "qhs_lpass_lpi", + .id = SM8350_SLAVE_LPASS_LPI_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_mpu = { + .name = "qhs_lpass_mpu", + .id = SM8350_SLAVE_LPASS_MPU_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qhs_lpass_top = { + .name = "qhs_lpass_top", + .id = SM8350_SLAVE_LPASS_TOP_CFG, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_aml_noc = { + .name = "srvc_niu_aml_noc", + .id = SM8350_SLAVE_SERVICES_LPASS_AML_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node srvc_niu_lpass_agnoc = { + .name = "srvc_niu_lpass_agnoc", + .id = SM8350_SLAVE_SERVICE_LPASS_AG_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node ebi = { + .name = "ebi", + .id = SM8350_SLAVE_EBI1, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf = { + .name = "qns_mem_noc_hf", + .id = SM8350_SLAVE_MNOC_HF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_HF_MEM_NOC }, +}; + +static struct qcom_icc_node qns_mem_noc_sf = { + .name = "qns_mem_noc_sf", + .id = SM8350_SLAVE_MNOC_SF_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_mnoc = { + .name = "srvc_mnoc", + .id = SM8350_SLAVE_SERVICE_MNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_nsp_gemnoc = { + .name = "qns_nsp_gemnoc", + .id = SM8350_SLAVE_CDSP_MEM_NOC, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_COMPUTE_NOC }, +}; + +static struct qcom_icc_node service_nsp_noc = { + .name = "service_nsp_noc", + .id = SM8350_SLAVE_SERVICE_NSP_NOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_gemnoc_gc = { + .name = "qns_gemnoc_gc", + .id = SM8350_SLAVE_SNOC_GEM_NOC_GC, + .channels = 1, + .buswidth = 8, + .num_links = 1, + .links = { SM8350_MASTER_SNOC_GC_MEM_NOC }, +}; + +static struct qcom_icc_node qns_gemnoc_sf = { + .name = "qns_gemnoc_sf", + .id = SM8350_SLAVE_SNOC_GEM_NOC_SF, + .channels = 1, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_SNOC_SF_MEM_NOC }, +}; + +static struct qcom_icc_node srvc_snoc = { + .name = "srvc_snoc", + .id = SM8350_SLAVE_SERVICE_SNOC, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_llcc_disp = { + .name = "qns_llcc_disp", + .id = SM8350_SLAVE_LLCC_DISP, + .channels = 4, + .buswidth = 16, + .num_links = 1, + .links = { SM8350_MASTER_LLCC_DISP }, +}; + +static struct qcom_icc_node ebi_disp = { + .name = "ebi_disp", + .id = SM8350_SLAVE_EBI1_DISP, + .channels = 4, + .buswidth = 4, +}; + +static struct qcom_icc_node qns_mem_noc_hf_disp = { + .name = "qns_mem_noc_hf_disp", + .id = SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_HF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_node qns_mem_noc_sf_disp = { + .name = "qns_mem_noc_sf_disp", + .id = SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP, + .channels = 2, + .buswidth = 32, + .num_links = 1, + .links = { SM8350_MASTER_MNOC_SF_MEM_NOC_DISP }, +}; + +static struct qcom_icc_bcm bcm_acv = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_ce0 = { + .name = "CE0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_crypto }, +}; + +static struct qcom_icc_bcm bcm_cn0 = { + .name = "CN0", + .keepalive = true, + .num_nodes = 2, + .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, +}; + +static struct qcom_icc_bcm bcm_cn1 = { + .name = "CN1", + .keepalive = false, + .num_nodes = 47, + .nodes = { &xm_qdss_dap, + &qhs_ahb2phy0, + &qhs_ahb2phy1, + &qhs_aoss, + &qhs_apss, + &qhs_camera_cfg, + &qhs_clk_ctl, + &qhs_compute_cfg, + &qhs_cpr_cx, + &qhs_cpr_mmcx, + &qhs_cpr_mx, + &qhs_crypto0_cfg, + &qhs_cx_rdpm, + &qhs_dcc_cfg, + &qhs_display_cfg, + &qhs_gpuss_cfg, + &qhs_hwkm, + &qhs_imem_cfg, + &qhs_ipa, + &qhs_ipc_router, + &qhs_mss_cfg, + &qhs_mx_rdpm, + &qhs_pcie0_cfg, + &qhs_pcie1_cfg, + &qhs_pimem_cfg, + &qhs_pka_wrapper_cfg, + &qhs_pmu_wrapper_cfg, + &qhs_qdss_cfg, + &qhs_qup0, + &qhs_qup1, + &qhs_qup2, + &qhs_security, + &qhs_spss_cfg, + &qhs_tcsr, + &qhs_tlmm, + &qhs_ufs_card_cfg, + &qhs_ufs_mem_cfg, + &qhs_usb3_0, + &qhs_usb3_1, + &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, + &qns_a1_noc_cfg, + &qns_a2_noc_cfg, + &qns_ddrss_cfg, + &qns_mnoc_cfg, + &qns_snoc_cfg, + &srvc_cnoc + }, +}; + +static struct qcom_icc_bcm bcm_cn2 = { + .name = "CN2", + .keepalive = false, + .num_nodes = 5, + .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 }, +}; + +static struct qcom_icc_bcm bcm_co0 = { + .name = "CO0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_nsp_gemnoc }, +}; + +static struct qcom_icc_bcm bcm_co3 = { + .name = "CO3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_nsp }, +}; + +static struct qcom_icc_bcm bcm_mc0 = { + .name = "MC0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 = { + .name = "MM0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 = { + .name = "MM1", + .keepalive = false, + .num_nodes = 3, + .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, +}; + +static struct qcom_icc_bcm bcm_mm4 = { + .name = "MM4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_mm5 = { + .name = "MM5", + .keepalive = false, + .num_nodes = 6, + .nodes = { &qnm_camnoc_icp, + &qnm_camnoc_sf, + &qnm_video0, + &qnm_video1, + &qnm_video_cvp, + &qxm_rot + }, +}; + +static struct qcom_icc_bcm bcm_sh0 = { + .name = "SH0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh2 = { + .name = "SH2", + .keepalive = false, + .num_nodes = 2, + .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, +}; + +static struct qcom_icc_bcm bcm_sh3 = { + .name = "SH3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_cmpnoc }, +}; + +static struct qcom_icc_bcm bcm_sh4 = { + .name = "SH4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &chm_apps }, +}; + +static struct qcom_icc_bcm bcm_sn0 = { + .name = "SN0", + .keepalive = true, + .num_nodes = 1, + .nodes = { &qns_gemnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn2 = { + .name = "SN2", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_gemnoc_gc }, +}; + +static struct qcom_icc_bcm bcm_sn3 = { + .name = "SN3", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxs_pimem }, +}; + +static struct qcom_icc_bcm bcm_sn4 = { + .name = "SN4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xs_qdss_stm }, +}; + +static struct qcom_icc_bcm bcm_sn5 = { + .name = "SN5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xm_pcie3_0 }, +}; + +static struct qcom_icc_bcm bcm_sn6 = { + .name = "SN6", + .keepalive = false, + .num_nodes = 1, + .nodes = { &xm_pcie3_1 }, +}; + +static struct qcom_icc_bcm bcm_sn7 = { + .name = "SN7", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn8 = { + .name = "SN8", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_bcm bcm_sn14 = { + .name = "SN14", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_pcie_mem_noc }, +}; + +static struct qcom_icc_bcm bcm_acv_disp = { + .name = "ACV", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mc0_disp = { + .name = "MC0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &ebi_disp }, +}; + +static struct qcom_icc_bcm bcm_mm0_disp = { + .name = "MM0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_hf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm1_disp = { + .name = "MM1", + .keepalive = false, + .num_nodes = 2, + .nodes = { &qxm_mdp0_disp, &qxm_mdp1_disp }, +}; + +static struct qcom_icc_bcm bcm_mm4_disp = { + .name = "MM4", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_mem_noc_sf_disp }, +}; + +static struct qcom_icc_bcm bcm_mm5_disp = { + .name = "MM5", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qxm_rot_disp }, +}; + +static struct qcom_icc_bcm bcm_sh0_disp = { + .name = "SH0", + .keepalive = false, + .num_nodes = 1, + .nodes = { &qns_llcc_disp }, +}; static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { }; diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c index e64c214b4020..eb7e17df32ba 100644 --- a/drivers/interconnect/qcom/sm8450.c +++ b/drivers/interconnect/qcom/sm8450.c @@ -8,7 +8,9 @@ #include <linux/interconnect.h> #include <linux/interconnect-provider.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> +#include <linux/property.h> #include <dt-bindings/interconnect/qcom,sm8450.h> #include "bcm-voter.h" @@ -1886,6 +1888,7 @@ static struct platform_driver qnoc_driver = { .driver = { .name = "qnoc-sm8450", .of_match_table = qnoc_of_match, + .sync_state = icc_sync_state, }, }; diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c index 0864ed285375..a10c8b6549ee 100644 --- a/drivers/interconnect/qcom/sm8550.c +++ b/drivers/interconnect/qcom/sm8550.c @@ -10,7 +10,9 @@ #include <linux/interconnect.h> #include <linux/interconnect-provider.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/mod_devicetable.h> +#include <linux/platform_device.h> +#include <linux/property.h> #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> #include "bcm-voter.h" diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c index 24bc994e1a12..16a145a3c914 100644 --- a/drivers/interconnect/qcom/smd-rpm.c +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -8,8 +8,6 @@ #include <linux/interconnect-provider.h> #include <linux/module.h> -#include <linux/of.h> -#include <linux/of_platform.h> #include <linux/platform_device.h> #include <linux/soc/qcom/smd-rpm.h> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 75e427f124b2..cadd4a820c03 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -496,6 +496,7 @@ config HISI_HIKEY_USB config OPEN_DICE tristate "Open Profile for DICE driver" depends on OF_RESERVED_MEM + depends on HAS_IOMEM help This driver exposes a DICE reserved memory region to userspace via a character device. The memory region contains Compound Device diff --git a/drivers/misc/atmel-ssc.c b/drivers/misc/atmel-ssc.c index 7f9f562d6433..ee590c4a1537 100644 --- a/drivers/misc/atmel-ssc.c +++ b/drivers/misc/atmel-ssc.c @@ -212,8 +212,7 @@ static int ssc_probe(struct platform_device *pdev) of_property_read_bool(np, "atmel,clk-from-rk-pin"); } - regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ssc->regs = devm_ioremap_resource(&pdev->dev, regs); + ssc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); if (IS_ERR(ssc->regs)) return PTR_ERR(ssc->regs); diff --git a/drivers/misc/bcm-vk/bcm_vk.h b/drivers/misc/bcm-vk/bcm_vk.h index 25d51222eedf..386884c2a263 100644 --- a/drivers/misc/bcm-vk/bcm_vk.h +++ b/drivers/misc/bcm-vk/bcm_vk.h @@ -340,7 +340,7 @@ struct bcm_vk_proc_mon_info { }; struct bcm_vk_hb_ctrl { - struct timer_list timer; + struct delayed_work work; u32 last_uptime; u32 lost_cnt; }; diff --git a/drivers/misc/bcm-vk/bcm_vk_msg.c b/drivers/misc/bcm-vk/bcm_vk_msg.c index 3c081504f38c..e17d81231ea6 100644 --- a/drivers/misc/bcm-vk/bcm_vk_msg.c +++ b/drivers/misc/bcm-vk/bcm_vk_msg.c @@ -137,11 +137,11 @@ void bcm_vk_set_host_alert(struct bcm_vk *vk, u32 bit_mask) #define BCM_VK_HB_TIMER_VALUE (BCM_VK_HB_TIMER_S * HZ) #define BCM_VK_HB_LOST_MAX (27 / BCM_VK_HB_TIMER_S) -static void bcm_vk_hb_poll(struct timer_list *t) +static void bcm_vk_hb_poll(struct work_struct *work) { u32 uptime_s; - struct bcm_vk_hb_ctrl *hb = container_of(t, struct bcm_vk_hb_ctrl, - timer); + struct bcm_vk_hb_ctrl *hb = container_of(to_delayed_work(work), struct bcm_vk_hb_ctrl, + work); struct bcm_vk *vk = container_of(hb, struct bcm_vk, hb_ctrl); if (bcm_vk_drv_access_ok(vk) && hb_mon_is_on()) { @@ -177,22 +177,22 @@ static void bcm_vk_hb_poll(struct timer_list *t) bcm_vk_set_host_alert(vk, ERR_LOG_HOST_HB_FAIL); } /* re-arm timer */ - mod_timer(&hb->timer, jiffies + BCM_VK_HB_TIMER_VALUE); + schedule_delayed_work(&hb->work, BCM_VK_HB_TIMER_VALUE); } void bcm_vk_hb_init(struct bcm_vk *vk) { struct bcm_vk_hb_ctrl *hb = &vk->hb_ctrl; - timer_setup(&hb->timer, bcm_vk_hb_poll, 0); - mod_timer(&hb->timer, jiffies + BCM_VK_HB_TIMER_VALUE); + INIT_DELAYED_WORK(&hb->work, bcm_vk_hb_poll); + schedule_delayed_work(&hb->work, BCM_VK_HB_TIMER_VALUE); } void bcm_vk_hb_deinit(struct bcm_vk *vk) { struct bcm_vk_hb_ctrl *hb = &vk->hb_ctrl; - del_timer(&hb->timer); + cancel_delayed_work_sync(&hb->work); } static void bcm_vk_msgid_bitmap_clear(struct bcm_vk *vk, diff --git a/drivers/misc/cxl/base.c b/drivers/misc/cxl/base.c index cc0caf9192dc..b054562c046e 100644 --- a/drivers/misc/cxl/base.c +++ b/drivers/misc/cxl/base.c @@ -7,6 +7,7 @@ #include <linux/rcupdate.h> #include <asm/errno.h> #include <misc/cxl-base.h> +#include <linux/of.h> #include <linux/of_platform.h> #include "cxl.h" diff --git a/drivers/misc/eeprom/idt_89hpesx.c b/drivers/misc/eeprom/idt_89hpesx.c index 740c06382b83..1d1f30b5c426 100644 --- a/drivers/misc/eeprom/idt_89hpesx.c +++ b/drivers/misc/eeprom/idt_89hpesx.c @@ -913,15 +913,9 @@ static ssize_t idt_dbgfs_csr_write(struct file *filep, const char __user *ubuf, return 0; /* Copy data from User-space */ - buf = kmalloc(count + 1, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - if (copy_from_user(buf, ubuf, count)) { - ret = -EFAULT; - goto free_buf; - } - buf[count] = 0; + buf = memdup_user_nul(ubuf, count); + if (IS_ERR(buf)) + return PTR_ERR(buf); /* Find position of colon in the buffer */ colon_ch = strnchr(buf, count, ':'); @@ -1294,14 +1288,15 @@ static int idt_create_sysfs_files(struct idt_89hpesx_dev *pdev) return 0; } - /* Allocate memory for attribute file */ - pdev->ee_file = devm_kmalloc(dev, sizeof(*pdev->ee_file), GFP_KERNEL); + /* + * Allocate memory for attribute file and copy the declared EEPROM attr + * structure to change some of fields + */ + pdev->ee_file = devm_kmemdup(dev, &bin_attr_eeprom, + sizeof(*pdev->ee_file), GFP_KERNEL); if (!pdev->ee_file) return -ENOMEM; - /* Copy the declared EEPROM attr structure to change some of fields */ - memcpy(pdev->ee_file, &bin_attr_eeprom, sizeof(*pdev->ee_file)); - /* In case of read-only EEPROM get rid of write ability */ if (pdev->eero) { pdev->ee_file->attr.mode &= ~0200; diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index 9666d28037e1..a66b7c111cd5 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -13,6 +13,7 @@ #include <linux/module.h> #include <linux/of_address.h> #include <linux/of.h> +#include <linux/platform_device.h> #include <linux/sort.h> #include <linux/of_platform.h> #include <linux/rpmsg.h> @@ -756,6 +757,7 @@ static int fastrpc_map_create(struct fastrpc_user *fl, int fd, { struct fastrpc_session_ctx *sess = fl->sctx; struct fastrpc_map *map = NULL; + struct sg_table *table; int err = 0; if (!fastrpc_map_lookup(fl, fd, ppmap, true)) @@ -783,11 +785,12 @@ static int fastrpc_map_create(struct fastrpc_user *fl, int fd, goto attach_err; } - map->table = dma_buf_map_attachment_unlocked(map->attach, DMA_BIDIRECTIONAL); - if (IS_ERR(map->table)) { - err = PTR_ERR(map->table); + table = dma_buf_map_attachment_unlocked(map->attach, DMA_BIDIRECTIONAL); + if (IS_ERR(table)) { + err = PTR_ERR(table); goto map_err; } + map->table = table; if (attr & FASTRPC_ATTR_SECUREMAP) { map->phys = sg_phys(map->table->sgl); @@ -1322,13 +1325,18 @@ static int fastrpc_init_create_static_process(struct fastrpc_user *fl, return 0; err_invoke: if (fl->cctx->vmcount) { - struct qcom_scm_vmperm perm; + u64 src_perms = 0; + struct qcom_scm_vmperm dst_perms; + u32 i; + + for (i = 0; i < fl->cctx->vmcount; i++) + src_perms |= BIT(fl->cctx->vmperms[i].vmid); - perm.vmid = QCOM_SCM_VMID_HLOS; - perm.perm = QCOM_SCM_PERM_RWX; + dst_perms.vmid = QCOM_SCM_VMID_HLOS; + dst_perms.perm = QCOM_SCM_PERM_RWX; err = qcom_scm_assign_mem(fl->cctx->remote_heap->phys, (u64)fl->cctx->remote_heap->size, - &fl->cctx->perms, &perm, 1); + &src_perms, &dst_perms, 1); if (err) dev_err(fl->sctx->dev, "Failed to assign memory phys 0x%llx size 0x%llx err %d", fl->cctx->remote_heap->phys, fl->cctx->remote_heap->size, err); @@ -1866,7 +1874,11 @@ static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) return -EINVAL; } - err = fastrpc_buf_alloc(fl, fl->sctx->dev, req.size, &buf); + if (req.flags == ADSP_MMAP_REMOTE_HEAP_ADDR) + err = fastrpc_remote_heap_alloc(fl, dev, req.size, &buf); + else + err = fastrpc_buf_alloc(fl, dev, req.size, &buf); + if (err) { dev_err(dev, "failed to allocate buffer\n"); return err; @@ -1905,12 +1917,8 @@ static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) /* Add memory to static PD pool, protection thru hypervisor */ if (req.flags == ADSP_MMAP_REMOTE_HEAP_ADDR && fl->cctx->vmcount) { - struct qcom_scm_vmperm perm; - - perm.vmid = QCOM_SCM_VMID_HLOS; - perm.perm = QCOM_SCM_PERM_RWX; - err = qcom_scm_assign_mem(buf->phys, buf->size, - &fl->cctx->perms, &perm, 1); + err = qcom_scm_assign_mem(buf->phys, (u64)buf->size, + &fl->cctx->perms, fl->cctx->vmperms, fl->cctx->vmcount); if (err) { dev_err(fl->sctx->dev, "Failed to assign memory phys 0x%llx size 0x%llx err %d", buf->phys, buf->size, err); diff --git a/drivers/misc/genwqe/card_base.c b/drivers/misc/genwqe/card_base.c index b03010810b89..224a7e97cbea 100644 --- a/drivers/misc/genwqe/card_base.c +++ b/drivers/misc/genwqe/card_base.c @@ -42,7 +42,7 @@ MODULE_VERSION(DRV_VERSION); MODULE_LICENSE("GPL"); static char genwqe_driver_name[] = GENWQE_DEVNAME; -static struct class *class_genwqe; + static struct dentry *debugfs_genwqe; static struct genwqe_dev *genwqe_devices[GENWQE_CARD_NO_MAX]; @@ -105,6 +105,26 @@ static const struct pci_device_id genwqe_device_table[] = { MODULE_DEVICE_TABLE(pci, genwqe_device_table); /** + * genwqe_devnode() - Set default access mode for genwqe devices. + * @dev: Pointer to device (unused) + * @mode: Carrier to pass-back given mode (permissions) + * + * Default mode should be rw for everybody. Do not change default + * device name. + */ +static char *genwqe_devnode(const struct device *dev, umode_t *mode) +{ + if (mode) + *mode = 0666; + return NULL; +} + +static const struct class class_genwqe = { + .name = GENWQE_DEVNAME, + .devnode = genwqe_devnode, +}; + +/** * genwqe_dev_alloc() - Create and prepare a new card descriptor * * Return: Pointer to card descriptor, or ERR_PTR(err) on error @@ -126,7 +146,7 @@ static struct genwqe_dev *genwqe_dev_alloc(void) return ERR_PTR(-ENOMEM); cd->card_idx = i; - cd->class_genwqe = class_genwqe; + cd->class_genwqe = &class_genwqe; cd->debugfs_genwqe = debugfs_genwqe; /* @@ -1340,35 +1360,18 @@ static struct pci_driver genwqe_driver = { }; /** - * genwqe_devnode() - Set default access mode for genwqe devices. - * @dev: Pointer to device (unused) - * @mode: Carrier to pass-back given mode (permissions) - * - * Default mode should be rw for everybody. Do not change default - * device name. - */ -static char *genwqe_devnode(const struct device *dev, umode_t *mode) -{ - if (mode) - *mode = 0666; - return NULL; -} - -/** * genwqe_init_module() - Driver registration and initialization */ static int __init genwqe_init_module(void) { int rc; - class_genwqe = class_create(GENWQE_DEVNAME); - if (IS_ERR(class_genwqe)) { + rc = class_register(&class_genwqe); + if (rc) { pr_err("[%s] create class failed\n", __func__); return -ENOMEM; } - class_genwqe->devnode = genwqe_devnode; - debugfs_genwqe = debugfs_create_dir(GENWQE_DEVNAME, NULL); rc = pci_register_driver(&genwqe_driver); @@ -1381,7 +1384,7 @@ static int __init genwqe_init_module(void) err_out0: debugfs_remove(debugfs_genwqe); - class_destroy(class_genwqe); + class_unregister(&class_genwqe); return rc; } @@ -1392,7 +1395,7 @@ static void __exit genwqe_exit_module(void) { pci_unregister_driver(&genwqe_driver); debugfs_remove(debugfs_genwqe); - class_destroy(class_genwqe); + class_unregister(&class_genwqe); } module_init(genwqe_init_module); diff --git a/drivers/misc/genwqe/card_base.h b/drivers/misc/genwqe/card_base.h index 0e902977d35f..d700266f2cd0 100644 --- a/drivers/misc/genwqe/card_base.h +++ b/drivers/misc/genwqe/card_base.h @@ -289,7 +289,7 @@ struct genwqe_dev { /* char device */ dev_t devnum_genwqe; /* major/minor num card */ - struct class *class_genwqe; /* reference to class object */ + const struct class *class_genwqe; /* reference to class object */ struct device *dev; /* for device creation */ struct cdev cdev_genwqe; /* char device for card */ diff --git a/drivers/misc/hi6421v600-irq.c b/drivers/misc/hi6421v600-irq.c index caa3de37698b..b075d803a2c2 100644 --- a/drivers/misc/hi6421v600-irq.c +++ b/drivers/misc/hi6421v600-irq.c @@ -244,10 +244,8 @@ static int hi6421v600_irq_probe(struct platform_device *pdev) pmic_pdev = container_of(pmic_dev, struct platform_device, dev); priv->irq = platform_get_irq(pmic_pdev, 0); - if (priv->irq < 0) { - dev_err(dev, "Error %d when getting IRQs\n", priv->irq); + if (priv->irq < 0) return priv->irq; - } platform_set_drvdata(pdev, priv); diff --git a/drivers/misc/hpilo.c b/drivers/misc/hpilo.c index 2fde8d63c5fe..f1b74d3f8958 100644 --- a/drivers/misc/hpilo.c +++ b/drivers/misc/hpilo.c @@ -25,7 +25,9 @@ #include <linux/slab.h> #include "hpilo.h" -static struct class *ilo_class; +static const struct class ilo_class = { + .name = "iLO", +}; static unsigned int ilo_major; static unsigned int max_ccb = 16; static char ilo_hwdev[MAX_ILO_DEV]; @@ -746,7 +748,7 @@ static void ilo_remove(struct pci_dev *pdev) minor = MINOR(ilo_hw->cdev.dev); for (i = minor; i < minor + max_ccb; i++) - device_destroy(ilo_class, MKDEV(ilo_major, i)); + device_destroy(&ilo_class, MKDEV(ilo_major, i)); cdev_del(&ilo_hw->cdev); ilo_disable_interrupts(ilo_hw); @@ -839,7 +841,7 @@ static int ilo_probe(struct pci_dev *pdev, for (minor = 0 ; minor < max_ccb; minor++) { struct device *dev; - dev = device_create(ilo_class, &pdev->dev, + dev = device_create(&ilo_class, &pdev->dev, MKDEV(ilo_major, minor), NULL, "hpilo!d%dccb%d", devnum, minor); if (IS_ERR(dev)) @@ -882,11 +884,9 @@ static int __init ilo_init(void) int error; dev_t dev; - ilo_class = class_create("iLO"); - if (IS_ERR(ilo_class)) { - error = PTR_ERR(ilo_class); + error = class_register(&ilo_class); + if (error) goto out; - } error = alloc_chrdev_region(&dev, 0, MAX_OPEN, ILO_NAME); if (error) @@ -902,7 +902,7 @@ static int __init ilo_init(void) chr_remove: unregister_chrdev_region(dev, MAX_OPEN); class_destroy: - class_destroy(ilo_class); + class_unregister(&ilo_class); out: return error; } @@ -911,7 +911,7 @@ static void __exit ilo_exit(void) { pci_unregister_driver(&ilo_driver); unregister_chrdev_region(MKDEV(ilo_major, 0), MAX_OPEN); - class_destroy(ilo_class); + class_unregister(&ilo_class); } MODULE_VERSION("1.5.0"); diff --git a/drivers/misc/lis3lv02d/lis3lv02d.c b/drivers/misc/lis3lv02d/lis3lv02d.c index 299d316f1bda..49868a45c0ad 100644 --- a/drivers/misc/lis3lv02d/lis3lv02d.c +++ b/drivers/misc/lis3lv02d/lis3lv02d.c @@ -26,7 +26,7 @@ #include <linux/miscdevice.h> #include <linux/pm_runtime.h> #include <linux/atomic.h> -#include <linux/of_device.h> +#include <linux/of.h> #include "lis3lv02d.h" #define DRIVER_NAME "lis3lv02d" diff --git a/drivers/misc/mchp_pci1xxxx/Kconfig b/drivers/misc/mchp_pci1xxxx/Kconfig index 4abb47de7219..64e457581fb4 100644 --- a/drivers/misc/mchp_pci1xxxx/Kconfig +++ b/drivers/misc/mchp_pci1xxxx/Kconfig @@ -2,6 +2,7 @@ config GP_PCI1XXXX tristate "Microchip PCI1XXXX PCIe to GPIO Expander + OTP/EEPROM manager" depends on PCI depends on GPIOLIB + depends on NVMEM_SYSFS select GPIOLIB_IRQCHIP select AUXILIARY_BUS help diff --git a/drivers/misc/mchp_pci1xxxx/Makefile b/drivers/misc/mchp_pci1xxxx/Makefile index fc4615cfe28b..ae31251dab37 100644 --- a/drivers/misc/mchp_pci1xxxx/Makefile +++ b/drivers/misc/mchp_pci1xxxx/Makefile @@ -1 +1 @@ -obj-$(CONFIG_GP_PCI1XXXX) := mchp_pci1xxxx_gp.o mchp_pci1xxxx_gpio.o +obj-$(CONFIG_GP_PCI1XXXX) := mchp_pci1xxxx_gp.o mchp_pci1xxxx_gpio.o mchp_pci1xxxx_otpe2p.o diff --git a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c new file mode 100644 index 000000000000..16695cb5e69c --- /dev/null +++ b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_otpe2p.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2022-2023 Microchip Technology Inc. +// PCI1xxxx OTP/EEPROM driver + +#include <linux/auxiliary_bus.h> +#include <linux/device.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/nvmem-provider.h> + +#include "mchp_pci1xxxx_gp.h" + +#define AUX_DRIVER_NAME "PCI1xxxxOTPE2P" +#define EEPROM_NAME "pci1xxxx_eeprom" +#define OTP_NAME "pci1xxxx_otp" + +#define PERI_PF3_SYSTEM_REG_ADDR_BASE 0x2000 +#define PERI_PF3_SYSTEM_REG_LENGTH 0x4000 + +#define EEPROM_SIZE_BYTES 8192 +#define OTP_SIZE_BYTES 8192 + +#define CONFIG_REG_ADDR_BASE 0 +#define EEPROM_REG_ADDR_BASE 0x0E00 +#define OTP_REG_ADDR_BASE 0x1000 + +#define MMAP_OTP_OFFSET(x) (OTP_REG_ADDR_BASE + (x)) +#define MMAP_EEPROM_OFFSET(x) (EEPROM_REG_ADDR_BASE + (x)) +#define MMAP_CFG_OFFSET(x) (CONFIG_REG_ADDR_BASE + (x)) + +#define EEPROM_CMD_REG 0x00 +#define EEPROM_DATA_REG 0x04 + +#define EEPROM_CMD_EPC_WRITE (BIT(29) | BIT(28)) +#define EEPROM_CMD_EPC_TIMEOUT_BIT BIT(17) +#define EEPROM_CMD_EPC_BUSY_BIT BIT(31) + +#define STATUS_READ_DELAY_US 1 +#define STATUS_READ_TIMEOUT_US 20000 + +#define OTP_ADDR_HIGH_OFFSET 0x04 +#define OTP_ADDR_LOW_OFFSET 0x08 +#define OTP_PRGM_DATA_OFFSET 0x10 +#define OTP_PRGM_MODE_OFFSET 0x14 +#define OTP_RD_DATA_OFFSET 0x18 +#define OTP_FUNC_CMD_OFFSET 0x20 +#define OTP_CMD_GO_OFFSET 0x28 +#define OTP_PASS_FAIL_OFFSET 0x2C +#define OTP_STATUS_OFFSET 0x30 + +#define OTP_FUNC_RD_BIT BIT(0) +#define OTP_FUNC_PGM_BIT BIT(1) +#define OTP_CMD_GO_BIT BIT(0) +#define OTP_STATUS_BUSY_BIT BIT(0) +#define OTP_PGM_MODE_BYTE_BIT BIT(0) +#define OTP_FAIL_BIT BIT(0) + +#define OTP_PWR_DN_BIT BIT(0) +#define OTP_PWR_DN_OFFSET 0x00 + +#define CFG_SYS_LOCK_OFFSET 0xA0 +#define CFG_SYS_LOCK_PF3 BIT(5) + +#define BYTE_LOW (GENMASK(7, 0)) +#define BYTE_HIGH (GENMASK(12, 8)) + +struct pci1xxxx_otp_eeprom_device { + struct auxiliary_device *pdev; + void __iomem *reg_base; + struct nvmem_config nvmem_config_eeprom; + struct nvmem_device *nvmem_eeprom; + struct nvmem_config nvmem_config_otp; + struct nvmem_device *nvmem_otp; +}; + +static int set_sys_lock(struct pci1xxxx_otp_eeprom_device *priv) +{ + void __iomem *sys_lock = priv->reg_base + + MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET); + u8 data; + + writel(CFG_SYS_LOCK_PF3, sys_lock); + data = readl(sys_lock); + if (data != CFG_SYS_LOCK_PF3) + return -EPERM; + + return 0; +} + +static void release_sys_lock(struct pci1xxxx_otp_eeprom_device *priv) +{ + void __iomem *sys_lock = priv->reg_base + + MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET); + writel(0, sys_lock); +} + +static bool is_eeprom_responsive(struct pci1xxxx_otp_eeprom_device *priv) +{ + void __iomem *rb = priv->reg_base; + u32 regval; + int ret; + + writel(EEPROM_CMD_EPC_TIMEOUT_BIT, + rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + writel(EEPROM_CMD_EPC_BUSY_BIT, + rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + + /* Wait for the EPC_BUSY bit to get cleared or timeout bit to get set*/ + ret = read_poll_timeout(readl, regval, !(regval & EEPROM_CMD_EPC_BUSY_BIT), + STATUS_READ_DELAY_US, STATUS_READ_TIMEOUT_US, + true, rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + + /* Return failure if either of software or hardware timeouts happen */ + if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT))) + return false; + + return true; +} + +static int pci1xxxx_eeprom_read(void *priv_t, unsigned int off, + void *buf_t, size_t count) +{ + struct pci1xxxx_otp_eeprom_device *priv = priv_t; + void __iomem *rb = priv->reg_base; + char *buf = buf_t; + u32 regval; + u32 byte; + int ret; + + if (off >= priv->nvmem_config_eeprom.size) + return -EFAULT; + + if ((off + count) > priv->nvmem_config_eeprom.size) + count = priv->nvmem_config_eeprom.size - off; + + ret = set_sys_lock(priv); + if (ret) + return ret; + + for (byte = 0; byte < count; byte++) { + writel(EEPROM_CMD_EPC_BUSY_BIT | (off + byte), rb + + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + + ret = read_poll_timeout(readl, regval, + !(regval & EEPROM_CMD_EPC_BUSY_BIT), + STATUS_READ_DELAY_US, + STATUS_READ_TIMEOUT_US, true, + rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT))) { + ret = -EIO; + goto error; + } + + buf[byte] = readl(rb + MMAP_EEPROM_OFFSET(EEPROM_DATA_REG)); + } + ret = byte; +error: + release_sys_lock(priv); + return ret; +} + +static int pci1xxxx_eeprom_write(void *priv_t, unsigned int off, + void *value_t, size_t count) +{ + struct pci1xxxx_otp_eeprom_device *priv = priv_t; + void __iomem *rb = priv->reg_base; + char *value = value_t; + u32 regval; + u32 byte; + int ret; + + if (off >= priv->nvmem_config_eeprom.size) + return -EFAULT; + + if ((off + count) > priv->nvmem_config_eeprom.size) + count = priv->nvmem_config_eeprom.size - off; + + ret = set_sys_lock(priv); + if (ret) + return ret; + + for (byte = 0; byte < count; byte++) { + writel(*(value + byte), rb + MMAP_EEPROM_OFFSET(EEPROM_DATA_REG)); + regval = EEPROM_CMD_EPC_TIMEOUT_BIT | EEPROM_CMD_EPC_WRITE | + (off + byte); + writel(regval, rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + writel(EEPROM_CMD_EPC_BUSY_BIT | regval, + rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + + ret = read_poll_timeout(readl, regval, + !(regval & EEPROM_CMD_EPC_BUSY_BIT), + STATUS_READ_DELAY_US, + STATUS_READ_TIMEOUT_US, true, + rb + MMAP_EEPROM_OFFSET(EEPROM_CMD_REG)); + if (ret < 0 || (!ret && (regval & EEPROM_CMD_EPC_TIMEOUT_BIT))) { + ret = -EIO; + goto error; + } + } + ret = byte; +error: + release_sys_lock(priv); + return ret; +} + +static void otp_device_set_address(struct pci1xxxx_otp_eeprom_device *priv, + u16 address) +{ + u16 lo, hi; + + lo = address & BYTE_LOW; + hi = (address & BYTE_HIGH) >> 8; + writew(lo, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_LOW_OFFSET)); + writew(hi, priv->reg_base + MMAP_OTP_OFFSET(OTP_ADDR_HIGH_OFFSET)); +} + +static int pci1xxxx_otp_read(void *priv_t, unsigned int off, + void *buf_t, size_t count) +{ + struct pci1xxxx_otp_eeprom_device *priv = priv_t; + void __iomem *rb = priv->reg_base; + char *buf = buf_t; + u32 regval; + u32 byte; + int ret; + u8 data; + + if (off >= priv->nvmem_config_otp.size) + return -EFAULT; + + if ((off + count) > priv->nvmem_config_otp.size) + count = priv->nvmem_config_otp.size - off; + + ret = set_sys_lock(priv); + if (ret) + return ret; + + for (byte = 0; byte < count; byte++) { + otp_device_set_address(priv, (u16)(off + byte)); + data = readl(rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET)); + writel(data | OTP_FUNC_RD_BIT, + rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET)); + data = readl(rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET)); + writel(data | OTP_CMD_GO_BIT, + rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET)); + + ret = read_poll_timeout(readl, regval, + !(regval & OTP_STATUS_BUSY_BIT), + STATUS_READ_DELAY_US, + STATUS_READ_TIMEOUT_US, true, + rb + MMAP_OTP_OFFSET(OTP_STATUS_OFFSET)); + + data = readl(rb + MMAP_OTP_OFFSET(OTP_PASS_FAIL_OFFSET)); + if (ret < 0 || data & OTP_FAIL_BIT) { + ret = -EIO; + goto error; + } + + buf[byte] = readl(rb + MMAP_OTP_OFFSET(OTP_RD_DATA_OFFSET)); + } + ret = byte; +error: + release_sys_lock(priv); + return ret; +} + +static int pci1xxxx_otp_write(void *priv_t, unsigned int off, + void *value_t, size_t count) +{ + struct pci1xxxx_otp_eeprom_device *priv = priv_t; + void __iomem *rb = priv->reg_base; + char *value = value_t; + u32 regval; + u32 byte; + int ret; + u8 data; + + if (off >= priv->nvmem_config_otp.size) + return -EFAULT; + + if ((off + count) > priv->nvmem_config_otp.size) + count = priv->nvmem_config_otp.size - off; + + ret = set_sys_lock(priv); + if (ret) + return ret; + + for (byte = 0; byte < count; byte++) { + otp_device_set_address(priv, (u16)(off + byte)); + + /* + * Set OTP_PGM_MODE_BYTE command bit in OTP_PRGM_MODE register + * to enable Byte programming + */ + data = readl(rb + MMAP_OTP_OFFSET(OTP_PRGM_MODE_OFFSET)); + writel(data | OTP_PGM_MODE_BYTE_BIT, + rb + MMAP_OTP_OFFSET(OTP_PRGM_MODE_OFFSET)); + writel(*(value + byte), rb + MMAP_OTP_OFFSET(OTP_PRGM_DATA_OFFSET)); + data = readl(rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET)); + writel(data | OTP_FUNC_PGM_BIT, + rb + MMAP_OTP_OFFSET(OTP_FUNC_CMD_OFFSET)); + data = readl(rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET)); + writel(data | OTP_CMD_GO_BIT, + rb + MMAP_OTP_OFFSET(OTP_CMD_GO_OFFSET)); + + ret = read_poll_timeout(readl, regval, + !(regval & OTP_STATUS_BUSY_BIT), + STATUS_READ_DELAY_US, + STATUS_READ_TIMEOUT_US, true, + rb + MMAP_OTP_OFFSET(OTP_STATUS_OFFSET)); + + data = readl(rb + MMAP_OTP_OFFSET(OTP_PASS_FAIL_OFFSET)); + if (ret < 0 || data & OTP_FAIL_BIT) { + ret = -EIO; + goto error; + } + } + ret = byte; +error: + release_sys_lock(priv); + return ret; +} + +static int pci1xxxx_otp_eeprom_probe(struct auxiliary_device *aux_dev, + const struct auxiliary_device_id *id) +{ + struct auxiliary_device_wrapper *aux_dev_wrapper; + struct pci1xxxx_otp_eeprom_device *priv; + struct gp_aux_data_type *pdata; + int ret; + u8 data; + + aux_dev_wrapper = container_of(aux_dev, struct auxiliary_device_wrapper, + aux_dev); + pdata = &aux_dev_wrapper->gp_aux_data; + if (!pdata) + return -EINVAL; + + priv = devm_kzalloc(&aux_dev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pdev = aux_dev; + + if (!devm_request_mem_region(&aux_dev->dev, pdata->region_start + + PERI_PF3_SYSTEM_REG_ADDR_BASE, + PERI_PF3_SYSTEM_REG_LENGTH, + aux_dev->name)) + return -ENOMEM; + + priv->reg_base = devm_ioremap(&aux_dev->dev, pdata->region_start + + PERI_PF3_SYSTEM_REG_ADDR_BASE, + PERI_PF3_SYSTEM_REG_LENGTH); + if (!priv->reg_base) + return -ENOMEM; + + ret = set_sys_lock(priv); + if (ret) + return ret; + + /* Set OTP_PWR_DN to 0 to make OTP Operational */ + data = readl(priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET)); + writel(data & ~OTP_PWR_DN_BIT, + priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET)); + + dev_set_drvdata(&aux_dev->dev, priv); + + if (is_eeprom_responsive(priv)) { + priv->nvmem_config_eeprom.type = NVMEM_TYPE_EEPROM; + priv->nvmem_config_eeprom.name = EEPROM_NAME; + priv->nvmem_config_eeprom.dev = &aux_dev->dev; + priv->nvmem_config_eeprom.owner = THIS_MODULE; + priv->nvmem_config_eeprom.reg_read = pci1xxxx_eeprom_read; + priv->nvmem_config_eeprom.reg_write = pci1xxxx_eeprom_write; + priv->nvmem_config_eeprom.priv = priv; + priv->nvmem_config_eeprom.stride = 1; + priv->nvmem_config_eeprom.word_size = 1; + priv->nvmem_config_eeprom.size = EEPROM_SIZE_BYTES; + + priv->nvmem_eeprom = devm_nvmem_register(&aux_dev->dev, + &priv->nvmem_config_eeprom); + if (IS_ERR(priv->nvmem_eeprom)) + return PTR_ERR(priv->nvmem_eeprom); + } + + release_sys_lock(priv); + + priv->nvmem_config_otp.type = NVMEM_TYPE_OTP; + priv->nvmem_config_otp.name = OTP_NAME; + priv->nvmem_config_otp.dev = &aux_dev->dev; + priv->nvmem_config_otp.owner = THIS_MODULE; + priv->nvmem_config_otp.reg_read = pci1xxxx_otp_read; + priv->nvmem_config_otp.reg_write = pci1xxxx_otp_write; + priv->nvmem_config_otp.priv = priv; + priv->nvmem_config_otp.stride = 1; + priv->nvmem_config_otp.word_size = 1; + priv->nvmem_config_otp.size = OTP_SIZE_BYTES; + + priv->nvmem_otp = devm_nvmem_register(&aux_dev->dev, + &priv->nvmem_config_otp); + if (IS_ERR(priv->nvmem_otp)) + return PTR_ERR(priv->nvmem_otp); + + return ret; +} + +static void pci1xxxx_otp_eeprom_remove(struct auxiliary_device *aux_dev) +{ + struct pci1xxxx_otp_eeprom_device *priv; + void __iomem *sys_lock; + + priv = dev_get_drvdata(&aux_dev->dev); + sys_lock = priv->reg_base + MMAP_CFG_OFFSET(CFG_SYS_LOCK_OFFSET); + writel(CFG_SYS_LOCK_PF3, sys_lock); + + /* Shut down OTP */ + writel(OTP_PWR_DN_BIT, + priv->reg_base + MMAP_OTP_OFFSET(OTP_PWR_DN_OFFSET)); + + writel(0, sys_lock); +} + +static const struct auxiliary_device_id pci1xxxx_otp_eeprom_auxiliary_id_table[] = { + {.name = "mchp_pci1xxxx_gp.gp_otp_e2p"}, + {}, +}; +MODULE_DEVICE_TABLE(auxiliary, pci1xxxx_otp_eeprom_auxiliary_id_table); + +static struct auxiliary_driver pci1xxxx_otp_eeprom_driver = { + .driver = { + .name = AUX_DRIVER_NAME, + }, + .probe = pci1xxxx_otp_eeprom_probe, + .remove = pci1xxxx_otp_eeprom_remove, + .id_table = pci1xxxx_otp_eeprom_auxiliary_id_table +}; +module_auxiliary_driver(pci1xxxx_otp_eeprom_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>"); +MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>"); +MODULE_AUTHOR("Vaibhaav Ram T.L <vaibhaavram.tl@microchip.com>"); +MODULE_DESCRIPTION("Microchip Technology Inc. PCI1xxxx OTP EEPROM Programmer"); diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index b8b716faf192..2733070acf39 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -184,6 +184,7 @@ static int mei_fwver(struct mei_cl_device *cldev) cldev->bus->fw_ver[i].hotfix = fwver->ver[i].hotfix; cldev->bus->fw_ver[i].buildno = fwver->ver[i].buildno; } + cldev->bus->fw_ver_received = 1; return ret; } @@ -237,8 +238,11 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev) { int ret; - /* No need to enable the client if nothing is needed from it */ - if (!cldev->bus->fw_f_fw_ver_supported) + /* + * No need to enable the client if nothing is needed from it. + * No need to fill in version if it is already filled in by the fix address client. + */ + if (!cldev->bus->fw_f_fw_ver_supported || cldev->bus->fw_ver_received) return; ret = mei_cldev_enable(cldev); @@ -555,8 +559,8 @@ static struct mei_fixup { MEI_FIXUP(MEI_UUID_NFC_HCI, mei_nfc), MEI_FIXUP(MEI_UUID_WD, mei_wd), MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix), - MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver), MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver), + MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver), MEI_FIXUP(MEI_UUID_HDCP, whitelist), MEI_FIXUP(MEI_UUID_ANY, vt_support), MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready), diff --git a/drivers/misc/mei/bus.c b/drivers/misc/mei/bus.c index 33ec6424dfee..2e65ce6bdec7 100644 --- a/drivers/misc/mei/bus.c +++ b/drivers/misc/mei/bus.c @@ -1329,6 +1329,7 @@ static struct mei_cl_device *mei_cl_bus_dev_alloc(struct mei_device *bus, mei_cl_bus_set_name(cldev); cldev->is_added = 0; INIT_LIST_HEAD(&cldev->bus_list); + device_enable_async_suspend(&cldev->dev); return cldev; } diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c index e63cabd0818d..6be8f1cc052c 100644 --- a/drivers/misc/mei/gsc-me.c +++ b/drivers/misc/mei/gsc-me.c @@ -312,4 +312,5 @@ module_auxiliary_driver(mei_gsc_driver); MODULE_AUTHOR("Intel Corporation"); MODULE_ALIAS("auxiliary:i915.mei-gsc"); MODULE_ALIAS("auxiliary:i915.mei-gscfi"); +MODULE_DESCRIPTION("Intel(R) Graphics System Controller"); MODULE_LICENSE("GPL"); diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c index bac8852aad51..c35e005b26be 100644 --- a/drivers/misc/mei/init.c +++ b/drivers/misc/mei/init.c @@ -142,6 +142,9 @@ int mei_reset(struct mei_device *dev) mei_hbm_reset(dev); + /* clean stale FW version */ + dev->fw_ver_received = 0; + memset(dev->rd_msg_hdr, 0, sizeof(dev->rd_msg_hdr)); if (ret) { @@ -157,7 +160,10 @@ int mei_reset(struct mei_device *dev) ret = mei_hw_start(dev); if (ret) { - dev_err(dev->dev, "hw_start failed ret = %d\n", ret); + char fw_sts_str[MEI_FW_STATUS_STR_SZ]; + + mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ); + dev_err(dev->dev, "hw_start failed ret = %d fw status = %s\n", ret, fw_sts_str); return ret; } diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c index 51876da3fd65..bb4e9eabda97 100644 --- a/drivers/misc/mei/main.c +++ b/drivers/misc/mei/main.c @@ -27,7 +27,10 @@ #include "mei_dev.h" #include "client.h" -static struct class *mei_class; +static const struct class mei_class = { + .name = "mei", +}; + static dev_t mei_devt; #define MEI_MAX_DEVS MINORMASK static DEFINE_MUTEX(mei_minor_lock); @@ -1115,7 +1118,7 @@ void mei_set_devstate(struct mei_device *dev, enum mei_dev_state state) dev->dev_state = state; - clsdev = class_find_device_by_devt(mei_class, dev->cdev.dev); + clsdev = class_find_device_by_devt(&mei_class, dev->cdev.dev); if (clsdev) { sysfs_notify(&clsdev->kobj, NULL, "dev_state"); put_device(clsdev); @@ -1232,7 +1235,7 @@ int mei_register(struct mei_device *dev, struct device *parent) goto err_dev_add; } - clsdev = device_create_with_groups(mei_class, parent, devno, + clsdev = device_create_with_groups(&mei_class, parent, devno, dev, mei_groups, "mei%d", dev->minor); @@ -1264,7 +1267,7 @@ void mei_deregister(struct mei_device *dev) mei_dbgfs_deregister(dev); - device_destroy(mei_class, devno); + device_destroy(&mei_class, devno); mei_minor_free(dev); } @@ -1274,12 +1277,9 @@ static int __init mei_init(void) { int ret; - mei_class = class_create("mei"); - if (IS_ERR(mei_class)) { - pr_err("couldn't create class\n"); - ret = PTR_ERR(mei_class); - goto err; - } + ret = class_register(&mei_class); + if (ret) + return ret; ret = alloc_chrdev_region(&mei_devt, 0, MEI_MAX_DEVS, "mei"); if (ret < 0) { @@ -1298,15 +1298,14 @@ static int __init mei_init(void) err_chrdev: unregister_chrdev_region(mei_devt, MEI_MAX_DEVS); err_class: - class_destroy(mei_class); -err: + class_unregister(&mei_class); return ret; } static void __exit mei_exit(void) { unregister_chrdev_region(mei_devt, MEI_MAX_DEVS); - class_destroy(mei_class); + class_unregister(&mei_class); mei_cl_bus_exit(); } diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h index 895011b7a0bf..cdf8a2edf0b3 100644 --- a/drivers/misc/mei/mei_dev.h +++ b/drivers/misc/mei/mei_dev.h @@ -512,6 +512,7 @@ struct mei_dev_timeouts { * @fw_ver : FW versions * * @fw_f_fw_ver_supported : fw feature: fw version supported + * @fw_ver_received : fw version received * * @me_clients_rwsem: rw lock over me_clients list * @me_clients : list of FW clients @@ -604,6 +605,7 @@ struct mei_device { struct mei_fw_version fw_ver[MEI_MAX_FW_VER_BLOCKS]; unsigned int fw_f_fw_ver_supported:1; + unsigned int fw_ver_received:1; struct rw_semaphore me_clients_rwsem; struct list_head me_clients; diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c index 3bf560bbdee0..2dcb9169e404 100644 --- a/drivers/misc/mei/pxp/mei_pxp.c +++ b/drivers/misc/mei/pxp/mei_pxp.c @@ -40,8 +40,7 @@ mei_pxp_send_message(struct device *dev, const void *message, size_t size) cldev = to_mei_cl_device(dev); - /* temporary drop const qualifier till the API is fixed */ - byte = mei_cldev_send(cldev, (u8 *)message, size); + byte = mei_cldev_send(cldev, message, size); if (byte < 0) { dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte); return byte; diff --git a/drivers/misc/qcom-coincell.c b/drivers/misc/qcom-coincell.c index 54d4f6ee8888..3c57f7429147 100644 --- a/drivers/misc/qcom-coincell.c +++ b/drivers/misc/qcom-coincell.c @@ -8,7 +8,6 @@ #include <linux/slab.h> #include <linux/of.h> #include <linux/regmap.h> -#include <linux/of_device.h> #include <linux/platform_device.h> struct qcom_coincell { diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c index 61209739dc43..e248c0a8882f 100644 --- a/drivers/misc/sram.c +++ b/drivers/misc/sram.c @@ -10,8 +10,8 @@ #include <linux/genalloc.h> #include <linux/io.h> #include <linux/list_sort.h> +#include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> diff --git a/drivers/misc/tps6594-esm.c b/drivers/misc/tps6594-esm.c index 05e2c151e632..b4d67a1a24e4 100644 --- a/drivers/misc/tps6594-esm.c +++ b/drivers/misc/tps6594-esm.c @@ -56,8 +56,7 @@ static int tps6594_esm_probe(struct platform_device *pdev) for (i = 0; i < pdev->num_resources; i++) { irq = platform_get_irq_byname(pdev, pdev->resource[i].name); if (irq < 0) - return dev_err_probe(dev, irq, "Failed to get %s irq\n", - pdev->resource[i].name); + return irq; ret = devm_request_threaded_irq(dev, irq, NULL, tps6594_esm_isr, IRQF_ONESHOT, @@ -82,7 +81,7 @@ static int tps6594_esm_probe(struct platform_device *pdev) return 0; } -static int tps6594_esm_remove(struct platform_device *pdev) +static void tps6594_esm_remove(struct platform_device *pdev) { struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent); struct device *dev = &pdev->dev; @@ -103,8 +102,6 @@ static int tps6594_esm_remove(struct platform_device *pdev) out: pm_runtime_put_sync(dev); pm_runtime_disable(dev); - - return ret; } static int tps6594_esm_suspend(struct device *dev) @@ -138,7 +135,7 @@ static struct platform_driver tps6594_esm_driver = { .pm = pm_sleep_ptr(&tps6594_esm_pm_ops), }, .probe = tps6594_esm_probe, - .remove = tps6594_esm_remove, + .remove_new = tps6594_esm_remove, }; module_platform_driver(tps6594_esm_driver); diff --git a/drivers/misc/tps6594-pfsm.c b/drivers/misc/tps6594-pfsm.c index 5223d1580807..88dcac814892 100644 --- a/drivers/misc/tps6594-pfsm.c +++ b/drivers/misc/tps6594-pfsm.c @@ -266,8 +266,7 @@ static int tps6594_pfsm_probe(struct platform_device *pdev) for (i = 0 ; i < pdev->num_resources ; i++) { irq = platform_get_irq_byname(pdev, pdev->resource[i].name); if (irq < 0) - return dev_err_probe(dev, irq, "Failed to get %s irq\n", - pdev->resource[i].name); + return irq; ret = devm_request_threaded_irq(dev, irq, NULL, tps6594_pfsm_isr, IRQF_ONESHOT, @@ -281,13 +280,11 @@ static int tps6594_pfsm_probe(struct platform_device *pdev) return misc_register(&pfsm->miscdev); } -static int tps6594_pfsm_remove(struct platform_device *pdev) +static void tps6594_pfsm_remove(struct platform_device *pdev) { struct tps6594_pfsm *pfsm = platform_get_drvdata(pdev); misc_deregister(&pfsm->miscdev); - - return 0; } static struct platform_driver tps6594_pfsm_driver = { @@ -295,7 +292,7 @@ static struct platform_driver tps6594_pfsm_driver = { .name = "tps6594-pfsm", }, .probe = tps6594_pfsm_probe, - .remove = tps6594_pfsm_remove, + .remove_new = tps6594_pfsm_remove, }; module_platform_driver(tps6594_pfsm_driver); diff --git a/drivers/misc/vcpu_stall_detector.c b/drivers/misc/vcpu_stall_detector.c index 53b5506080e1..6479c962da1a 100644 --- a/drivers/misc/vcpu_stall_detector.c +++ b/drivers/misc/vcpu_stall_detector.c @@ -13,7 +13,6 @@ #include <linux/module.h> #include <linux/nmi.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/param.h> #include <linux/percpu.h> #include <linux/platform_device.h> diff --git a/drivers/misc/xilinx_sdfec.c b/drivers/misc/xilinx_sdfec.c index 270ff4c5971a..94a0ee19bf20 100644 --- a/drivers/misc/xilinx_sdfec.c +++ b/drivers/misc/xilinx_sdfec.c @@ -15,7 +15,8 @@ #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> -#include <linux/of_platform.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/poll.h> #include <linux/slab.h> #include <linux/clk.h> @@ -1347,7 +1348,6 @@ static int xsdfec_probe(struct platform_device *pdev) { struct xsdfec_dev *xsdfec; struct device *dev; - struct resource *res; int err; bool irq_enabled = true; @@ -1363,8 +1363,7 @@ static int xsdfec_probe(struct platform_device *pdev) return err; dev = xsdfec->dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - xsdfec->regs = devm_ioremap_resource(dev, res); + xsdfec->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(xsdfec->regs)) { err = PTR_ERR(xsdfec->regs); goto err_xsdfec_dev; diff --git a/drivers/misc/xilinx_tmr_inject.c b/drivers/misc/xilinx_tmr_inject.c index d96f6d7cd109..9fc5835bfebc 100644 --- a/drivers/misc/xilinx_tmr_inject.c +++ b/drivers/misc/xilinx_tmr_inject.c @@ -11,7 +11,8 @@ #include <asm/xilinx_mb_manager.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/fault-inject.h> /* TMR Inject Register offsets */ diff --git a/drivers/misc/xilinx_tmr_manager.c b/drivers/misc/xilinx_tmr_manager.c index 0ef55e06d3a0..03912a90fd95 100644 --- a/drivers/misc/xilinx_tmr_manager.c +++ b/drivers/misc/xilinx_tmr_manager.c @@ -15,7 +15,8 @@ #include <asm/xilinx_mb_manager.h> #include <linux/module.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> /* TMR Manager Register offsets */ #define XTMR_MANAGER_CR_OFFSET 0x0 @@ -170,8 +171,7 @@ static int xtmr_manager_probe(struct platform_device *pdev) if (!xtmr_manager) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - xtmr_manager->regs = devm_ioremap_resource(&pdev->dev, res); + xtmr_manager->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(xtmr_manager->regs)) return PTR_ERR(xtmr_manager->regs); diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index da9befa3d6c4..5bc9c4874fe3 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -226,6 +226,19 @@ config NVMEM_QCOM_QFPROM This driver can also be built as a module. If so, the module will be called nvmem_qfprom. +config NVMEM_QCOM_SEC_QFPROM + tristate "QCOM SECURE QFPROM Support" + depends on ARCH_QCOM || COMPILE_TEST + depends on HAS_IOMEM + depends on OF + select QCOM_SCM + help + Say y here to enable secure QFPROM support. The secure QFPROM provides access + functions for QFPROM data to rest of the drivers via nvmem interface. + + This driver can also be built as a module. If so, the module will be called + nvmem_sec_qfprom. + config NVMEM_RAVE_SP_EEPROM tristate "Rave SP EEPROM Support" depends on RAVE_SP_CORE @@ -247,7 +260,7 @@ config NVMEM_ROCKCHIP_EFUSE depends on ARCH_ROCKCHIP || COMPILE_TEST depends on HAS_IOMEM help - This is a simple drive to dump specified values of Rockchip SoC + This is a simple driver to dump specified values of Rockchip SoC from eFuse, such as cpu-leakage. This driver can also be built as a module. If so, the module @@ -258,8 +271,8 @@ config NVMEM_ROCKCHIP_OTP depends on ARCH_ROCKCHIP || COMPILE_TEST depends on HAS_IOMEM help - This is a simple drive to dump specified values of Rockchip SoC - from otp, such as cpu-leakage. + This is a simple driver to dump specified values of Rockchip SoC + from OTP, such as cpu-leakage. This driver can also be built as a module. If so, the module will be called nvmem_rockchip_otp. @@ -392,4 +405,16 @@ config NVMEM_ZYNQMP If sure, say yes. If unsure, say no. +config NVMEM_QORIQ_EFUSE + tristate "NXP QorIQ eFuse support" + depends on PPC_85xx || COMPILE_TEST + depends on HAS_IOMEM + help + This driver provides read support for the eFuses (SFP) on NXP QorIQ + series SoC's. This includes secure boot settings, the globally unique + NXP ID 'FUIDR' and the OEM unique ID 'OUIDR'. + + This driver can also be built as a module. If so, the module + will be called nvmem_qoriq_efuse. + endif diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index cc23ce4ffb1f..423baf089515 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -46,6 +46,8 @@ obj-$(CONFIG_NVMEM_NINTENDO_OTP) += nvmem-nintendo-otp.o nvmem-nintendo-otp-y := nintendo-otp.o obj-$(CONFIG_NVMEM_QCOM_QFPROM) += nvmem_qfprom.o nvmem_qfprom-y := qfprom.o +obj-$(CONFIG_NVMEM_QCOM_SEC_QFPROM) += nvmem_sec_qfprom.o +nvmem_sec_qfprom-y := sec-qfprom.o obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o obj-$(CONFIG_NVMEM_RMEM) += nvmem-rmem.o @@ -77,3 +79,5 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o nvmem-vf610-ocotp-y := vf610-ocotp.o obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o +obj-$(CONFIG_NVMEM_QORIQ_EFUSE) += nvmem-qoriq-efuse.o +nvmem-qoriq-efuse-y := qoriq-efuse.o diff --git a/drivers/nvmem/bcm-ocotp.c b/drivers/nvmem/bcm-ocotp.c index 0c1fa0c4feb2..2490f44caa40 100644 --- a/drivers/nvmem/bcm-ocotp.c +++ b/drivers/nvmem/bcm-ocotp.c @@ -8,7 +8,6 @@ #include <linux/module.h> #include <linux/nvmem-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> /* diff --git a/drivers/nvmem/brcm_nvram.c b/drivers/nvmem/brcm_nvram.c index 4567c597c87f..9737104f3b76 100644 --- a/drivers/nvmem/brcm_nvram.c +++ b/drivers/nvmem/brcm_nvram.c @@ -159,8 +159,7 @@ static int brcm_nvram_probe(struct platform_device *pdev) return -ENOMEM; priv->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index 3f8c7718412b..eaf6a3fe8ca6 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -17,7 +17,6 @@ #include <linux/nvmem-provider.h> #include <linux/gpio/consumer.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/slab.h> struct nvmem_device { @@ -772,12 +771,16 @@ int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner) list_add(&layout->node, &nvmem_layouts); spin_unlock(&nvmem_layout_lock); + blocking_notifier_call_chain(&nvmem_notifier, NVMEM_LAYOUT_ADD, layout); + return 0; } EXPORT_SYMBOL_GPL(__nvmem_layout_register); void nvmem_layout_unregister(struct nvmem_layout *layout) { + blocking_notifier_call_chain(&nvmem_notifier, NVMEM_LAYOUT_REMOVE, layout); + spin_lock(&nvmem_layout_lock); list_del(&layout->node); spin_unlock(&nvmem_layout_lock); @@ -786,10 +789,10 @@ EXPORT_SYMBOL_GPL(nvmem_layout_unregister); static struct nvmem_layout *nvmem_layout_get(struct nvmem_device *nvmem) { - struct device_node *layout_np, *np = nvmem->dev.of_node; + struct device_node *layout_np; struct nvmem_layout *l, *layout = ERR_PTR(-EPROBE_DEFER); - layout_np = of_get_child_by_name(np, "nvmem-layout"); + layout_np = of_nvmem_layout_get_container(nvmem); if (!layout_np) return NULL; @@ -998,17 +1001,17 @@ struct nvmem_device *nvmem_register(const struct nvmem_config *config) if (rval) goto err_remove_cells; - dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name); - - rval = device_add(&nvmem->dev); + rval = nvmem_add_cells_from_fixed_layout(nvmem); if (rval) goto err_remove_cells; - rval = nvmem_add_cells_from_fixed_layout(nvmem); + rval = nvmem_add_cells_from_layout(nvmem); if (rval) goto err_remove_cells; - rval = nvmem_add_cells_from_layout(nvmem); + dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name); + + rval = device_add(&nvmem->dev); if (rval) goto err_remove_cells; diff --git a/drivers/nvmem/imx-iim.c b/drivers/nvmem/imx-iim.c index c86339a7f583..f13bbd164086 100644 --- a/drivers/nvmem/imx-iim.c +++ b/drivers/nvmem/imx-iim.c @@ -14,7 +14,6 @@ #include <linux/module.h> #include <linux/nvmem-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/clk.h> diff --git a/drivers/nvmem/imx-ocotp-ele.c b/drivers/nvmem/imx-ocotp-ele.c index f1cbbc9afeb8..cf920542f939 100644 --- a/drivers/nvmem/imx-ocotp-ele.c +++ b/drivers/nvmem/imx-ocotp-ele.c @@ -9,7 +9,7 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/nvmem-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/nvmem/imx-ocotp-scu.c b/drivers/nvmem/imx-ocotp-scu.c index 399e1eb8b4c1..c38d9c1c3f48 100644 --- a/drivers/nvmem/imx-ocotp-scu.c +++ b/drivers/nvmem/imx-ocotp-scu.c @@ -11,7 +11,7 @@ #include <linux/firmware/imx/sci.h> #include <linux/module.h> #include <linux/nvmem-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index ab556c011f3e..a223d9537f22 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -20,7 +20,6 @@ #include <linux/module.h> #include <linux/nvmem-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/delay.h> diff --git a/drivers/nvmem/lpc18xx_otp.c b/drivers/nvmem/lpc18xx_otp.c index 16c92ea85d49..adc9948e7b2e 100644 --- a/drivers/nvmem/lpc18xx_otp.c +++ b/drivers/nvmem/lpc18xx_otp.c @@ -14,7 +14,6 @@ #include <linux/module.h> #include <linux/nvmem-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -68,14 +67,12 @@ static int lpc18xx_otp_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; struct lpc18xx_otp *otp; - struct resource *res; otp = devm_kzalloc(&pdev->dev, sizeof(*otp), GFP_KERNEL); if (!otp) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - otp->base = devm_ioremap_resource(&pdev->dev, res); + otp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(otp->base)) return PTR_ERR(otp->base); diff --git a/drivers/nvmem/meson-mx-efuse.c b/drivers/nvmem/meson-mx-efuse.c index 13eb14316f46..d6d7aeda31f9 100644 --- a/drivers/nvmem/meson-mx-efuse.c +++ b/drivers/nvmem/meson-mx-efuse.c @@ -14,7 +14,6 @@ #include <linux/module.h> #include <linux/nvmem-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/sizes.h> #include <linux/slab.h> @@ -194,7 +193,6 @@ static int meson_mx_efuse_probe(struct platform_device *pdev) { const struct meson_mx_efuse_platform_data *drvdata; struct meson_mx_efuse *efuse; - struct resource *res; drvdata = of_device_get_match_data(&pdev->dev); if (!drvdata) @@ -204,8 +202,7 @@ static int meson_mx_efuse_probe(struct platform_device *pdev) if (!efuse) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - efuse->base = devm_ioremap_resource(&pdev->dev, res); + efuse->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(efuse->base)) return PTR_ERR(efuse->base); diff --git a/drivers/nvmem/qcom-spmi-sdam.c b/drivers/nvmem/qcom-spmi-sdam.c index f822790db49e..70f2d4f2efbf 100644 --- a/drivers/nvmem/qcom-spmi-sdam.c +++ b/drivers/nvmem/qcom-spmi-sdam.c @@ -6,8 +6,8 @@ #include <linux/device.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_platform.h> #include <linux/nvmem-provider.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #define SDAM_MEM_START 0x40 diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index c1e893c8a247..14814cba2dd6 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -374,8 +374,7 @@ static int qfprom_probe(struct platform_device *pdev) return -ENOMEM; /* The corrected section is always provided */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->qfpcorrected = devm_ioremap_resource(dev, res); + priv->qfpcorrected = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->qfpcorrected)) return PTR_ERR(priv->qfpcorrected); @@ -402,12 +401,10 @@ static int qfprom_probe(struct platform_device *pdev) priv->qfpraw = devm_ioremap_resource(dev, res); if (IS_ERR(priv->qfpraw)) return PTR_ERR(priv->qfpraw); - res = platform_get_resource(pdev, IORESOURCE_MEM, 2); - priv->qfpconf = devm_ioremap_resource(dev, res); + priv->qfpconf = devm_platform_ioremap_resource(pdev, 2); if (IS_ERR(priv->qfpconf)) return PTR_ERR(priv->qfpconf); - res = platform_get_resource(pdev, IORESOURCE_MEM, 3); - priv->qfpsecurity = devm_ioremap_resource(dev, res); + priv->qfpsecurity = devm_platform_ioremap_resource(pdev, 3); if (IS_ERR(priv->qfpsecurity)) return PTR_ERR(priv->qfpsecurity); @@ -427,12 +424,8 @@ static int qfprom_probe(struct platform_device *pdev) return PTR_ERR(priv->vcc); priv->secclk = devm_clk_get(dev, "core"); - if (IS_ERR(priv->secclk)) { - ret = PTR_ERR(priv->secclk); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Error getting clock: %d\n", ret); - return ret; - } + if (IS_ERR(priv->secclk)) + return dev_err_probe(dev, PTR_ERR(priv->secclk), "Error getting clock\n"); /* Only enable writing if we have SoC data. */ if (priv->soc_data) diff --git a/drivers/nvmem/qoriq-efuse.c b/drivers/nvmem/qoriq-efuse.c new file mode 100644 index 000000000000..e7fd04d6dd94 --- /dev/null +++ b/drivers/nvmem/qoriq-efuse.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Westermo Network Technologies AB + */ + +#include <linux/device.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/nvmem-provider.h> +#include <linux/platform_device.h> + +struct qoriq_efuse_priv { + void __iomem *base; +}; + +static int qoriq_efuse_read(void *context, unsigned int offset, void *val, + size_t bytes) +{ + struct qoriq_efuse_priv *priv = context; + + /* .stride = 4 so offset is guaranteed to be aligned */ + __ioread32_copy(val, priv->base + offset, bytes / 4); + + /* Ignore trailing bytes (there shouldn't be any) */ + + return 0; +} + +static int qoriq_efuse_probe(struct platform_device *pdev) +{ + struct nvmem_config config = { + .dev = &pdev->dev, + .read_only = true, + .reg_read = qoriq_efuse_read, + .stride = sizeof(u32), + .word_size = sizeof(u32), + .name = "qoriq_efuse_read", + .id = NVMEM_DEVID_AUTO, + .root_only = true, + }; + struct qoriq_efuse_priv *priv; + struct nvmem_device *nvmem; + struct resource *res; + + priv = devm_kzalloc(config.dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + config.size = resource_size(res); + config.priv = priv; + nvmem = devm_nvmem_register(config.dev, &config); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static const struct of_device_id qoriq_efuse_of_match[] = { + { .compatible = "fsl,t1023-sfp", }, + {/* sentinel */}, +}; +MODULE_DEVICE_TABLE(of, qoriq_efuse_of_match); + +static struct platform_driver qoriq_efuse_driver = { + .probe = qoriq_efuse_probe, + .driver = { + .name = "qoriq-efuse", + .of_match_table = qoriq_efuse_of_match, + }, +}; +module_platform_driver(qoriq_efuse_driver); + +MODULE_AUTHOR("Richard Alpe <richard.alpe@bit42.se>"); +MODULE_DESCRIPTION("NXP QorIQ Security Fuse Processor (SFP) Reader"); +MODULE_LICENSE("GPL"); diff --git a/drivers/nvmem/rave-sp-eeprom.c b/drivers/nvmem/rave-sp-eeprom.c index c456011b75e8..df6a1c594b78 100644 --- a/drivers/nvmem/rave-sp-eeprom.c +++ b/drivers/nvmem/rave-sp-eeprom.c @@ -10,7 +10,7 @@ #include <linux/mfd/rave-sp.h> #include <linux/module.h> #include <linux/nvmem-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/sizes.h> diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c index e4579de5d014..4004c5bece42 100644 --- a/drivers/nvmem/rockchip-efuse.c +++ b/drivers/nvmem/rockchip-efuse.c @@ -267,8 +267,7 @@ static int rockchip_efuse_probe(struct platform_device *pdev) if (!efuse) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - efuse->base = devm_ioremap_resource(dev, res); + efuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(efuse->base)) return PTR_ERR(efuse->base); diff --git a/drivers/nvmem/sc27xx-efuse.c b/drivers/nvmem/sc27xx-efuse.c index c825fc902d10..2210da40dfbd 100644 --- a/drivers/nvmem/sc27xx-efuse.c +++ b/drivers/nvmem/sc27xx-efuse.c @@ -4,7 +4,6 @@ #include <linux/hwspinlock.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/nvmem-provider.h> diff --git a/drivers/nvmem/sec-qfprom.c b/drivers/nvmem/sec-qfprom.c new file mode 100644 index 000000000000..e48c2dc0c44b --- /dev/null +++ b/drivers/nvmem/sec-qfprom.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/firmware/qcom/qcom_scm.h> +#include <linux/mod_devicetable.h> +#include <linux/nvmem-provider.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +/** + * struct sec_qfprom - structure holding secure qfprom attributes + * + * @base: starting physical address for secure qfprom corrected address space. + * @dev: qfprom device structure. + */ +struct sec_qfprom { + phys_addr_t base; + struct device *dev; +}; + +static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) +{ + struct sec_qfprom *priv = context; + unsigned int i; + u8 *val = _val; + u32 read_val; + u8 *tmp; + + for (i = 0; i < bytes; i++, reg++) { + if (i == 0 || reg % 4 == 0) { + if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) { + dev_err(priv->dev, "Couldn't access fuse register\n"); + return -EINVAL; + } + tmp = (u8 *)&read_val; + } + + val[i] = tmp[reg & 3]; + } + + return 0; +} + +static int sec_qfprom_probe(struct platform_device *pdev) +{ + struct nvmem_config econfig = { + .name = "sec-qfprom", + .stride = 1, + .word_size = 1, + .id = NVMEM_DEVID_AUTO, + .reg_read = sec_qfprom_reg_read, + }; + struct device *dev = &pdev->dev; + struct nvmem_device *nvmem; + struct sec_qfprom *priv; + struct resource *res; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + priv->base = res->start; + + econfig.size = resource_size(res); + econfig.dev = dev; + econfig.priv = priv; + + priv->dev = dev; + + nvmem = devm_nvmem_register(dev, &econfig); + + return PTR_ERR_OR_ZERO(nvmem); +} + +static const struct of_device_id sec_qfprom_of_match[] = { + { .compatible = "qcom,sec-qfprom" }, + {/* sentinel */}, +}; +MODULE_DEVICE_TABLE(of, sec_qfprom_of_match); + +static struct platform_driver qfprom_driver = { + .probe = sec_qfprom_probe, + .driver = { + .name = "qcom_sec_qfprom", + .of_match_table = sec_qfprom_of_match, + }, +}; +module_platform_driver(qfprom_driver); +MODULE_DESCRIPTION("Qualcomm Secure QFPROM driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c index 4692aa985bd6..89c27112320f 100644 --- a/drivers/nvmem/snvs_lpgpr.c +++ b/drivers/nvmem/snvs_lpgpr.c @@ -7,7 +7,8 @@ #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/nvmem-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/platform_device.h> #include <linux/regmap.h> #define IMX6Q_SNVS_HPLR 0x00 diff --git a/drivers/nvmem/sprd-efuse.c b/drivers/nvmem/sprd-efuse.c index 4f1fcbfec394..7e6e31db4baa 100644 --- a/drivers/nvmem/sprd-efuse.c +++ b/drivers/nvmem/sprd-efuse.c @@ -7,7 +7,7 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/nvmem-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #define SPRD_EFUSE_ENABLE 0x20 diff --git a/drivers/nvmem/stm32-romem.c b/drivers/nvmem/stm32-romem.c index 38d0bf557129..0f84044bd1ad 100644 --- a/drivers/nvmem/stm32-romem.c +++ b/drivers/nvmem/stm32-romem.c @@ -196,8 +196,7 @@ static int stm32_romem_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/nvmem/sunplus-ocotp.c b/drivers/nvmem/sunplus-ocotp.c index f85350b17d67..f3a18aa0a6c7 100644 --- a/drivers/nvmem/sunplus-ocotp.c +++ b/drivers/nvmem/sunplus-ocotp.c @@ -13,8 +13,8 @@ #include <linux/io.h> #include <linux/iopoll.h> #include <linux/module.h> +#include <linux/mod_devicetable.h> #include <linux/nvmem-provider.h> -#include <linux/of_device.h> #include <linux/platform_device.h> /* diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c index a970f1741cc6..5d364d85347f 100644 --- a/drivers/nvmem/sunxi_sid.c +++ b/drivers/nvmem/sunxi_sid.c @@ -12,7 +12,6 @@ #include <linux/module.h> #include <linux/nvmem-provider.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/random.h> @@ -125,7 +124,6 @@ static int sun8i_sid_read_by_reg(void *context, unsigned int offset, static int sunxi_sid_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *res; struct nvmem_config *nvmem_cfg; struct nvmem_device *nvmem; struct sunxi_sid *sid; @@ -142,8 +140,7 @@ static int sunxi_sid_probe(struct platform_device *pdev) return -EINVAL; sid->value_offset = cfg->value_offset; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - sid->base = devm_ioremap_resource(dev, res); + sid->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(sid->base)) return PTR_ERR(sid->base); diff --git a/drivers/nvmem/u-boot-env.c b/drivers/nvmem/u-boot-env.c index ee9fd9989b6e..c4ae94af4af7 100644 --- a/drivers/nvmem/u-boot-env.c +++ b/drivers/nvmem/u-boot-env.c @@ -11,7 +11,7 @@ #include <linux/mtd/mtd.h> #include <linux/nvmem-consumer.h> #include <linux/nvmem-provider.h> -#include <linux/of_device.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> @@ -47,7 +47,7 @@ struct u_boot_env_image_broadcom { __le32 magic; __le32 len; __le32 crc32; - uint8_t data[0]; + DECLARE_FLEX_ARRAY(uint8_t, data); } __packed; static int u_boot_env_read(void *context, unsigned int offset, void *val, diff --git a/drivers/nvmem/uniphier-efuse.c b/drivers/nvmem/uniphier-efuse.c index aca910b3b6f8..0a1dbb80537e 100644 --- a/drivers/nvmem/uniphier-efuse.c +++ b/drivers/nvmem/uniphier-efuse.c @@ -41,8 +41,7 @@ static int uniphier_efuse_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index e72419d7e72e..dddb235dd020 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -19,6 +19,7 @@ if PCCARD config PCMCIA tristate "16-bit PCMCIA support" + depends on HAS_IOMEM select CRC32 default y help diff --git a/drivers/peci/controller/Kconfig b/drivers/peci/controller/Kconfig index 2fc5e2abb74a..4f9c245ad042 100644 --- a/drivers/peci/controller/Kconfig +++ b/drivers/peci/controller/Kconfig @@ -16,3 +16,19 @@ config PECI_ASPEED This driver can also be built as a module. If so, the module will be called peci-aspeed. + +config PECI_NPCM + tristate "Nuvoton NPCM PECI support" + depends on ARCH_NPCM || COMPILE_TEST + depends on OF + select REGMAP_MMIO + help + This option enables PECI controller driver for Nuvoton NPCM7XX + and NPCM8XX SoCs. It allows BMC to discover devices connected + to it and communicate with them using PECI protocol. + + Say Y here if you want support for the Platform Environment Control + Interface (PECI) bus adapter driver on the Nuvoton NPCM SoCs. + + This support is also available as a module. If so, the module + will be called peci-npcm. diff --git a/drivers/peci/controller/Makefile b/drivers/peci/controller/Makefile index 022c28ef1bf0..e247449bb423 100644 --- a/drivers/peci/controller/Makefile +++ b/drivers/peci/controller/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o +obj-$(CONFIG_PECI_NPCM) += peci-npcm.o diff --git a/drivers/peci/controller/peci-aspeed.c b/drivers/peci/controller/peci-aspeed.c index 731c5d8f75c6..7fdc25afcf2f 100644 --- a/drivers/peci/controller/peci-aspeed.c +++ b/drivers/peci/controller/peci-aspeed.c @@ -468,7 +468,7 @@ static void aspeed_peci_property_setup(struct aspeed_peci *priv) ASPEED_PECI_CMD_TIMEOUT_MS_DEFAULT, &priv->cmd_timeout_ms); } -static struct peci_controller_ops aspeed_ops = { +static const struct peci_controller_ops aspeed_ops = { .xfer = aspeed_peci_xfer, }; diff --git a/drivers/peci/controller/peci-npcm.c b/drivers/peci/controller/peci-npcm.c new file mode 100644 index 000000000000..ec613d35c796 --- /dev/null +++ b/drivers/peci/controller/peci-npcm.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology corporation + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/jiffies.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/peci.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +/* NPCM GCR module */ +#define NPCM_INTCR3_OFFSET 0x9C +#define NPCM_INTCR3_PECIVSEL BIT(19) + +/* NPCM PECI Registers */ +#define NPCM_PECI_CTL_STS 0x00 +#define NPCM_PECI_RD_LENGTH 0x04 +#define NPCM_PECI_ADDR 0x08 +#define NPCM_PECI_CMD 0x0C +#define NPCM_PECI_CTL2 0x10 +#define NPCM_PECI_WR_LENGTH 0x1C +#define NPCM_PECI_PDDR 0x2C +#define NPCM_PECI_DAT_INOUT(n) (0x100 + ((n) * 4)) + +#define NPCM_PECI_MAX_REG 0x200 + +/* NPCM_PECI_CTL_STS - 0x00 : Control Register */ +#define NPCM_PECI_CTRL_DONE_INT_EN BIT(6) +#define NPCM_PECI_CTRL_ABRT_ERR BIT(4) +#define NPCM_PECI_CTRL_CRC_ERR BIT(3) +#define NPCM_PECI_CTRL_DONE BIT(1) +#define NPCM_PECI_CTRL_START_BUSY BIT(0) + +/* NPCM_PECI_RD_LENGTH - 0x04 : Command Register */ +#define NPCM_PECI_RD_LEN_MASK GENMASK(6, 0) + +/* NPCM_PECI_CMD - 0x10 : Command Register */ +#define NPCM_PECI_CTL2_MASK GENMASK(7, 6) + +/* NPCM_PECI_WR_LENGTH - 0x1C : Command Register */ +#define NPCM_PECI_WR_LEN_MASK GENMASK(6, 0) + +/* NPCM_PECI_PDDR - 0x2C : Command Register */ +#define NPCM_PECI_PDDR_MASK GENMASK(4, 0) + +#define NPCM_PECI_INT_MASK (NPCM_PECI_CTRL_ABRT_ERR | \ + NPCM_PECI_CTRL_CRC_ERR | \ + NPCM_PECI_CTRL_DONE) + +#define NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC (50 * USEC_PER_MSEC) +#define NPCM_PECI_IDLE_CHECK_INTERVAL_USEC (10 * USEC_PER_MSEC) +#define NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT 1000 +#define NPCM_PECI_CMD_TIMEOUT_MS_MAX 60000 +#define NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT 15 +#define NPCM_PECI_PULL_DOWN_DEFAULT 0 + +struct npcm_peci { + u32 cmd_timeout_ms; + struct completion xfer_complete; + struct regmap *regmap; + u32 status; + spinlock_t lock; /* to sync completion status handling */ + struct peci_controller *controller; + struct device *dev; + struct clk *clk; + int irq; +}; + +static int npcm_peci_xfer(struct peci_controller *controller, u8 addr, struct peci_request *req) +{ + struct npcm_peci *priv = dev_get_drvdata(controller->dev.parent); + unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms); + unsigned int msg_rd; + u32 cmd_sts; + int i, ret; + + /* Check command sts and bus idle state */ + ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts, + !(cmd_sts & NPCM_PECI_CTRL_START_BUSY), + NPCM_PECI_IDLE_CHECK_INTERVAL_USEC, + NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC); + if (ret) + return ret; /* -ETIMEDOUT */ + + spin_lock_irq(&priv->lock); + reinit_completion(&priv->xfer_complete); + + regmap_write(priv->regmap, NPCM_PECI_ADDR, addr); + regmap_write(priv->regmap, NPCM_PECI_RD_LENGTH, NPCM_PECI_WR_LEN_MASK & req->rx.len); + regmap_write(priv->regmap, NPCM_PECI_WR_LENGTH, NPCM_PECI_WR_LEN_MASK & req->tx.len); + + if (req->tx.len) { + regmap_write(priv->regmap, NPCM_PECI_CMD, req->tx.buf[0]); + + for (i = 0; i < (req->tx.len - 1); i++) + regmap_write(priv->regmap, NPCM_PECI_DAT_INOUT(i), req->tx.buf[i + 1]); + } + +#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) + dev_dbg(priv->dev, "addr : %#02x, tx.len : %#02x, rx.len : %#02x\n", + addr, req->tx.len, req->rx.len); + print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf, req->tx.len); +#endif + + priv->status = 0; + regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_START_BUSY, + NPCM_PECI_CTRL_START_BUSY); + + spin_unlock_irq(&priv->lock); + + ret = wait_for_completion_interruptible_timeout(&priv->xfer_complete, timeout); + if (ret < 0) + return ret; + + if (ret == 0) { + dev_dbg(priv->dev, "timeout waiting for a response\n"); + return -ETIMEDOUT; + } + + spin_lock_irq(&priv->lock); + + if (priv->status != NPCM_PECI_CTRL_DONE) { + spin_unlock_irq(&priv->lock); + dev_dbg(priv->dev, "no valid response, status: %#02x\n", priv->status); + return -EIO; + } + + regmap_write(priv->regmap, NPCM_PECI_CMD, 0); + + for (i = 0; i < req->rx.len; i++) { + regmap_read(priv->regmap, NPCM_PECI_DAT_INOUT(i), &msg_rd); + req->rx.buf[i] = (u8)msg_rd; + } + + spin_unlock_irq(&priv->lock); + +#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) + print_hex_dump_bytes("RX : ", DUMP_PREFIX_NONE, req->rx.buf, req->rx.len); +#endif + return 0; +} + +static irqreturn_t npcm_peci_irq_handler(int irq, void *arg) +{ + struct npcm_peci *priv = arg; + u32 status_ack = 0; + u32 status; + + spin_lock(&priv->lock); + regmap_read(priv->regmap, NPCM_PECI_CTL_STS, &status); + priv->status |= (status & NPCM_PECI_INT_MASK); + + if (status & NPCM_PECI_CTRL_CRC_ERR) + status_ack |= NPCM_PECI_CTRL_CRC_ERR; + + if (status & NPCM_PECI_CTRL_ABRT_ERR) + status_ack |= NPCM_PECI_CTRL_ABRT_ERR; + + /* + * All commands should be ended up with a NPCM_PECI_CTRL_DONE + * bit set even in an error case. + */ + if (status & NPCM_PECI_CTRL_DONE) { + status_ack |= NPCM_PECI_CTRL_DONE; + complete(&priv->xfer_complete); + } + + regmap_write_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_INT_MASK, status_ack); + + spin_unlock(&priv->lock); + return IRQ_HANDLED; +} + +static int npcm_peci_init_ctrl(struct npcm_peci *priv) +{ + u32 cmd_sts; + int ret; + + priv->clk = devm_clk_get_enabled(priv->dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(priv->dev, "failed to get ref clock\n"); + return PTR_ERR(priv->clk); + } + + ret = device_property_read_u32(priv->dev, "cmd-timeout-ms", &priv->cmd_timeout_ms); + if (ret) { + priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT; + } else if (priv->cmd_timeout_ms > NPCM_PECI_CMD_TIMEOUT_MS_MAX || + priv->cmd_timeout_ms == 0) { + dev_warn(priv->dev, "invalid cmd-timeout-ms: %u, falling back to: %u\n", + priv->cmd_timeout_ms, NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT); + + priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT; + } + + regmap_update_bits(priv->regmap, NPCM_PECI_CTL2, NPCM_PECI_CTL2_MASK, + NPCM_PECI_PULL_DOWN_DEFAULT << 6); + + regmap_update_bits(priv->regmap, NPCM_PECI_PDDR, NPCM_PECI_PDDR_MASK, + NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT); + + ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts, + !(cmd_sts & NPCM_PECI_CTRL_START_BUSY), + NPCM_PECI_IDLE_CHECK_INTERVAL_USEC, + NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC); + if (ret) + return ret; /* -ETIMEDOUT */ + + /* PECI interrupt enable */ + regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, NPCM_PECI_CTRL_DONE_INT_EN, + NPCM_PECI_CTRL_DONE_INT_EN); + + return 0; +} + +static const struct regmap_config npcm_peci_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = NPCM_PECI_MAX_REG, + .fast_io = true, +}; + +static struct peci_controller_ops npcm_ops = { + .xfer = npcm_peci_xfer, +}; + +static int npcm_peci_probe(struct platform_device *pdev) +{ + struct peci_controller *controller; + struct npcm_peci *priv; + void __iomem *base; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, priv); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &npcm_peci_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) + return priv->irq; + + ret = devm_request_irq(&pdev->dev, priv->irq, npcm_peci_irq_handler, + 0, "peci-npcm-irq", priv); + if (ret) + return ret; + + init_completion(&priv->xfer_complete); + spin_lock_init(&priv->lock); + + ret = npcm_peci_init_ctrl(priv); + if (ret) + return ret; + + controller = devm_peci_controller_add(priv->dev, &npcm_ops); + if (IS_ERR(controller)) + return dev_err_probe(priv->dev, PTR_ERR(controller), + "failed to add npcm peci controller\n"); + + priv->controller = controller; + + return 0; +} + +static const struct of_device_id npcm_peci_of_table[] = { + { .compatible = "nuvoton,npcm750-peci", }, + { .compatible = "nuvoton,npcm845-peci", }, + { } +}; +MODULE_DEVICE_TABLE(of, npcm_peci_of_table); + +static struct platform_driver npcm_peci_driver = { + .probe = npcm_peci_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = npcm_peci_of_table, + }, +}; +module_platform_driver(npcm_peci_driver); + +MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); +MODULE_DESCRIPTION("NPCM PECI driver"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(PECI); diff --git a/drivers/peci/core.c b/drivers/peci/core.c index 9c8cf07e51c7..0f83a9c6093b 100644 --- a/drivers/peci/core.c +++ b/drivers/peci/core.c @@ -44,7 +44,7 @@ int peci_controller_scan_devices(struct peci_controller *controller) } static struct peci_controller *peci_controller_alloc(struct device *dev, - struct peci_controller_ops *ops) + const struct peci_controller_ops *ops) { struct peci_controller *controller; int ret; @@ -113,7 +113,7 @@ static void unregister_controller(void *_controller) * Return: Pointer to the newly allocated controller or ERR_PTR() in case of failure. */ struct peci_controller *devm_peci_controller_add(struct device *dev, - struct peci_controller_ops *ops) + const struct peci_controller_ops *ops) { struct peci_controller *controller; int ret; diff --git a/drivers/peci/cpu.c b/drivers/peci/cpu.c index de4a7b3e5966..bd990acd92b8 100644 --- a/drivers/peci/cpu.c +++ b/drivers/peci/cpu.c @@ -323,6 +323,11 @@ static const struct peci_device_id peci_cpu_device_ids[] = { .model = INTEL_FAM6_ICELAKE_D, .data = "icxd", }, + { /* Sapphire Rapids Xeon */ + .family = 6, + .model = INTEL_FAM6_SAPPHIRERAPIDS_X, + .data = "spr", + }, { } }; MODULE_DEVICE_TABLE(peci, peci_cpu_device_ids); diff --git a/drivers/uio/uio_pruss.c b/drivers/uio/uio_pruss.c index 83966dbd3bbf..77e2dc404885 100644 --- a/drivers/uio/uio_pruss.c +++ b/drivers/uio/uio_pruss.c @@ -175,8 +175,12 @@ static int pruss_probe(struct platform_device *pdev) goto err_free_ddr_vaddr; } + ret = platform_get_irq(pdev, 0); + if (ret < 0) + goto err_unmap; + + gdev->hostirq_start = ret; gdev->pintc_base = pdata->pintc_base; - gdev->hostirq_start = platform_get_irq(pdev, 0); for (cnt = 0, p = gdev->info; cnt < MAX_PRUSS_EVT; cnt++, p++) { p->mem[0].addr = regs_prussio->start; @@ -211,6 +215,7 @@ err_unloop: for (i = 0, p = gdev->info; i < cnt; i++, p++) { uio_unregister_device(p); } +err_unmap: iounmap(gdev->prussio_vaddr); err_free_ddr_vaddr: dma_free_coherent(dev, extram_pool_sz, gdev->ddr_vaddr, |