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Diffstat (limited to 'sound/soc/amd/acp-pcm-dma.c')
-rw-r--r--sound/soc/amd/acp-pcm-dma.c206
1 files changed, 108 insertions, 98 deletions
diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 9fb356db3ab2..540088d317f2 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -23,6 +23,8 @@
#include <drm/amd_asic_type.h>
#include "acp.h"
+#define DRV_NAME "acp_audio_dma"
+
#define PLAYBACK_MIN_NUM_PERIODS 2
#define PLAYBACK_MAX_NUM_PERIODS 2
#define PLAYBACK_MAX_PERIOD_SIZE 16384
@@ -182,19 +184,18 @@ static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
* system memory <-> ACP SRAM
*/
static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
- u32 size, int direction,
- u32 pte_offset, u32 asic_type)
+ u32 size, int direction, u32 pte_offset,
+ u16 ch, u32 sram_bank,
+ u16 dma_dscr_idx, u32 asic_type)
{
u16 i;
- u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
dmadscr[i].xfer_val = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
- dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i;
- dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS
- + (i * (size/2));
+ dma_dscr_idx = dma_dscr_idx + i;
+ dmadscr[i].dest = sram_bank + (i * (size/2));
dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
+ (pte_offset * SZ_4K) + (i * (size/2));
switch (asic_type) {
@@ -209,25 +210,19 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
(size / 2);
}
} else {
- dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i;
+ dma_dscr_idx = dma_dscr_idx + i;
+ dmadscr[i].src = sram_bank + (i * (size/2));
+ dmadscr[i].dest =
+ ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
+ (pte_offset * SZ_4K) + (i * (size/2));
switch (asic_type) {
case CHIP_STONEY:
- dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS +
- (i * (size/2));
- dmadscr[i].dest =
- ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
- (pte_offset * SZ_4K) + (i * (size/2));
dmadscr[i].xfer_val |=
BIT(22) |
(ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) |
(size / 2);
break;
default:
- dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS +
- (i * (size/2));
- dmadscr[i].dest =
- ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
- (pte_offset * SZ_4K) + (i * (size/2));
dmadscr[i].xfer_val |=
BIT(22) |
(ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |
@@ -237,72 +232,49 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
&dmadscr[i]);
}
- if (direction == SNDRV_PCM_STREAM_PLAYBACK)
- config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM,
- PLAYBACK_START_DMA_DESCR_CH12,
- NUM_DSCRS_PER_CHANNEL,
- ACP_DMA_PRIORITY_LEVEL_NORMAL);
- else
- config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM,
- CAPTURE_START_DMA_DESCR_CH14,
- NUM_DSCRS_PER_CHANNEL,
- ACP_DMA_PRIORITY_LEVEL_NORMAL);
+ config_acp_dma_channel(acp_mmio, ch,
+ dma_dscr_idx - 1,
+ NUM_DSCRS_PER_CHANNEL,
+ ACP_DMA_PRIORITY_LEVEL_NORMAL);
}
/* Initialize the DMA descriptor information for transfer between
* ACP SRAM <-> I2S
*/
-static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio,
- u32 size, int direction,
- u32 asic_type)
+static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
+ int direction, u32 sram_bank,
+ u16 destination, u16 ch,
+ u16 dma_dscr_idx, u32 asic_type)
{
u16 i;
- u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
dmadscr[i].xfer_val = 0;
if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
- dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i;
- dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS +
- (i * (size/2));
+ dma_dscr_idx = dma_dscr_idx + i;
+ dmadscr[i].src = sram_bank + (i * (size/2));
/* dmadscr[i].dest is unused by hardware. */
dmadscr[i].dest = 0;
- dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) |
+ dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
(size / 2);
} else {
- dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i;
+ dma_dscr_idx = dma_dscr_idx + i;
/* dmadscr[i].src is unused by hardware. */
dmadscr[i].src = 0;
- switch (asic_type) {
- case CHIP_STONEY:
- dmadscr[i].dest =
- ACP_SHARED_RAM_BANK_3_ADDRESS +
- (i * (size / 2));
- break;
- default:
- dmadscr[i].dest =
- ACP_SHARED_RAM_BANK_5_ADDRESS +
- (i * (size / 2));
- }
+ dmadscr[i].dest =
+ sram_bank + (i * (size / 2));
dmadscr[i].xfer_val |= BIT(22) |
- (FROM_ACP_I2S_1 << 16) | (size / 2);
+ (destination << 16) | (size / 2);
}
config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
&dmadscr[i]);
}
/* Configure the DMA channel with the above descriptore */
- if (direction == SNDRV_PCM_STREAM_PLAYBACK)
- config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
- PLAYBACK_START_DMA_DESCR_CH13,
- NUM_DSCRS_PER_CHANNEL,
- ACP_DMA_PRIORITY_LEVEL_NORMAL);
- else
- config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
- CAPTURE_START_DMA_DESCR_CH15,
- NUM_DSCRS_PER_CHANNEL,
- ACP_DMA_PRIORITY_LEVEL_NORMAL);
+ config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
+ NUM_DSCRS_PER_CHANNEL,
+ ACP_DMA_PRIORITY_LEVEL_NORMAL);
}
/* Create page table entries in ACP SRAM for the allocated memory */
@@ -344,23 +316,51 @@ static void config_acp_dma(void __iomem *acp_mmio,
struct audio_substream_data *audio_config,
u32 asic_type)
{
- u32 pte_offset;
+ u32 pte_offset, sram_bank;
+ u16 ch1, ch2, destination, dma_dscr_idx;
- if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
+ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) {
pte_offset = ACP_PLAYBACK_PTE_OFFSET;
- else
+ ch1 = SYSRAM_TO_ACP_CH_NUM;
+ ch2 = ACP_TO_I2S_DMA_CH_NUM;
+ sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS;
+ destination = TO_ACP_I2S_1;
+
+ } else {
pte_offset = ACP_CAPTURE_PTE_OFFSET;
+ ch1 = SYSRAM_TO_ACP_CH_NUM;
+ ch2 = ACP_TO_I2S_DMA_CH_NUM;
+ switch (asic_type) {
+ case CHIP_STONEY:
+ sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS;
+ break;
+ default:
+ sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS;
+ }
+ destination = FROM_ACP_I2S_1;
+ }
acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages,
pte_offset);
+ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
+ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
+ else
+ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
/* Configure System memory <-> ACP SRAM DMA descriptors */
set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size,
- audio_config->direction, pte_offset, asic_type);
+ audio_config->direction, pte_offset,
+ ch1, sram_bank, dma_dscr_idx, asic_type);
+ if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)
+ dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
+ else
+ dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15;
/* Configure ACP SRAM <-> I2S DMA descriptors */
set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size,
- audio_config->direction, asic_type);
+ audio_config->direction, sram_bank,
+ destination, ch2, dma_dscr_idx,
+ asic_type);
}
/* Start a given DMA channel transfer */
@@ -655,7 +655,7 @@ static irqreturn_t dma_irq_handler(int irq, void *arg)
1, 0);
acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false);
- snd_pcm_period_elapsed(irq_data->play_stream);
+ snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
@@ -678,7 +678,7 @@ static irqreturn_t dma_irq_handler(int irq, void *arg)
if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) {
valid_irq = true;
- snd_pcm_period_elapsed(irq_data->capture_stream);
+ snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16,
acp_mmio, mmACP_EXTERNAL_INTR_STAT);
}
@@ -695,8 +695,8 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
int ret = 0;
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
- struct audio_drv_data *intr_data = dev_get_drvdata(prtd->platform->dev);
-
+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
+ struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
struct audio_substream_data *adata =
kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
if (adata == NULL)
@@ -723,7 +723,7 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
ret = snd_pcm_hw_constraint_integer(runtime,
SNDRV_PCM_HW_PARAM_PERIODS);
if (ret < 0) {
- dev_err(prtd->platform->dev, "set integer constraint failed\n");
+ dev_err(component->dev, "set integer constraint failed\n");
kfree(adata);
return ret;
}
@@ -736,11 +736,11 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
* This enablement is not required for another stream, if current
* stream is not closed
*/
- if (!intr_data->play_stream && !intr_data->capture_stream)
+ if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream)
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- intr_data->play_stream = substream;
+ intr_data->play_i2ssp_stream = substream;
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
* won't be turned off. The default state for SRAM banks is ON.
* Setting SRAM bank state code skipped for STONEY platform.
@@ -751,7 +751,7 @@ static int acp_dma_open(struct snd_pcm_substream *substream)
bank, true);
}
} else {
- intr_data->capture_stream = substream;
+ intr_data->capture_i2ssp_stream = substream;
if (intr_data->asic_type != CHIP_STONEY) {
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(intr_data->acp_mmio,
@@ -772,7 +772,8 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_runtime *runtime;
struct audio_substream_data *rtd;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
- struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev);
+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
+ struct audio_drv_data *adata = dev_get_drvdata(component->dev);
runtime = substream->runtime;
rtd = runtime->private_data;
@@ -859,11 +860,11 @@ static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- if (bytescount > rtd->renderbytescount)
- bytescount = bytescount - rtd->renderbytescount;
+ if (bytescount > rtd->i2ssp_renderbytescount)
+ bytescount = bytescount - rtd->i2ssp_renderbytescount;
} else {
- if (bytescount > rtd->capturebytescount)
- bytescount = bytescount - rtd->capturebytescount;
+ if (bytescount > rtd->i2ssp_capturebytescount)
+ bytescount = bytescount - rtd->i2ssp_capturebytescount;
}
pos = do_div(bytescount, buffersize);
return bytes_to_frames(runtime, pos);
@@ -909,6 +910,7 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
struct snd_pcm_runtime *runtime = substream->runtime;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
struct audio_substream_data *rtd = runtime->private_data;
+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
if (!rtd)
return -EINVAL;
@@ -919,14 +921,14 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
bytescount = acp_get_byte_count(rtd->acp_mmio,
substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- if (rtd->renderbytescount == 0)
- rtd->renderbytescount = bytescount;
+ if (rtd->i2ssp_renderbytescount == 0)
+ rtd->i2ssp_renderbytescount = bytescount;
acp_dma_start(rtd->acp_mmio,
SYSRAM_TO_ACP_CH_NUM, false);
while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
BIT(SYSRAM_TO_ACP_CH_NUM)) {
if (!loops--) {
- dev_err(prtd->platform->dev,
+ dev_err(component->dev,
"acp dma start timeout\n");
return -ETIMEDOUT;
}
@@ -937,8 +939,8 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
ACP_TO_I2S_DMA_CH_NUM, true);
} else {
- if (rtd->capturebytescount == 0)
- rtd->capturebytescount = bytescount;
+ if (rtd->i2ssp_capturebytescount == 0)
+ rtd->i2ssp_capturebytescount = bytescount;
acp_dma_start(rtd->acp_mmio,
I2S_TO_ACP_DMA_CH_NUM, true);
}
@@ -954,12 +956,16 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
*/
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
ret = acp_dma_stop(rtd->acp_mmio,
+ SYSRAM_TO_ACP_CH_NUM);
+ ret = acp_dma_stop(rtd->acp_mmio,
ACP_TO_I2S_DMA_CH_NUM);
- rtd->renderbytescount = 0;
+ rtd->i2ssp_renderbytescount = 0;
} else {
ret = acp_dma_stop(rtd->acp_mmio,
I2S_TO_ACP_DMA_CH_NUM);
- rtd->capturebytescount = 0;
+ ret = acp_dma_stop(rtd->acp_mmio,
+ ACP_TO_SYSRAM_CH_NUM);
+ rtd->i2ssp_capturebytescount = 0;
}
break;
default:
@@ -972,7 +978,8 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
{
int ret;
- struct audio_drv_data *adata = dev_get_drvdata(rtd->platform->dev);
+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);
+ struct audio_drv_data *adata = dev_get_drvdata(component->dev);
switch (adata->asic_type) {
case CHIP_STONEY:
@@ -989,7 +996,7 @@ static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
break;
}
if (ret < 0)
- dev_err(rtd->platform->dev,
+ dev_err(component->dev,
"buffer preallocation failer error:%d\n", ret);
return ret;
}
@@ -1000,12 +1007,13 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
struct snd_pcm_runtime *runtime = substream->runtime;
struct audio_substream_data *rtd = runtime->private_data;
struct snd_soc_pcm_runtime *prtd = substream->private_data;
- struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev);
+ struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);
+ struct audio_drv_data *adata = dev_get_drvdata(component->dev);
kfree(rtd);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- adata->play_stream = NULL;
+ adata->play_i2ssp_stream = NULL;
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
* won't be turned off. The default state for SRAM banks is ON.
* Setting SRAM bank state code skipped for STONEY platform.
@@ -1017,7 +1025,7 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
false);
}
} else {
- adata->capture_stream = NULL;
+ adata->capture_i2ssp_stream = NULL;
if (adata->asic_type != CHIP_STONEY) {
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
@@ -1028,7 +1036,7 @@ static int acp_dma_close(struct snd_pcm_substream *substream)
/* Disable ACP irq, when the current stream is being closed and
* another stream is also not active.
*/
- if (!adata->play_stream && !adata->capture_stream)
+ if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream)
acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
return 0;
@@ -1046,7 +1054,8 @@ static const struct snd_pcm_ops acp_dma_ops = {
.prepare = acp_dma_prepare,
};
-static struct snd_soc_platform_driver acp_asoc_platform = {
+static struct snd_soc_component_driver acp_asoc_platform = {
+ .name = DRV_NAME,
.ops = &acp_dma_ops,
.pcm_new = acp_dma_new,
};
@@ -1078,8 +1087,9 @@ static int acp_audio_probe(struct platform_device *pdev)
* and device doesn't generate any interrupts.
*/
- audio_drv_data->play_stream = NULL;
- audio_drv_data->capture_stream = NULL;
+ audio_drv_data->play_i2ssp_stream = NULL;
+ audio_drv_data->capture_i2ssp_stream = NULL;
+
audio_drv_data->asic_type = *pdata;
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -1104,7 +1114,8 @@ static int acp_audio_probe(struct platform_device *pdev)
return status;
}
- status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform);
+ status = devm_snd_soc_register_component(&pdev->dev,
+ &acp_asoc_platform, NULL, 0);
if (status != 0) {
dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
return status;
@@ -1125,7 +1136,6 @@ static int acp_audio_remove(struct platform_device *pdev)
status = acp_deinit(adata->acp_mmio);
if (status)
dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
- snd_soc_unregister_platform(&pdev->dev);
pm_runtime_disable(&pdev->dev);
return 0;
@@ -1143,7 +1153,7 @@ static int acp_pcm_resume(struct device *dev)
return status;
}
- if (adata->play_stream && adata->play_stream->runtime) {
+ if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
/* For Stoney, Memory gating is disabled,i.e SRAM Banks
* won't be turned off. The default state for SRAM banks is ON.
* Setting SRAM bank state code skipped for STONEY platform.
@@ -1154,17 +1164,17 @@ static int acp_pcm_resume(struct device *dev)
true);
}
config_acp_dma(adata->acp_mmio,
- adata->play_stream->runtime->private_data,
+ adata->play_i2ssp_stream->runtime->private_data,
adata->asic_type);
}
- if (adata->capture_stream && adata->capture_stream->runtime) {
+ if (adata->capture_i2ssp_stream && adata->capture_i2ssp_stream->runtime) {
if (adata->asic_type != CHIP_STONEY) {
for (bank = 5; bank <= 8; bank++)
acp_set_sram_bank_state(adata->acp_mmio, bank,
true);
}
config_acp_dma(adata->acp_mmio,
- adata->capture_stream->runtime->private_data,
+ adata->capture_i2ssp_stream->runtime->private_data,
adata->asic_type);
}
acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-12 00:15:26 +0000