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2020-12-07media: ccs: Dual PLL supportSakari Ailus
2020-12-07media: ccs-pll: Add trivial dual PLL supportSakari Ailus
2020-12-07media: ccs-pll: Separate VT divisor limit calculation from the restSakari Ailus
2020-12-07media: ccs-pll: Fix VT post-PLL divisor calculationSakari Ailus
2020-12-07media: ccs-pll: Make VT divisors 16-bitSakari Ailus
2020-12-07media: ccs-pll: Rework bounds checksSakari Ailus
2020-12-07media: ccs-pll: Print relevant information on PLL treeSakari Ailus
2020-12-07media: ccs-pll: Better separate OP and VT sub-tree calculationSakari Ailus
2020-12-07media: ccs-pll: Check for derating and overrating, support non-derating sensorsSakari Ailus
2020-12-07media: ccs-pll: Split off VT subtree calculationSakari Ailus
2020-12-07media: ccs-pll: Add C-PHY supportSakari Ailus
2020-12-07media: ccs-pll: Add sanity checksSakari Ailus
2020-12-07media: ccs-pll: Add support flexible OP PLL pixel clock dividerSakari Ailus
2020-12-07media: ccs-pll: Support two cycles per pixel on OP domainSakari Ailus
2020-12-07media: ccs-pll: Add support for extended input PLL clock dividerSakari Ailus
2020-12-07media: ccs-pll: Add support for decoupled OP domain calculationSakari Ailus
2020-12-07media: ccs: Add support for lane speed modelSakari Ailus
2020-12-07media: ccs-pll: Add support for lane speed modelSakari Ailus
2020-12-07media: ccs-pll: Use explicit 32-bit unsigned typeSakari Ailus
2020-12-07media: ccs-pll: Fix check for PLL multiplier upper boundSakari Ailus
2020-12-07media: ccs-pll: Fix comment on check against maximum PLL multiplierSakari Ailus
2020-12-07media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound searchSakari Ailus
2020-12-07media: ccs-pll: Fix condition for pre-PLL divider lower boundSakari Ailus
2020-12-07media: ccs-pll: Begin calculation from OP system clock frequencySakari Ailus
2020-12-07media: ccs-pll: Use the BIT macroSakari Ailus
2020-12-07media: ccs-pll: Document the structs in the header as well as the functionSakari Ailus
2020-12-07media: ccs-pll: Move the flags field down, away from 8-bit fieldsSakari Ailus
2020-12-07media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHYSakari Ailus
2020-12-07media: ccs-pll: Remove parallel bus supportSakari Ailus
2020-12-07media: ccs-pll: End search if there are no better values availableSakari Ailus
2020-12-07media: ccs-pll: Use correct VT divisor for calculating VT SYS divisorSakari Ailus
2020-12-07media: ccs-pll: Split limits and PLL configuration into front and back partsSakari Ailus
2020-12-07media: ccs-pll: Don't use div_u64 to divide a 32-bit numberSakari Ailus
2020-12-07media: dt-bindings: schema indentation fixesRob Herring
2020-12-07media: vivid: fix 'disconnect' error injectionHans Verkuil
2020-12-07media: rcar-vin: Mask VNCSI_IFMD registerJacopo Mondi
2020-12-07media: MAINTAINERS: Add myself as maintainer of the Amlogic GE2D driverNeil Armstrong
2020-12-07media: meson: Add M2M driver for the Amlogic GE2D Accelerator UnitNeil Armstrong
2020-12-07media: dt-bindings: media: Add bindings for the Amlogic GE2D Accelerator UnitNeil Armstrong
2020-12-07media: cedrus: Make VP8 codec as capabilityJernej Skrabec
2020-12-07media: gspca: Fix memory leak in probeAlan Stern
2020-12-07media: doc: pixfmt-yuv: Move all planar YUV formats to common fileLaurent Pinchart
2020-12-07media: doc: pixfmt-yuv: Move all semi-planar YUV formats to common fileLaurent Pinchart
2020-12-07media: doc: pixfmt-yuv: Move all luma-only YUV formats to common fileLaurent Pinchart
2020-12-07media: doc: pixfmt-packed-yuv: Clarify naming scheme for 4:4:4 formatsLaurent Pinchart
2020-12-07media: doc: pixfmt-packed-yuv: Express 4:4:4 formats in a more compact wayLaurent Pinchart
2020-12-07media: doc: pixfmt-packed-yuv: Fill padding bits with 'X'Laurent Pinchart
2020-12-07media: doc: pixfmt-yuv: Move all packed YUV formats to common fileLaurent Pinchart
2020-12-07media: doc: pixfmt-yuv: Document subsampling in more detailsLaurent Pinchart
2020-12-07media: doc: pixfmt-rgb: Replace '-' with 'X' to denote paddingLaurent Pinchart
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