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path: root/arch/arm/mm/proc-v7-2level.S
AgeCommit message (Expand)Author
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
2018-05-31ARM: spectre-v2: harden branch predictor on context switchesRussell King
2015-06-12Merge branches 'arnd-fixes', 'clk', 'misc', 'v7' and 'fixes' into for-nextRussell King
2015-06-01ARM: redo TTBR setup code for LPAERussell King
2015-05-08ARM: 8353/1: mm: Fix Cortex-A8 erratum 430973 segfaults for bootloaders and m...Tony Lindgren
2015-04-14ARM: proc-v7: avoid errata 430973 workaround for non-Cortex A8 CPUsRussell King
2014-07-18ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+Russell King
2014-02-10ARM: 7954/1: mm: remove remaining domain support from ARMv6Will Deacon
2013-07-22ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2Will Deacon
2013-07-14arm: delete __cpuinit/__CPUINIT usage from all ARM usersPaul Gortmaker
2013-04-03ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP insteadWill Deacon
2013-02-16ARM: 7650/1: mm: replace direct access to mm->context.id with new macroBen Dooks
2012-11-09ARM: mm: introduce present, faulting entries for PAGE_NONEWill Deacon
2012-11-09ARM: mm: introduce L_PTE_VALID for page table entriesWill Deacon
2012-11-09ARM: mm: don't use the access flag permissions mechanism for classic MMUWill Deacon
2012-07-09ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current processWill Deacon
2012-04-17ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUsCatalin Marinas
2012-04-17ARM: Use TTBR1 instead of reserved context IDWill Deacon
2011-12-08ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.SCatalin Marinas