linux.git - Linux kernel

Age	Commit message (Collapse)	Author
2010-10-22	Blackfin: SIC: BF537: change default data/error relative priorities	Michael Hennerich
	Some peripherals might generate an error interrupt shortly after the data interrupt due to the fact that the peripheral isn't serviced fast enough. In most cases this isn't a problem and is expected behavior. This hasn't been a problem on most parts since you simply don't request the error interrupt (or you leave it disabled while there is an expected state) and do the peripheral status checking in the data interrupt. The Blackfin SIC allows people to prioritize data and error interrupts, and the Blackfin CEC allows interrupts of equal or higher priority to nest. The current default settings gives error interrupts a higher priority than data interrupts. So if an error occurs while processing the data interrupt, it will be serviced immediately. However, the error interrupt on the BF537 SIC cannot be enabled on a per-peripheral basis. Once the error interrupt is enabled for one peripheral, it is automatically enabled for all peripherals. Therefore lower the default multiplexed error interrupt priority so most people need not worry themselves with this issue. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-06-12	Blackfin: add support for gptimer0 as a tick source	Graf Yang
	For systems where the core cycles are not a usable tick source (like SMP or cycles gets updated), enable gptimer0 as an alternative. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-01-07	Blackfin arch: merge adeos blackfin part to arch/blackfin/	Yi Li
	[Mike Frysinger <vapier.adi@gmail.com>: - handle bf531/bf532/bf534/bf536 variants in ipipe.h - cleanup IPIPE logic for bfin_set_irq_handler() - cleanup ipipe asm code a bit and add missing ENDPROC() - simplify IPIPE code in trap_c - unify some of the IPIPE code and fix style - simplify DO_IRQ_L1 handling with ipipe code - revert IRQ_SW_INT# addition from ipipe merge - remove duplicate get_{c,s}clk() prototypes ] Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
2007-11-15	Blackfin arch: split board selection off into mach subdirs	Mike Frysinger
	Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-08-28	Blackfin arch: Remove legacy support	Michael Hennerich
	Now that there is a generic GPIO driver framework remove GPIO register unified name space legacy support. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-05-07	blackfin architecture	Bryan Wu
	This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>