aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv/kvm/vcpu.c
AgeCommit message (Expand)Author
2022-12-31RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config()Anup Patel
2022-10-21RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for SstcAnup Patel
2022-10-02RISC-V: KVM: Use generic guest entry infrastructureJisheng Zhang
2022-10-02RISC-V: KVM: Record number of signal exits as a vCPU statJisheng Zhang
2022-10-02RISC-V: KVM: Expose Zicbom to the guestAndrew Jones
2022-10-02RISC-V: KVM: Provide UAPI for Zicbom block sizeAndrew Jones
2022-10-02RISC-V: KVM: Make ISA ext mappings explicitAndrew Jones
2022-10-02RISC-V: KVM: Allow Guest use Zihintpause extensionMayuresh Chitale
2022-10-02RISC-V: KVM: Allow Guest use Svinval extensionAnup Patel
2022-08-12RISC-V: KVM: Support sstc extensionAtish Patra
2022-07-29RISC-V: KVM: Add support for Svpbmt inside Guest/VMAnup Patel
2022-07-29RISC-V: KVM: Add extensible CSR emulation frameworkAnup Patel
2022-07-29RISC-V: KVM: move preempt_disable() call in kvm_arch_vcpu_ioctl_runNikolay Borisov
2022-07-29RISC-V: KVM: Improve ISA extension by using a bitmapAtish Patra
2022-07-11RISC-V: KVM: Fix SRCU deadlock caused by kvm_riscv_check_vcpu_requests()Anup Patel
2022-05-20RISC-V: KVM: Introduce ISA extension registerAtish Patra
2022-05-20RISC-V: KVM: Cleanup stale TLB entries when host CPU changesAnup Patel
2022-05-20RISC-V: KVM: Add remote HFENCE functions based on VCPU requestsAnup Patel
2022-05-20RISC-V: KVM: Introduce range based local HFENCE functionsAnup Patel
2022-05-20RISC-V: KVM: Use G-stage name for hypervisor page tableAnup Patel
2022-04-21KVM: Add helpers to wrap vcpu->srcu_idx and yell if it's abusedSean Christopherson
2022-04-21KVM: RISC-V: Use kvm_vcpu.srcu_idx, drop RISC-V's unnecessary copySean Christopherson
2022-04-20RISC-V: KVM: Restrict the extensions that can be disabledAtish Patra
2022-04-20RISC-V: KVM: Remove 's' & 'u' as valid ISA extensionAtish Patra
2022-04-09RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put()Anup Patel
2022-02-02RISC-V: KVM: make CY, TM, and IR counters accessible in VU modeMayuresh Chitale
2022-02-02kvm/riscv: rework guest entry logicMark Rutland
2022-01-06RISC-V: KVM: Add SBI HSM extension in KVMAtish Patra
2022-01-06KVM: RISC-V: Use common KVM implementation of MMU memory cachesSean Christopherson
2021-11-17Documentation: update vcpu-requests.rst referenceMauro Carvalho Chehab
2021-11-01RISC-V: KVM: remove unneeded semicolonran jianping
2021-10-31RISC-V: KVM: Factor-out FP virtualization into separate sourcesAnup Patel
2021-10-04RISC-V: KVM: Add SBI v0.1 supportAtish Patra
2021-10-04RISC-V: KVM: Implement ONE REG interface for FP registersAtish Patra
2021-10-04RISC-V: KVM: FP lazy save/restoreAtish Patra
2021-10-04RISC-V: KVM: Add timer functionalityAtish Patra
2021-10-04RISC-V: KVM: Implement VMID allocatorAnup Patel
2021-10-04RISC-V: KVM: Implement VCPU world-switchAnup Patel
2021-10-04RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctlsAnup Patel
2021-10-04RISC-V: KVM: Implement VCPU interrupts and requests handlingAnup Patel
2021-10-04RISC-V: KVM: Implement VCPU create, init and destroy functionsAnup Patel
2021-10-04RISC-V: Add initial skeletal KVM supportAnup Patel