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path: root/arch/riscv/mm/tlbflush.c
AgeCommit message (Expand)Author
2023-03-30riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong
2023-03-22Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich
2023-01-07riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich
2022-01-20RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra
2021-06-30riscv: add ASID-based tlbflushing methodsGuo Ren
2021-06-30riscv: pass the mm_struct to __sbi_tlb_flush_rangeChristoph Hellwig
2021-05-22riscv: mm: add THP support on 64-bitNanyong Sun
2021-05-22riscv: mm: add param stride for __sbi_tlb_flush_rangeNanyong Sun
2019-10-29RISC-V: Issue a tlb page flush if possibleAtish Patra
2019-10-29RISC-V: Issue a local tlbflush if possible.Atish Patra
2019-10-29RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig