Age | Commit message (Expand) | Author |
---|---|---|
2023-03-30 | riscv: mm: Fix incorrect ASID argument when flushing TLB | Dylan Jhong |
2023-03-22 | Revert "riscv: mm: notify remote harts about mmu cache updates" | Sergey Matyukevich |
2023-01-07 | riscv: mm: notify remote harts about mmu cache updates | Sergey Matyukevich |
2022-01-20 | RISC-V: Do not use cpumask data structure for hartid bitmap | Atish Patra |
2021-06-30 | riscv: add ASID-based tlbflushing methods | Guo Ren |
2021-06-30 | riscv: pass the mm_struct to __sbi_tlb_flush_range | Christoph Hellwig |
2021-05-22 | riscv: mm: add THP support on 64-bit | Nanyong Sun |
2021-05-22 | riscv: mm: add param stride for __sbi_tlb_flush_range | Nanyong Sun |
2019-10-29 | RISC-V: Issue a tlb page flush if possible | Atish Patra |
2019-10-29 | RISC-V: Issue a local tlbflush if possible. | Atish Patra |
2019-10-29 | RISC-V: Do not invoke SBI call if cpumask is empty | Atish Patra |
2019-09-05 | riscv: move the TLB flush logic out of line | Christoph Hellwig |