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AgeCommit message (Expand)Author
2017-11-30RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macrosOlof Johansson
2017-11-30RISC-V: use generic serial.hOlof Johansson
2017-11-28RISC-V: remove spin_unlock_wait()Palmer Dabbelt
2017-11-28RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt
2017-11-28RISC-V: Add READ_ONCE in arch_spin_is_locked()Palmer Dabbelt
2017-11-28RISC-V: __test_and_op_bit_ord should be strongly orderedPalmer Dabbelt
2017-11-28RISC-V: Remove smb_mb__{before,after}_spinlock()Palmer Dabbelt
2017-11-28RISC-V: Remove __smp_bp__{before,after}_atomicPalmer Dabbelt
2017-11-28RISC-V: Comment on why {,cmp}xchg is ordered how it isPalmer Dabbelt
2017-11-28RISC-V: Remove unused arguments from ATOMIC_OPPalmer Dabbelt
2017-11-27RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpuAndrew Waterman
2017-11-27RISC-V: Remove __vdso_cmpxchg{32,64} symbol versionsPalmer Dabbelt
2017-11-15Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub...Linus Torvalds
2017-09-26RISC-V: Build InfrastructurePalmer Dabbelt
2017-09-26RISC-V: User-facing APIPalmer Dabbelt
2017-09-26RISC-V: Paging and MMUPalmer Dabbelt
2017-09-26RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt
2017-09-26RISC-V: Task implementationPalmer Dabbelt
2017-09-26RISC-V: ELF and module implementationPalmer Dabbelt
2017-09-26RISC-V: Generic library routines and assemblyPalmer Dabbelt
2017-09-26RISC-V: Atomic and Locking CodePalmer Dabbelt
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt