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path: root/drivers/clk/mediatek/clk-mt2701.c
AgeCommit message (Expand)Author
2023-11-20clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_dataJiasheng Jiang
2023-05-11clk: mediatek: Consistently use GATE_MTK() macroAngeloGioacchino Del Regno
2022-06-15clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen
2022-06-15clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen
2022-06-15clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen
2022-06-15clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen
2022-05-19clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai
2022-05-18clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner
2019-02-25clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_selchunhui dai
2018-08-30clk: mediatek: remove unused array audio_parentsColin Ian King
2018-05-15clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee
2018-03-19clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang
2017-11-02clk: mediatek: mark mtk_infrasys_init_early __initArnd Bergmann
2017-06-19clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang
2016-11-08reset: mediatek: Add MT2701 reset driverShunli Wang
2016-11-08clk: mediatek: Add MT2701 clock supportShunli Wang