| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-05-11 | clk: renesas: r9a06g032: Switch to .determine_rate() | Geert Uytterhoeven |
| 2021-03-30 | clk: renesas: Zero init clk_init_data | Geert Uytterhoeven |
| 2021-03-24 | clk: renesas: Couple of spelling fixes | Bhaskar Chowdhury |
| 2020-12-07 | clk: renesas: r9a06g032: Drop __packed for portability | Geert Uytterhoeven |
| 2020-04-14 | clk: renesas: r9a06g032: Fix some typo in comments | Christophe JAILLET |
| 2019-08-23 | clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain | Geert Uytterhoeven |
| 2019-06-04 | clk: renesas: r9a06g032: Add clock domain support | Gareth Williams |
| 2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd |
| 2019-04-02 | clk: renesas: r9a06g032: Add missing PCI USB clock | Gareth Williams |
| 2018-12-10 | clk: renesas: Remove usage of CLK_IS_BASIC | Stephen Boyd |
| 2018-09-11 | clk: renesas: r9a06g032: Fix UART34567 clock rate | Phil Edworthy |
| 2018-06-25 | clk: renesas: Renesas R9A06G032 clock driver | Michel Pollet |
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index : linux.git | |
| Linux kernel | git repo user |
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