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path: root/drivers/clk/renesas
AgeCommit message (Expand)Author
2021-12-08clk: renesas: r9a07g044: Add GPU clock and reset entriesBiju Das
2021-12-08clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das
2021-12-08clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macroBiju Das
2021-12-08clk: renesas: cpg-mssr: Add support for R-Car S4-8Yoshihiro Shimoda
2021-12-08clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverYoshihiro Shimoda
2021-11-26clk: renesas: r9a07g044: Add TSU clock and reset entryBiju Das
2021-11-19clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()Lad Prabhakar
2021-11-19clk: renesas: cpg-mssr: Check return value of pm_genpd_init()Lad Prabhakar
2021-11-19clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()Lad Prabhakar
2021-11-19clk: renesas: rzg2l: Check return value of pm_genpd_init()Lad Prabhakar
2021-11-19clk: renesas: r9a07g044: Add RSPI clock and reset entriesLad Prabhakar
2021-11-19clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIVBiju Das
2021-11-19clk: renesas: rzg2l: Add CPG_PL1_DDIV macroBiju Das
2021-11-19clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRSTWolfram Sang
2021-11-19clk: renesas: rcar-gen3: Switch to new SD clock handlingWolfram Sang
2021-11-19clk: renesas: r8a779a0: Add SDnH clock to V3UWolfram Sang
2021-11-19clk: renesas: rcar-gen3: Add SDnH clockWolfram Sang
2021-11-19clk: renesas: rcar-gen3: Add dummy SDnH clockWolfram Sang
2021-11-15clk: renesas: r9a07g044: Add OSTM clock and reset entriesBiju Das
2021-11-15clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macrosBiju Das
2021-11-15clk: renesas: r9a07g044: Add WDT clock and reset entriesBiju Das
2021-11-15clk: renesas: r9a07g044: Add clock and reset entry for SCI1Lad Prabhakar
2021-11-15clk: renesas: rzg2l: Add missing kerneldoc for resetsGeert Uytterhoeven
2021-10-15clk: renesas: r8a779[56]x: Add MLP clocksAndrey Gusakov
2021-10-08clk: renesas: r9a07g044: Add SDHI clock and reset entriesBiju Das
2021-10-08clk: renesas: rzg2l: Add SDHI clk mux supportBiju Das
2021-10-08clk: renesas: r8a779a0: Add RPC supportWolfram Sang
2021-10-08clk: renesas: cpg-lib: Move RPC clock registration to the libraryWolfram Sang
2021-10-08clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...Lad Prabhakar
2021-09-28clk: renesas: r8a779a0: Add Z0 and Z1 clock supportGeert Uytterhoeven
2021-09-24clk: renesas: r9a07g044: Add GbEthernet clock/resetBiju Das
2021-09-24clk: renesas: rzg2l: Add support to handle coupled clocksBiju Das
2021-09-24clk: renesas: r9a07g044: Add ethernet clock sourcesBiju Das
2021-09-24clk: renesas: rzg2l: Add support to handle MUX clocksBiju Das
2021-09-24clk: renesas: r8a779a0: Add TPU clockWolfram Sang
2021-09-24clk: renesas: rzg2l: Fix clk status functionBiju Das
2021-09-24clk: renesas: r9a07g044: Mark IA55_CLK and DMAC_ACLK criticalBiju Das
2021-09-02Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2021-08-29Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds
2021-08-28clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereferenceAdam Ford
2021-08-13clk: renesas: Make CLK_R9A06G032 invisibleGeert Uytterhoeven
2021-07-26clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for CANFDLad Prabhakar
2021-07-19clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]Geert Uytterhoeven
2021-07-19clk: renesas: r9a07g044: Add GPIO clock and reset entriesLad Prabhakar
2021-07-19clk: renesas: r9a07g044: Add SSIF-2 clock and reset entriesBiju Das
2021-07-19clk: renesas: r9a07g044: Add USB clocks/resetsBiju Das
2021-07-19clk: renesas: r9a07g044: Add DMAC clocks/resetsBiju Das
2021-07-19clk: renesas: r9a07g044: Add I2C clocks/resetsBiju Das