linux.git - Linux kernel

Age	Commit message (Expand)	Author
2019-07-17	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds
2019-06-27	clk: rockchip: export HDMIPHY clock on rk3228	Heiko Stuebner
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	Thomas Gleixner
2019-05-20	clk: rockchip: add 1.464GHz cpu-clock rate to rk3228	Justin Swartz
2019-05-15	clk: Remove io.h from clk-provider.h	Stephen Boyd
2018-03-23	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	Shawn Lin
2017-08-22	clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id	Elaine Zhang
2017-06-02	clk: rockchip: mark noc and some special clk as critical on rk3228	Elaine Zhang
2017-06-02	clk: rockchip: export more rk3228 clocks ids	Elaine Zhang
2017-05-17	clk: rockchip: fix up the RK3228 clk cpu setting table	Elaine Zhang
2016-07-01	clk: rockchip: export rk3228 MAC clocks	Xing Zheng
2016-07-01	clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk	Xing Zheng
2016-07-01	clk: rockchip: export rk3228 audio clocks	Xing Zheng
2016-07-01	clk: rockchip: include rk3228 downstream muxes into fractional dividers	Xing Zheng
2016-06-22	clk: rockchip: fix incorrect rk3228 clock registers	Xing Zheng
2016-03-27	clk: rockchip: release io resource when failing to init clk	Shawn Lin
2016-03-27	clk: rockchip: Add support for multiple clock providers	Xing Zheng
2016-03-27	clk: rockchip: allow varying mux parameters for cpuclk pll-sources	Xing Zheng
2016-02-26	clk: rockchip: set the clock ids for RK3228 HDMI	Yakir Yang
2016-02-26	clk: rockchip: set the clock ids for RK3228 VOP	Yakir Yang
2016-02-26	clk: rockchip: add the tsadc clocks found on rk3228 SoCs	Caesar Wang
2016-02-04	clk: rockchip: convert manually created factor clocks to the new type	Heiko Stuebner
2016-01-28	clk: rockchip: fix wrong mmc phase shift for rk3228	Shawn Lin
2015-12-21	clk: rockchip: only enter pll slow-mode directly before reboots on rk3288	Heiko Stuebner
2015-12-12	clk: rockchip: add clock controller for rk3228	Jeffy Chen