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path: root/drivers/clk/socfpga/clk-agilex.c
AgeCommit message (Expand)Author
2021-09-24clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen
2021-07-26clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen
2021-07-26clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen
2021-07-26clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen
2021-06-27clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen
2021-06-27clk: agilex/stratix10: fix bypass representationDinh Nguyen
2021-06-27clk: agilex/stratix10: remove noc_clkDinh Nguyen
2021-03-30clk: socfpga: Fix code formattingStephen Boyd
2021-03-30clk: socfpga: Convert to s10/agilex/n5x to use clk_hwDinh Nguyen
2021-02-12clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen
2020-09-22clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing
2020-06-19clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen
2020-06-19clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen
2020-05-26clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 09:49:43 +0000