| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-11-28 | clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data | Gustavo A. R. Silva |
| 2021-06-27 | clk: agilex/stratix10: add support for the 2nd bypass | Dinh Nguyen |
| 2021-03-30 | clk: socfpga: Convert to s10/agilex/n5x to use clk_hw | Dinh Nguyen |
| 2021-02-12 | clk: socfpga: agilex: add clock driver for eASIC N5X platform | Dinh Nguyen |
| 2020-05-26 | clk: socfpga: agilex: add clock driver for the Agilex platform | Dinh Nguyen |
| 2020-05-26 | clk: socfpga: stratix10: use new parent data scheme | Dinh Nguyen |
| 2020-02-12 | clk: socfpga: stratix10: simplify parameter passing | Dinh Nguyen |
| 2018-04-06 | clk: socfpga: stratix10: add clock driver for Stratix10 platform | Dinh Nguyen |
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