aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/sunxi/clk-sunxi.c
AgeCommit message (Expand)Author
2015-02-21Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds
2015-02-02clk: Add rate constraints to clocksTomeu Vizoso
2015-01-25sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede
2015-01-14clk: sunxi: Remove custom phase functionMaxime Ripard
2015-01-06clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai
2015-01-05ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede
2014-12-21clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede
2014-12-21clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai
2014-12-21clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai
2014-11-23clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai
2014-11-23clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai
2014-11-23clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai
2014-11-11clk: sunxi: unify APB1 clockEmilio López
2014-10-21clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai
2014-10-21clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai
2014-09-27clk: sunxi: Move mbus to mod0 fileMaxime Ripard
2014-09-27clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard
2014-09-27clk: sunxi: Introduce mbus compatibleMaxime Ripard
2014-09-27clk: sunxi: factors: Invert the probing logicMaxime Ripard
2014-09-13clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai
2014-07-28clk: sunxi: add __iomem markings to MMIO pointersEmilio López
2014-07-04clk: sunxi: Add A23 clocks supportChen-Yu Tsai
2014-07-04clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai
2014-07-04clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai
2014-07-04clk: sunxi: register clock gates with clkdevChen-Yu Tsai
2014-06-11clk: sun6i: Protect SDRAM gating bitMaxime Ripard
2014-06-11clk: sun6i: Protect CPU clockMaxime Ripard
2014-06-11clk: sunxi: Rework clock protection codeMaxime Ripard
2014-06-11clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard
2014-06-11clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard
2014-06-11clk: sunxi: Remove calls to clk_putMaxime Ripard
2014-06-11clk: sunxi: Implement A31 USB clockMaxime Ripard
2014-06-07Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds
2014-05-20clk: sunxi: fix function type for CLK_OF_DECLARERob Herring
2014-05-20clk: sunxi: avoid double DT matchingRob Herring
2014-05-14clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clkHans de Goede
2014-05-05clk: sunxi: Implement MMC phase controlEmilio López
2014-03-19clk: sunxi: fix thinko in commentEmilio López
2014-03-19clk: sunxi: fix some calculationsEmilio López
2014-03-19clk: sunxi: fix A20 PLL4 calculationEmilio López
2014-02-18clk: sunxi: Add new clock compatiblesMaxime Ripard
2014-02-18clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai
2014-02-18clk: sunxi: Add support for PLL6 on the A31Maxime Ripard
2014-02-18clk: sunxi: Add USB clock register defintionsRoman Byshko
2014-02-18clk: sunxi: Add support for USB clock-register reset bitsHans de Goede
2014-02-03clk: sunxi: get divs parent clock name from parent factor clockChen-Yu Tsai
2014-02-03clk: sunxi: add names for pll5, pll6 parent clocks to factors_dataChen-Yu Tsai
2014-02-03clk: sunxi: add clock-output-names dt property supportChen-Yu Tsai
2014-01-27clk: sunxi: fix overflow when setting up divided factorsEmilio López
2013-12-28clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 11:58:37 +0000