| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2014-02-17 | clk: tegra: cclk_lp has a pllx/2 divider | Andrew Bresticker | |
| When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines whether cclk_lp output is divided by 2. Set TEGRA_DIVIDER_2 so that the clk_super driver is aware of this. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> | |||
| 2013-11-26 | clk: tegra: introduce common gen4 super clock | Peter De Schrijver | |
| Introduce a common function which performs super clock initialization for Tegra114 and beyond. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> | |||
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