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path: root/drivers/clk/tegra
AgeCommit message (Expand)Author
2020-01-10clk: tegra20/30: Explicitly set parent clock for Video DecoderDmitry Osipenko
2020-01-10clk: tegra20/30: Don't pre-initialize displays parent clockDmitry Osipenko
2020-01-10clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul...Dmitry Osipenko
2020-01-10clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe()Sowjanya Komatineni
2020-01-08clk: tegra: Mark fuse clock as criticalStephen Warren
2019-11-13clk: tegra: Use match_string() helper to simplify the codeYueHaibing
2019-11-11clk: tegra: Fix build error without CONFIG_PM_SLEEPYueHaibing
2019-11-11clk: tegra: Optimize PLLX restore on Tegra20/30Dmitry Osipenko
2019-11-11clk: tegra: Add suspend and resume support on Tegra210Sowjanya Komatineni
2019-11-11clk: tegra: Share clk and rst register defines with Tegra clock driverSowjanya Komatineni
2019-11-11clk: tegra: Use fence_udelay() during PLLU initSowjanya Komatineni
2019-11-11clk: tegra: clk-dfll: Add suspend and resume supportSowjanya Komatineni
2019-11-11clk: tegra: clk-super: Add restore-context supportSowjanya Komatineni
2019-11-11clk: tegra: clk-super: Fix to enable PLLP branches to CPUSowjanya Komatineni
2019-11-11clk: tegra: periph: Add restore_context supportSowjanya Komatineni
2019-11-11clk: tegra: Support for OSC context save and restoreSowjanya Komatineni
2019-11-11clk: tegra: pll: Save and restore pll contextSowjanya Komatineni
2019-11-11clk: tegra: pllout: Save and restore pllout contextSowjanya Komatineni
2019-11-11clk: tegra: divider: Save and restore divider rateSowjanya Komatineni
2019-11-11clk: tegra: Reimplement SOR clocks on Tegra210Thierry Reding
2019-11-11clk: tegra: Reimplement SOR clock on Tegra124Thierry Reding
2019-11-11clk: tegra: Rename sor0_lvds to sor0_outThierry Reding
2019-11-11clk: tegra: Move SOR0 implementation to Tegra124Thierry Reding
2019-11-11clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRCThierry Reding
2019-11-11clk: tegra: Add Tegra20/30 EMC clock implementationDmitry Osipenko
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2019-06-28Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds
2019-06-25clk: tegra: Do not enable PLL_RE_VCO on Tegra210Thierry Reding
2019-06-25clk: tegra: Warn if an enabled PLL is in IDDQThierry Reding
2019-06-25clk: tegra: Do not warn unnecessarilyThierry Reding
2019-06-25clk: tegra210: fix PLLU and PLLU_OUT1JC Kuo
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
2019-06-14clk: tegra210: Fix default rates for HDA clocksJon Hunter
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd
2019-04-25clk: tegra: divider: Mark Memory Controller clock as read-onlyDmitry Osipenko
2019-04-25clk: tegra: emc: Replace BUG() with WARN_ONCE()Dmitry Osipenko
2019-04-25clk: tegra: emc: Fix EMC max-rate clampingDmitry Osipenko
2019-04-25clk: tegra: emc: Support multiple RAM codesDmitry Osipenko
2019-04-25clk: tegra: emc: Don't enable EMC clock manuallyDmitry Osipenko
2019-04-25clk: tegra124: Remove lock-enable bit from PLLMDmitry Osipenko
2019-04-25clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides dividerDmitry Osipenko
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski
2019-04-19clk: tegra: Don't enable already enabled PLLsDmitry Osipenko
2019-04-11clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing
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