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path: root/drivers/clk/tegra
AgeCommit message (Expand)Author
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-...Stephen Boyd
2019-04-23clk: core: replace clk_{readl,writel} with {readl,writel}Jonas Gorski
2019-04-11clk: tegra: Make tegra_clk_super_mux_ops staticYueHaibing
2019-03-14Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2019-03-08Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and ...Stephen Boyd
2019-02-22clk: tegra: dfll: Fix debugfs_simple_attr.cocci warningsYueHaibing
2019-02-18clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' staticWei Yongjun
2019-02-15Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo
2019-02-06clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver
2019-01-09clk: tegra: dfll: Fix a potential Oop in remove()Dan Carpenter
2018-12-14Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd
2018-12-14clk: tegra: Return the exact clock rate from clk_round_rateRobert Yang
2018-12-14clk: tegra30: Use Tegra CPU powergate helper functionJon Hunter
2018-12-14clk: tegra: Fix maximum audio sync clock for Tegra124/210Jon Hunter
2018-12-14clk: tegra: get rid of duplicate definesMarcel Ziswiler
2018-11-28clk: tegra: Change to use DEFINE_SHOW_ATTRIBUTE macroYangtao Li
2018-11-08clk: tegra20: Check whether direct PLLM sourcing is turned off for EMCDmitry Osipenko
2018-11-08clk: tegra20: Turn EMC clock gate into dividerDmitry Osipenko
2018-10-16clk: tegra210: Include size.h for compilation easeStephen Boyd
2018-10-16clk: tegra: Fixes for MBIST work aroundJoseph Lo
2018-10-16clk: tegra: probe deferral error reportingMarcel Ziswiler
2018-08-14Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',...Stephen Boyd
2018-08-14Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-te...Stephen Boyd
2018-07-25clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocksPeter De-Schrijver
2018-07-25clk: tegra: Add sdmmc mux divider clockPeter De-Schrijver
2018-07-25clk: tegra: Refactor fractional divider calculationPeter De Schrijver
2018-07-25clk: tegra: Fix includes required by fence_udelay()Aapo Vienamo
2018-07-08clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko
2018-07-08clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko
2018-07-08clk: tegra: Make vde a child of pll_c3Thierry Reding
2018-07-08clk: tegra: Make vic03 a child of pll_c3Thierry Reding
2018-07-08clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen
2018-06-12treewide: kzalloc() -> kcalloc()Kees Cook
2018-06-04Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' and...Stephen Boyd
2018-06-01clk: tegra: no need to check return value of debugfs_create functionsGreg Kroah-Hartman
2018-05-18clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20Dmitry Osipenko
2018-05-18clk: tegra20: Correct parents of CDEV1/2 clocksDmitry Osipenko
2018-05-18clk: tegra20: Add DEV1/DEV2 OSC dividersDmitry Osipenko
2018-03-12clk: tegra: Fix pll_u rate configurationMarcel Ziswiler
2018-03-12clk: tegra: Specify VDE clock rateDmitry Osipenko
2018-03-12clk: tegra20: Correct PLL_C_OUT1 setupDmitry Osipenko
2018-03-12clk: tegra: Mark HCLK, SCLK and EMC as criticalDmitry Osipenko
2018-03-08clk: tegra: MBIST work around for Tegra210Peter De Schrijver
2018-03-08clk: tegra: add fence_delay for clock registersPeter De Schrijver
2018-03-08clk: tegra: Add la clock for Tegra210Peter De Schrijver