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path: root/drivers/clk/visconti
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2022-03-17clk: visconti: prevent array overflow in visconti_clk_register_gates()Dan Carpenter
This code was using -1 to represent that there was no reset function. Unfortunately, the -1 was stored in u8 so the if (clks[i].rs_id >= 0) condition was always true. This lead to an out of bounds access in visconti_clk_register_gates(). Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220316083533.GA30941@kili Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-13clk: visconti: Fix uninitialized variable in printkDan Carpenter
The "pll_clck" variable is uninitialized. The "ret" error code was supposed to be printed instead. Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220111072529.GJ11243@kili Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-07clk: visconti: Remove pointless NULL check in visconti_pll_add_lookup()Nathan Chancellor
Clang warns: drivers/clk/visconti/pll.c:292:20: warning: address of array 'ctx->clk_data.hws' will always evaluate to 'true' [-Wpointer-bool-conversion] if (ctx->clk_data.hws && id) ~~~~~~~~~~~~~~^~~ ~~ 1 warning generated. This array cannot be NULL if ctx is not NULL, which is allocated in visconti_init_pll(), so just remove the check, which matches other clk drivers. Fixes: b4cbe606dc36 ("clk: visconti: Add support common clock driver and reset driver") Link: https://github.com/ClangBuiltLinux/linux/issues/1564 Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20220107183303.2337676-1-nathan@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-05clk: visconti: Add support common clock driver and reset driverNobuhiro Iwamatsu
Add support for common interface of the common clock and reset driver for Toshiba Visconti5 and its SoC, TMPV7708. The PIPLLCT provides the PLL, and the PISMU provides clock and reset functionality. Each drivers are provided in this patch. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Link: https://lore.kernel.org/r/20211025031038.4180686-4-nobuhiro1.iwamatsu@toshiba.co.jp [sboyd@kernel.org: Add bitfield.h include to pll.c] Signed-off-by: Stephen Boyd <sboyd@kernel.org>