| Age | Commit message (Expand) | Author |
|---|
| 2021-07-12 | dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions | Biju Das |
| 2021-07-12 | clk: renesas: r9a07g044: Add P2 Clock support | Biju Das |
| 2021-07-12 | clk: renesas: r9a07g044: Fix P1 Clock | Biju Das |
| 2021-07-12 | clk: renesas: r9a07g044: Rename divider table | Biju Das |
| 2021-07-12 | clk: renesas: rzg2l: Add multi clock PM support | Biju Das |
| 2021-07-08 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds |
| 2021-07-02 | Merge branch 'akpm' (patches from Andrew) | Linus Torvalds |
| 2021-07-01 | Revert "clk: divider: Switch from .round_rate to .determine_rate by default" | Stephen Boyd |
| 2021-07-01 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds |
| 2021-07-01 | kernel.h: split out panic and oops helpers | Andy Shevchenko |
| 2021-06-30 | clk: hisilicon: hi3559a: Drop __init markings everywhere | Stephen Boyd |
| 2021-06-30 | clk: meson: regmap: switch to determine_rate for the dividers | Martin Blumenstingl |
| 2021-06-30 | clk: divider: Switch from .round_rate to .determine_rate by default | Martin Blumenstingl |
| 2021-06-30 | clk: divider: Add re-usable determine_rate implementations | Martin Blumenstingl |
| 2021-06-30 | clk: k210: Fix k210_clk_set_parent() | Damien Le Moal |
| 2021-06-30 | clk: lmk04832: Fix spelling mistakes in dev_err messages and comments | Colin Ian King |
| 2021-06-30 | clk: lmk04832: fix return value check in lmk04832_probe() | Wang Hai |
| 2021-06-30 | clk: stm32mp1: fix missing spin_lock_init() | Wang Hai |
| 2021-06-29 | Merge branches 'clk-st', 'clk-si' and 'clk-hisilicon' into clk-next | Stephen Boyd |
| 2021-06-29 | Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-... | Stephen Boyd |
| 2021-06-29 | Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk... | Stephen Boyd |
| 2021-06-29 | Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'cl... | Stephen Boyd |
| 2021-06-29 | Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and '... | Stephen Boyd |
| 2021-06-28 | clk: zynqmp: Handle divider specific read only flag | Rajan Vaja |
| 2021-06-28 | clk: zynqmp: Use firmware specific mux clock flags | Rajan Vaja |
| 2021-06-28 | clk: zynqmp: Use firmware specific divider clock flags | Rajan Vaja |
| 2021-06-28 | clk: zynqmp: Use firmware specific common clock flags | Rajan Vaja |
| 2021-06-28 | clk: lmk04832: Use of match table | Stephen Boyd |
| 2021-06-28 | clk: lmk04832: Depend on SPI | Stephen Boyd |
| 2021-06-28 | clk: stm32mp1: new compatible for secure RCC support | Gabriel Fernandez |
| 2021-06-27 | clk: hisilicon: Add clock driver for hi3559A SoC | Dongjiu Geng |
| 2021-06-27 | clk: si5341: Add sysfs properties to allow checking/resetting device faults | Robert Hancock |
| 2021-06-27 | clk: si5341: Add silabs,iovdd-33 property | Robert Hancock |
| 2021-06-27 | clk: si5341: Add silabs,xaxb-ext-clk property | Robert Hancock |
| 2021-06-27 | clk: si5341: Allow different output VDD_SEL values | Robert Hancock |
| 2021-06-27 | clk: si5341: Update initialization magic | Robert Hancock |
| 2021-06-27 | clk: si5341: Check for input clock presence and PLL lock on startup | Robert Hancock |
| 2021-06-27 | clk: si5341: Avoid divide errors due to bogus register contents | Robert Hancock |
| 2021-06-27 | clk: si5341: Wait for DEVICE_READY on startup | Robert Hancock |
| 2021-06-27 | drivers: ti: remove redundant error message in adpll.c | Yu Jiahua |
| 2021-06-27 | clk: st: clkgen-fsyn: embed soc clock outputs within compatible data | Alain Volmat |
| 2021-06-27 | clk: st: clkgen-pll: embed soc clock outputs within compatible data | Alain Volmat |
| 2021-06-27 | clk: st: flexgen: embed soc clock outputs within compatible data | Alain Volmat |
| 2021-06-27 | clk: st: clkgen-pll: remove unused variable of struct clkgen_pll | Alain Volmat |
| 2021-06-27 | clk: ingenic: Add support for the JZ4760 | Paul Cercueil |
| 2021-06-27 | clk: ingenic: Support overriding PLLs M/N/OD calc algorithm | Paul Cercueil |
| 2021-06-27 | clk: ingenic: Remove pll_info.no_bypass_bit | Paul Cercueil |
| 2021-06-27 | clk: ingenic: Read bypass register only when there is one | Paul Cercueil |
| 2021-06-27 | clk: Support bypassing dividers | Paul Cercueil |
| 2021-06-27 | clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare | Jonathan Marek |
