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path: root/drivers/cxl/core
AgeCommit message (Expand)Author
2022-11-04cxl/region: Recycle region idsDan Williams
2022-11-04cxl/region: Fix 'distance' calculation with passthrough portsDan Williams
2022-11-04cxl/pmem: Fix cxl_pmem_region and cxl_memdev leakDan Williams
2022-11-04cxl/region: Fix cxl_region leak, cleanup targets at region deleteDan Williams
2022-11-04cxl/region: Fix region HPA ordering validationDan Williams
2022-11-01cxl/region: Fix decoder allocation crashVishal Verma
2022-10-20cxl/region: Fix null pointer dereference due to pass through decoder commitJonathan Cameron
2022-10-20cxl/mbox: Add a check on input payload sizeJonathan Cameron
2022-08-05cxl/hdm: Fix skip allocations vs multiple pmem allocationsDan Williams
2022-08-05cxl/region: Disallow region granularity != window granularityDan Williams
2022-08-05cxl/region: Fix x1 interleave to greater than x1 interleave routingDan Williams
2022-08-05cxl/region: Move HPA setup to cxl_region_attach()Dan Williams
2022-08-05cxl/region: Fix decoder interleave programmingDan Williams
2022-08-05cxl/regions: add padding for cxl_rr_ep_add nested listsBagas Sanjaya
2022-08-05cxl/region: Fix region reference target accountingDan Williams
2022-08-05cxl/region: Fix region commit uninitialized variable warningDan Williams
2022-08-05cxl/region: Fix port setup uninitialized variable warningsDan Williams
2022-08-01cxl/region: Stop initializing interleave granularityDan Williams
2022-08-01cxl/hdm: Fix DPA reservation vs cxl_endpoint_decoder lifetimeDan Williams
2022-08-01cxl/region: Delete 'region' attribute from root decodersDan Williams
2022-08-01cxl/region: decrement ->nr_targets on error in cxl_region_attach()Dan Carpenter
2022-08-01cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter
2022-08-01cxl/region: uninitialized variable in alloc_hpa()Dan Carpenter
2022-07-26cxl/region: Introduce cxl_pmem_region objectsDan Williams
2022-07-26cxl/region: Add region driver boiler plateDan Williams
2022-07-25cxl/hdm: Commit decoder state to hardwareDan Williams
2022-07-25cxl/region: Program target listsDan Williams
2022-07-25cxl/region: Attach endpoint decodersDan Williams
2022-07-25cxl/acpi: Add a host-bridge index lookup mechanismDan Williams
2022-07-25cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams
2022-07-25cxl/region: Allocate HPA capacity to regionsDan Williams
2022-07-25cxl/region: Add interleave geometry attributesBen Widawsky
2022-07-25cxl/region: Add a 'uuid' attributeBen Widawsky
2022-07-21cxl/region: Add region creation supportBen Widawsky
2022-07-21cxl/mem: Enumerate port targets before adding endpointsDan Williams
2022-07-21cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky
2022-07-21cxl/port: Move dport tracking to an xarrayDan Williams
2022-07-21cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams
2022-07-21cxl/port: Record parent dport when adding portsDan Williams
2022-07-21cxl/port: Record dport in endpoint referencesDan Williams
2022-07-21cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams
2022-07-21cxl/hdm: Track next decoder to allocateDan Williams
2022-07-21cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams
2022-07-21cxl/hdm: Enumerate allocated DPADan Williams
2022-07-21cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams
2022-07-21cxl/core: Define a 'struct cxl_root_decoder'Dan Williams
2022-07-21cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams
2022-07-19cxl/port: Read CDAT tableIra Weiny
2022-07-10cxl/hdm: Initialize decoder type for memory expander devicesDan Williams
2022-07-10cxl/port: Cache CXL host bridge dataDan Williams
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