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path: root/drivers/gpu/drm/i915/intel_psr.c
AgeCommit message (Expand)Author
2016-04-07drm/i915: Do not use {HAS_*, IS_*, INTEL_INFO}(dev_priv->dev)Joonas Lahtinen
2016-03-10Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."Ville Syrjälä
2016-03-03drm/i915: Add wait_for_usTvrtko Ursulin
2016-02-17drm/i915: Enable PSR by default on Haswell and Broadwell.Rodrigo Vivi
2016-02-17drm/i915: Enable PSR by default on Valleyview and Cherryview.Rodrigo Vivi
2016-02-17drm/i915: Change i915.enable_psr parameter to use per platform default.Rodrigo Vivi
2016-02-01drm/i915: Instrument PSR parameter for debuging with link standby x link off.Rodrigo Vivi
2016-02-01drm/i915: Add PSR main link standby support backRodrigo Vivi
2016-02-01drm/i915: PSR simplify port and link standby checks.Rodrigo Vivi
2015-12-11drm/i915: PSR also doesn't have link_entry_time on SKL.Rodrigo Vivi
2015-12-10drm/i915: Separate cherryview from valleyviewWayne Boyer
2015-12-07drm/i915: Fix idle_frames counter.Rodrigo Vivi
2015-11-24drm/i915: Also disable PSR on Sink when disabling it on Source.Rodrigo Vivi
2015-11-24drm/i915: PSR: Mask LPSP hw tracking back again.Rodrigo Vivi
2015-11-24drm/i915: PSR: Let's rely more on frontbuffer tracking.Rodrigo Vivi
2015-11-24drm/i915: Remove duplicated dpcd write on hsw_psr_enable_sink.Rodrigo Vivi
2015-11-18drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.Rodrigo Vivi
2015-11-18drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.Rodrigo Vivi
2015-11-18drm/i915: Reduce PSR re-activation time for VLV/CHV.Rodrigo Vivi
2015-11-18drm/i915: Delay first PSR activation.Rodrigo Vivi
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä
2015-11-16drm/i915: Model PSR AUX register selection more like the normal AUX codeVille Syrjälä
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä
2015-11-16drm/i915: Parametrize AUX registersVille Syrjälä
2015-10-13drm/i915: Parametrize HSW video DIP data registersVille Syrjälä
2015-08-05drm/i915: VLV/CHV PSR: Increase wait delay time before active PSR.Rodrigo Vivi
2015-07-09drm/i915: PSR: Increase idle_framesRodrigo Vivi
2015-07-09drm/i915: PSR: Remove Low Power HW tracking mask.Rodrigo Vivi
2015-07-09drm/i915: PSR: Flush means invalidate + flushRodrigo Vivi
2015-06-24drm/i915/psr: Restrict single-shot updates to the PSR pipeDaniel Vetter
2015-06-24drm/i915/psr: Restrict buffer tracking to the PSR pipeDaniel Vetter
2015-04-14drm/i915: PSR VLV: Add single frame update.Rodrigo Vivi
2015-04-14drm/i915: PSR: deprecate link_standby support for core platforms.Rodrigo Vivi
2015-04-14drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logicRodrigo Vivi
2015-04-14drm/i915: PSR: Remove wrong LINK_DISABLE.Rodrigo Vivi
2015-04-07drm/i915/skl: Enabling PSR2 SU with frame syncSonika Jindal
2015-03-30drm/i915: PSR: Keep sink state consistent with sourceDurgadoss R
2015-03-26drm/i915: Remove duplicated psr.active unsetRodrigo Vivi
2015-01-28drm/i915/skl: Enabling PSR on SkylakeSonika Jindal
2015-01-27drm/i915: Make intel_crtc->config a pointerAnder Conselvan de Oliveira
2015-01-27drm/i915: Embedded struct drm_crtc_state in intel_crtc_stateAnder Conselvan de Oliveira
2015-01-15drm/i915: group link_standby setup and let this info visible everywhere.Rodrigo Vivi
2015-01-15drm/i915: Add missing vbt check.Rodrigo Vivi
2015-01-15drm/i915: PSR HSW/BDW: Fix inverted logic at sink main_link_active bit.Rodrigo Vivi
2015-01-15drm/i915: PSR VLV/CHV: Remove condition checks that only applies to Haswell.Rodrigo Vivi
2015-01-15drm/i915: VLV/CHV PSR needs to exit PSR on every flush.Rodrigo Vivi
2014-12-03drm/i915: VLV/CHV PSR Software timer modeRodrigo Vivi
2014-12-03drm/i915: PSR VLV/CHV: Introduce setup, enable and disable functionsRodrigo Vivi
2014-12-03drm/i915: Remove intel_psr_is_enabled function.Rodrigo Vivi
2014-12-03drm/i915: remove PSR BDW single frame update.Rodrigo Vivi
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