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2021-02-25Merge tag 'pci-v5.12-changes' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Remove unnecessary locking around _OSC (Bjorn Helgaas) - Clarify message about _OSC failure (Bjorn Helgaas) - Remove notification of PCIe bandwidth changes (Bjorn Helgaas) - Tidy checking of syscall user config accessors (Heiner Kallweit) Resource management: - Decline to resize resources if boot config must be preserved (Ard Biesheuvel) - Fix pci_register_io_range() memory leak (Geert Uytterhoeven) Error handling (Keith Busch): - Clear error status from the correct device - Retain error recovery status so drivers can use it after reset - Log the type of Port (Root or Switch Downstream) that we reset - Always request a reset for Downstream Ports in frozen state Endpoint framework and NTB (Kishon Vijay Abraham I): - Make *_get_first_free_bar() take into account 64 bit BAR - Add helper API to get the 'next' unreserved BAR - Make *_free_bar() return error codes on failure - Remove unused pci_epf_match_device() - Add support to associate secondary EPC with EPF - Add support in configfs to associate two EPCs with EPF - Add pci_epc_ops to map MSI IRQ - Add pci_epf_ops to expose function-specific attrs - Allow user to create sub-directory of 'EPF Device' directory - Implement ->msi_map_irq() ops for cadence - Configure LM_EP_FUNC_CFG based on epc->function_num_map for cadence - Add EP function driver to provide NTB functionality - Add support for EPF PCI Non-Transparent Bridge - Add specification for PCI NTB function device - Add PCI endpoint NTB function user guide - Add configfs binding documentation for pci-ntb endpoint function Broadcom STB PCIe controller driver: - Add support for BCM4908 and external PERST# signal controller (Rafał Miłecki) Cadence PCIe controller driver: - Retrain Link to work around Gen2 training defect (Nadeem Athani) - Fix merge botch in cdns_pcie_host_map_dma_ranges() (Krzysztof Wilczyński) Freescale Layerscape PCIe controller driver: - Add LX2160A rev2 EP mode support (Hou Zhiqiang) - Convert to builtin_platform_driver() (Michael Walle) MediaTek PCIe controller driver: - Fix OF node reference leak (Krzysztof Wilczyński) Microchip PolarFlare PCIe controller driver: - Add Microchip PolarFire PCIe controller driver (Daire McNamara) Qualcomm PCIe controller driver: - Use PHY_REFCLK_USE_PAD only for ipq8064 (Ansuel Smith) - Add support for ddrss_sf_tbu clock for sm8250 (Dmitry Baryshkov) Renesas R-Car PCIe controller driver: - Drop PCIE_RCAR config option (Lad Prabhakar) - Always allocate MSI addresses in 32bit space (Marek Vasut) Rockchip PCIe controller driver: - Add FriendlyARM NanoPi M4B DT binding (Chen-Yu Tsai) - Make 'ep-gpios' DT property optional (Chen-Yu Tsai) Synopsys DesignWare PCIe controller driver: - Work around ECRC configuration hardware defect (Vidya Sagar) - Drop support for config space in DT 'ranges' (Rob Herring) - Change size to u64 for EP outbound iATU (Shradha Todi) - Add upper limit address for outbound iATU (Shradha Todi) - Make dw_pcie ops optional (Jisheng Zhang) - Remove unnecessary dw_pcie_ops from al driver (Jisheng Zhang) Xilinx Versal CPM PCIe controller driver: - Fix OF node reference leak (Pan Bian) Miscellaneous: - Remove tango host controller driver (Arnd Bergmann) - Remove IRQ handler & data together (altera-msi, brcmstb, dwc) (Martin Kaiser) - Fix xgene-msi race in installing chained IRQ handler (Martin Kaiser) - Apply CONFIG_PCI_DEBUG to entire drivers/pci hierarchy (Junhao He) - Fix pci-bridge-emul array overruns (Russell King) - Remove obsolete uses of WARN_ON(in_interrupt()) (Sebastian Andrzej Siewior)" * tag 'pci-v5.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (69 commits) PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064 PCI: qcom: Add support for ddrss_sf_tbu clock dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250 PCI: al: Remove useless dw_pcie_ops PCI: dwc: Don't assume the ops in dw_pcie always exist PCI: dwc: Add upper limit address for outbound iATU PCI: dwc: Change size to u64 for EP outbound iATU PCI: dwc: Drop support for config space in 'ranges' PCI: layerscape: Convert to builtin_platform_driver() PCI: layerscape: Add LX2160A rev2 EP mode support dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible strings PCI: dwc: Work around ECRC configuration issue PCI/portdrv: Report reset for frozen channel PCI/AER: Specify the type of Port that was reset PCI/ERR: Retain status from error notification PCI/AER: Clear AER status from Root Port when resetting Downstream Port PCI/ERR: Clear status of the reporting device dt-bindings: arm: rockchip: Add FriendlyARM NanoPi M4B PCI: rockchip: Make 'ep-gpios' DT property optional Documentation: PCI: Add PCI endpoint NTB function user guide ...
2021-02-24Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas
- Remove IRQ handler & data together for altera, brcmstb, dwc (Martin Kaiser) - Fix xgene race in installing chained IRQ handler (Martin Kaiser) - Drop PCIE_RCAR config option (replaced by PCIE_RCAR_HOST) (Lad Prabhakar) - Fix xgene comment about CRS vs CRS SV (Bjorn Helgaas) * remotes/lorenzo/pci/misc: PCI: hv: Fix typo PCI: xgene: Fix CRS SV comment PCI: brcmstb: Remove chained IRQ handler and data in one go PCI: Drop PCIE_RCAR config option PCI: xgene-msi: Fix race in installing chained irq handler PCI: dwc: Remove IRQ handler and data in one go PCI: altera-msi: Remove IRQ handler and data in one go
2021-02-24Merge branch 'remotes/lorenzo/pci/xilinx'Bjorn Helgaas
- Fix reference count leak on error path (Pan Bian) * remotes/lorenzo/pci/xilinx: PCI: xilinx-cpm: Fix reference count leak on error path
2021-02-24Merge branch 'remotes/lorenzo/pci/tango'Bjorn Helgaas
- Remove tango host controller driver (Arnd Bergmann) * remotes/lorenzo/pci/tango: PCI: Remove tango host controller driver # Conflicts: # drivers/pci/controller/Makefile
2021-02-24Merge branch 'pci/rockchip'Bjorn Helgaas
- Make 'ep-gpios' DT property optional (Chen-Yu Tsai) - Add FriendlyARM NanoPi M4B to rockchip DT binding (Chen-Yu Tsai) * pci/rockchip: dt-bindings: arm: rockchip: Add FriendlyARM NanoPi M4B PCI: rockchip: Make 'ep-gpios' DT property optional
2021-02-24Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas
- Always allocate rcar MSI addresses in 32-bit space so legacy devices without 64-bit MSI support can use MSI (Marek Vasut) * remotes/lorenzo/pci/rcar: PCI: rcar: Always allocate MSI addresses in 32bit space
2021-02-24Merge branch 'pci/qcom'Bjorn Helgaas
- Add support for SM8250 PCIe SF TBU clock (Dmitry Baryshkov) - Use PHY_REFCLK_USE_PAD only for qcom ipq8064 (Ansuel Smith) * pci/qcom: PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064 PCI: qcom: Add support for ddrss_sf_tbu clock dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250
2021-02-24Merge branch 'pci/ntb'Bjorn Helgaas
- Account for 64-bit BARs in pci_epc_get_first_free_bar() (Kishon Vijay Abraham I) - Add pci_epc_get_next_free_bar() helper (Kishon Vijay Abraham I) - Return error codes on failure of endpoint BAR interfaces (Kishon Vijay Abraham I) - Remove unused pci_epf_match_device() (Kishon Vijay Abraham I) - Add support for secondary endpoint controller to prepare for NTB endpoint functionality (Kishon Vijay Abraham I) - Add configfs support for secondary endpoint controller (Kishon Vijay Abraham I) - Add MSI address mapping ops for NTB doorbell support (Kishon Vijay Abraham I) - Add ops for endpoint function-specific attributes (Kishon Vijay Abraham I) - Allow configfs subdirectory for endpoint function configuration (Kishon Vijay Abraham I) - Implement cadence MSI address mapping ops (Kishon Vijay Abraham I) - Configure cadence LM_EP_FUNC_CFG based on epc->function_num_map (Kishon Vijay Abraham I) - Add endpoint-side driver to provide NTB functionality (Kishon Vijay Abraham I) - Add host-side driver for generic EPF NTB functionality (Kishon Vijay Abraham I) - Document NTB endpoint functionality (Kishon Vijay Abraham I) * pci/ntb: Documentation: PCI: Add PCI endpoint NTB function user guide Documentation: PCI: Add configfs binding documentation for pci-ntb endpoint function NTB: Add support for EPF PCI Non-Transparent Bridge PCI: Add TI J721E device to PCI IDs PCI: endpoint: Add EP function driver to provide NTB functionality PCI: cadence: Configure LM_EP_FUNC_CFG based on epc->function_num_map PCI: cadence: Implement ->msi_map_irq() ops PCI: endpoint: Allow user to create sub-directory of 'EPF Device' directory PCI: endpoint: Add pci_epf_ops to expose function-specific attrs PCI: endpoint: Add pci_epc_ops to map MSI IRQ PCI: endpoint: Add support in configfs to associate two EPCs with EPF PCI: endpoint: Add support to associate secondary EPC with EPF PCI: endpoint: Remove unused pci_epf_match_device() PCI: endpoint: Make *_free_bar() to return error codes on failure PCI: endpoint: Add helper API to get the 'next' unreserved BAR PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BAR Documentation: PCI: Add specification for the PCI NTB function device
2021-02-24Merge branch 'pci/microchip'Bjorn Helgaas
- Call platform_set_drvdata() earlier so drivers can do window setup in init functions instead of custom probe (Daire McNamara) - Add DT binding and host mode driver for Microchip PolarFire PCIe controller (Daire McNamara) * pci/microchip: MAINTAINERS: Add Daire McNamara as Microchip PCIe driver maintainer PCI: microchip: Add Microchip PolarFire PCIe controller driver dt-bindings: PCI: microchip: Add Microchip PolarFire host binding PCI: Call platform_set_drvdata earlier in devm_pci_alloc_host_bridge
2021-02-24Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas
- Fix of_node_put() reference leak (Krzysztof Wilczyński) * remotes/lorenzo/pci/mediatek: PCI: mediatek: Add missing of_node_put() to fix reference leak
2021-02-24Merge branch 'pci/layerscape'Bjorn Helgaas
- Add Layerscape LX2160A rev2 endpoint mode support (Hou Zhiqiang) - Convert layerscape to builtin_platform_driver() (Michael Walle) * pci/layerscape: PCI: layerscape: Convert to builtin_platform_driver() PCI: layerscape: Add LX2160A rev2 EP mode support dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible strings
2021-02-24Merge branch 'pci/dwc'Bjorn Helgaas
- Always set DesignWare "TLP Digest" bit so generic code can enable ECRC via the AER Capability (Vidya Sagar) - Drop support for config space in DT 'ranges' (Rob Herring) - Increase width of outbound iATU size to u64 (Shradha Todi) - Add upper limit address for outbound iATU (Shradha Todi) - Allow dwc-based drivers that don't override any default ops (Jisheng Zhang) - Drop unnecessary dw_pcie_ops from the al driver (Jisheng Zhang) * pci/dwc: PCI: al: Remove useless dw_pcie_ops PCI: dwc: Don't assume the ops in dw_pcie always exist PCI: dwc: Add upper limit address for outbound iATU PCI: dwc: Change size to u64 for EP outbound iATU PCI: dwc: Drop support for config space in 'ranges' PCI: dwc: Work around ECRC configuration issue
2021-02-24Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas
- Retrain Link to work around Gen2 training defect (Nadeem Athani) * remotes/lorenzo/pci/cadence: PCI: cadence: Retrain Link to work around Gen2 training defect
2021-02-24Merge branch 'remotes/lorenzo/pci/brcmstb'Bjorn Helgaas
- Add support for BCM4908 with external PERST# signal controller (Rafał Miłecki) * remotes/lorenzo/pci/brcmstb: PCI: brcmstb: support BCM4908 with external PERST# signal controller dt-bindings: PCI: brcmstb: add BCM4908 binding
2021-02-24Merge branch 'pci/misc'Bjorn Helgaas
- Align checking of syscall user config accessor return codes (Heiner Kallweit) - Fix "ordering" comment typos (Bjorn Helgaas) - Fix 'ARM/TEXAS INSTRUMENT KEYSTONE CLOCKSOURCE' capitalization in MAINTAINERS (Bjorn Helgaas) - Add Silicom Denmark vendor ID (Martin Hundebøll) - Apply CONFIG_PCI_DEBUG to entire drivers/pci hierarchy (Junhao He) - Remove WARN_ON(in_interrupt()) (Sebastian Andrzej Siewior) * pci/misc: PCI: Remove WARN_ON(in_interrupt()) PCI: Apply CONFIG_PCI_DEBUG to entire drivers/pci hierarchy PCI: Add Silicom Denmark vendor ID MAINTAINERS: Fix 'ARM/TEXAS INSTRUMENT KEYSTONE CLOCKSOURCE' capitalization Fix "ordering" comment typos PCI: Align checking of syscall user config accessors
2021-02-24Merge branch 'pci/host-probe-refactor'Bjorn Helgaas
- Fix merge botch in cdns_pcie_host_map_dma_ranges() (Krzysztof Wilczyński) * pci/host-probe-refactor: PCI: cadence: Fix DMA range mapping early return error
2021-02-24Merge branch 'pci/resource'Bjorn Helgaas
- Decline requests to resize BARs if platform requires us to preserve resource assignments (Ard Biesheuvel) * pci/resource: PCI: Decline to resize resources if boot config must be preserved
2021-02-24Merge branch 'pci/link'Bjorn Helgaas
- Remove bandwidth notification for now to avoid reporting spam (Bjorn Helgaas) * pci/link: PCI/LINK: Remove bandwidth notification
2021-02-24Merge branch 'pci/hotplug'Bjorn Helgaas
- Remove unused acpiphp_callback typedef (Chen Lin) * pci/hotplug: PCI: acpiphp: Remove unused acpiphp_callback typedef
2021-02-24Merge branch 'pci/error'Bjorn Helgaas
- Clear AER status of the reporting device (Keith Busch) - Clear AER status from Root Port when resetting Downstream Port (Keith Busch) - Retain status from error notification (Keith Busch) - Log the type of Port that was reset for error handling (Keith Busch) - Report reset for frozen channel (Keith Busch) * pci/error: PCI/portdrv: Report reset for frozen channel PCI/AER: Specify the type of Port that was reset PCI/ERR: Retain status from error notification PCI/AER: Clear AER status from Root Port when resetting Downstream Port PCI/ERR: Clear status of the reporting device
2021-02-24PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064Ansuel Smith
The use of PHY_REFCLK_USE_PAD introduced a regression for apq8064 devices. It was tested that while apq doesn't require the padding, ipq SoC must use it or the kernel hangs on boot. Link: https://lore.kernel.org/r/20201019165555.8269-1-ansuelsmth@gmail.com Fixes: de3c4bf64897 ("PCI: qcom: Add support for tx term offset for rev 2.1.0") Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: stable@vger.kernel.org # v4.19+
2021-02-24PCI: qcom: Add support for ddrss_sf_tbu clockDmitry Baryshkov
On SM8250 additional clock is required for PCIe devices to access NOC. Update PCIe controller driver to control this clock. Link: https://lore.kernel.org/r/20210117013114.441973-3-dmitry.baryshkov@linaro.org Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
2021-02-24PCI: al: Remove useless dw_pcie_opsJisheng Zhang
We have removed the assumption that dw_pcie_ops always exists in the dwc core driver, so we can remove the useless dw_pcie_ops now. Link: https://lore.kernel.org/r/20210128144324.2fa8577c@xhacker.debian Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jonathan Chocron <jonnyc@amazon.com>
2021-02-24PCI: dwc: Don't assume the ops in dw_pcie always existJisheng Zhang
Some dwc-based device drivers, especially host-only drivers, may work well with the default read_dbi/write_dbi/link_up implementations in pcie-designware.c, so remove the assumption that every driver implements them to simplify those drivers. Link: https://lore.kernel.org/r/20210128144258.10329aa4@xhacker.debian Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24PCI: dwc: Add upper limit address for outbound iATUShradha Todi
The size parameter is unsigned long type which can accept size > 4GB. In that case, the upper limit address must be programmed. Add support to program the upper limit address and set INCREASE_REGION_SIZE in case size > 4GB. Link: https://lore.kernel.org/r/1612250918-19610-1-git-send-email-shradha.t@samsung.com Signed-off-by: Shradha Todi <shradha.t@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Rob Herring <robh@kernel.org>
2021-02-24PCI: dwc: Change size to u64 for EP outbound iATUShradha Todi
Since outbound iATU permits size to be greater than 4GB for which the support is also available, allow EP function to send u64 size instead of truncating to u32. Link: https://lore.kernel.org/r/1609929900-19082-1-git-send-email-shradha.t@samsung.com Signed-off-by: Shradha Todi <shradha.t@samsung.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
2021-02-24PCI: dwc: Drop support for config space in 'ranges'Rob Herring
Since commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code"), the code setting dbi_base when the config space is defined in 'ranges' property instead of 'reg' is dead code as dbi_base is never NULL. Rather than fix this, let's just drop the code. Using ranges has been deprecated since 2014. The only platforms using this were exynos5440, i.MX6 and Spear13xx. Exynos5440 is dead and has been removed. i.MX6 and Spear13xx had PCIe support added just before this was deprecated and were fixed within a kernel release or 2. Link: https://lore.kernel.org/r/20201215194149.86831-1-robh@kernel.org Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24PCI: layerscape: Convert to builtin_platform_driver()Michael Walle
fw_devlink will defer the probe until all suppliers are ready. We can't use builtin_platform_driver_probe() because it doesn't retry after probe deferral. Convert it to builtin_platform_driver(). Link: https://lore.kernel.org/r/20210120105246.23218-1-michael@walle.cc Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24PCI: layerscape: Add LX2160A rev2 EP mode supportHou Zhiqiang
The LX2160A rev2 uses the same PCIe IP as LS2088A, but LX2160A rev2 PCIe controller is integrated with different stride between PFs' register address. Link: https://lore.kernel.org/r/20201026051448.1913-2-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-24PCI: dwc: Work around ECRC configuration issueVidya Sagar
DesignWare core has a TLP digest (TD) override bit in one of the control registers of ATU. This bit also needs to be programmed for proper ECRC functionality. This is currently identified as an issue with DesignWare IP version 4.90a. [bhelgaas: fix typos/grammar errors] Link: https://lore.kernel.org/r/20201230165723.673-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI/portdrv: Report reset for frozen channelKeith Busch
The PCI error recovery always resets the link for a frozen state, so the port driver should return that a reset is required for its result. This will get the .slot_reset() callback invoked, which is necessary to restore the port's config space. Without this, the driver had been relying on downstream drivers to return this status. Link: https://lore.kernel.org/r/20210104230300.1277180-6-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/AER: Specify the type of Port that was resetKeith Busch
The AER driver may be called upon to reset either a Downstream or a Root Port. Check which type it is to properly identify it when logging that the reset occurred. Link: https://lore.kernel.org/r/20210104230300.1277180-5-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/ERR: Retain status from error notificationKeith Busch
Overwriting the frozen detected status with the result of the link reset loses the NEED_RESET result that drivers are depending on for error handling to report the .slot_reset() callback. Retain this status so that subsequent error handling has the correct flow. Link: https://lore.kernel.org/r/20210104230300.1277180-4-kbusch@kernel.org Reported-by: Hinko Kocevar <hinko.kocevar@ess.eu> Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sean V Kelley <sean.v.kelley@intel.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/AER: Clear AER status from Root Port when resetting Downstream PortKeith Busch
The pci_dev parameter given to aer_root_reset() may be a Downstream Port rather than the Root Port. Get the Root Port from the provided device in order to clear the root's AER status. Link: https://lore.kernel.org/r/20210104230300.1277180-3-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sean V Kelley <sean.v.kelley@intel.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI/ERR: Clear status of the reporting deviceKeith Busch
Error handling operates on the first Downstream Port above the detected error, but the error may have been reported by a downstream device. Clear the AER status of the device that reported the error rather than the first Downstream Port. Link: https://lore.kernel.org/r/20210104230300.1277180-2-kbusch@kernel.org Tested-by: Hedi Berriche <hedi.berriche@hpe.com> Signed-off-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sean V Kelley <sean.v.kelley@intel.com> Acked-by: Hedi Berriche <hedi.berriche@hpe.com>
2021-02-23PCI: rockchip: Make 'ep-gpios' DT property optionalChen-Yu Tsai
The Rockchip PCIe controller DT binding clearly states that 'ep-gpios' is an optional property. And indeed there are boards that don't require it. Make the driver follow the binding by using devm_gpiod_get_optional() instead of devm_gpiod_get(). [bhelgaas: tidy whitespace] Link: https://lore.kernel.org/r/20210121162321.4538-2-wens@kernel.org Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Fixes: 964bac9455be ("PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Add EP function driver to provide NTB functionalityKishon Vijay Abraham I
Add a new endpoint function driver to provide NTB functionality using multiple PCIe endpoint instances. [arnd@arndb.de: Select configfs dependency] [yebin10@huawei.com: Fix unused but set variables] [geert+renesas@glider.be: Explain NTB in PCI_EPF_NTB help text] Link: https://lore.kernel.org/r/20210201195809.7342-14-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ye Bin <yebin10@huawei.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: cadence: Configure LM_EP_FUNC_CFG based on epc->function_num_mapKishon Vijay Abraham I
The number of functions supported by the endpoint controller is configured in LM_EP_FUNC_CFG based on func_no member of struct pci_epf. Now that an endpoint function can be associated with two endpoint controllers (primary and secondary), just using func_no will not suffice as that will take into account only if the endpoint controller is associated with the primary interface of endpoint function. Instead use epc->function_num_map which will already have the configured functions information (irrespective of whether the endpoint controller is associated with primary or secondary interface). Link: https://lore.kernel.org/r/20210201195809.7342-13-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tom Joseph <tjoseph@cadence.com>
2021-02-23PCI: cadence: Implement ->msi_map_irq() opsKishon Vijay Abraham I
Implement ->msi_map_irq() ops in order to map physical address to MSI address and return MSI data. Link: https://lore.kernel.org/r/20210201195809.7342-12-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Tom Joseph <tjoseph@cadence.com>
2021-02-23PCI: endpoint: Allow user to create sub-directory of 'EPF Device' directoryKishon Vijay Abraham I
Documentation/PCI/endpoint/pci-endpoint-cfs.rst explains how a user has to create a directory in-order to create a 'EPF Device' that can be configured/probed by 'EPF Driver'. Allow user to create a sub-directory of 'EPF Device' directory for any function specific attributes that has to be exposed to the user. Link: https://lore.kernel.org/r/20210201195809.7342-11-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Add pci_epf_ops to expose function-specific attrsKishon Vijay Abraham I
In addition to the attributes that are generic across function drivers documented in Documentation/PCI/endpoint/pci-endpoint-cfs.rst, there could be function-specific attributes that has to be exposed by the function driver to be configured by the user. Add ->add_cfs() in pci_epf_ops to be populated by the function driver if it has to expose any function-specific attributes and pci_epf_type_add_cfs() to be invoked by pci-ep-cfs.c when sub-directory to main function directory is created. Link: https://lore.kernel.org/r/20210201195809.7342-10-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Add pci_epc_ops to map MSI IRQKishon Vijay Abraham I
Add pci_epc_ops to map physical address to MSI address and return MSI data. The physical address is an address in the outbound region. This is required to implement doorbell functionality of NTB (non-transparent bridge) wherein EPC on either side of the interface (primary and secondary) can directly write to the physical address (in outbound region) of the other interface to ring doorbell using MSI. Link: https://lore.kernel.org/r/20210201195809.7342-9-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Add support in configfs to associate two EPCs with EPFKishon Vijay Abraham I
Now that PCI endpoint core supports to add secondary endpoint controller (EPC) with endpoint function (EPF), Add support in configfs to associate two EPCs with EPF. This creates "primary" and "secondary" directory inside the directory created by users for EPF device. Users have to add a symlink of endpoint controller (pci_ep/controllers/) to "primary" or "secondary" directory to bind EPF to primary and secondary EPF interfaces respectively. Existing method of linking directory representing EPF device to directory representing EPC device to associate a single EPC device with a EPF device will continue to work. Link: https://lore.kernel.org/r/20210201195809.7342-8-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Add support to associate secondary EPC with EPFKishon Vijay Abraham I
In the case of standard endpoint functions, only one endpoint controller (EPC) will be associated with an endpoint function (EPF). However for providing NTB (non transparent bridge) functionality, two EPCs should be associated with a single EPF. Add support to associate secondary EPC with EPF. This is in preparation for adding NTB endpoint function driver. Link: https://lore.kernel.org/r/20210201195809.7342-7-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Remove unused pci_epf_match_device()Kishon Vijay Abraham I
Remove unused pci_epf_match_device() function added in pci-epf-core.c Link: https://lore.kernel.org/r/20210201195809.7342-6-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Make *_free_bar() to return error codes on failureKishon Vijay Abraham I
Modify pci_epc_get_next_free_bar() and pci_epc_get_first_free_bar() to return error values if there are no free BARs available. Link: https://lore.kernel.org/r/20210201195809.7342-5-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Add helper API to get the 'next' unreserved BARKishon Vijay Abraham I
Add an API to get the next unreserved BAR starting from a given BAR number that can be used by the endpoint function. Link: https://lore.kernel.org/r/20210201195809.7342-4-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit BARKishon Vijay Abraham I
pci_epc_get_first_free_bar() uses only "reserved_bar" member in epc_features to get the first unreserved BAR. However if the reserved BAR is also a 64-bit BAR, then the next BAR shouldn't be returned (since 64-bit BAR uses two BARs). Make pci_epc_get_first_free_bar() take into account 64 bit BAR while returning the first free unreserved BAR. Link: https://lore.kernel.org/r/20210201195809.7342-3-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2021-02-23PCI: microchip: Add Microchip PolarFire PCIe controller driverDaire McNamara
Add support for the Microchip PolarFire PCIe controller when configured in host (Root Complex) mode. [bhelgaas: wrap lines to fit in 80 columns, fix trivial style issues] Link: https://lore.kernel.org/r/20210125162934.5335-4-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> [lorenzo.pieralisi@arm.com: minor comments tweak] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
2021-02-23PCI: Call platform_set_drvdata earlier in devm_pci_alloc_host_bridgeDaire McNamara
Many drivers can now use pci_host_common_probe() directly. Their hardware window setup can be moved from their 'custom' probe functions to individual driver init functions. Link: https://lore.kernel.org/r/20210125162934.5335-2-daire.mcnamara@microchip.com Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 19:33:17 +0000