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path: root/drivers/soc/mediatek/mtk-mmsys.c
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2022-09-15soc: mediatek: Add mmsys func to adapt to dpi output for MT8186Xinlei Lee
Add mmsys func to manipulate dpi output format config for MT8186. Co-developed-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> Reviewed-by: Nís F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/all/1663161662-1598-2-git-send-email-xinlei.lee@mediatek.com/ Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-22Merge tag 'v5.18-next-vdso0-stable-tag' into v5.18-next/socMatthias Brugger
2022-04-22soc: mediatek: add mtk-mmsys support for mt8195 vdosys0jason-jh.lin
1. Add mt8195 mmsys compatible for 2 vdosys. 2. Add io_start into each driver data of mt8195 vdosys. 3. Add get match data function to identify mmsys by io_start. 4. Add mt8195 routing table settings of vdosys0. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://lore.kernel.org/r/20220419094143.9561-2-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-04-04soc: mediatek: mmsys: Add sw0_rst_offset for MT8192AngeloGioacchino Del Regno
MT8192 has the same sw0 reset offset as MT8186: add the parameter to be able to use mmsys as a reset controller for managing at least the DSI reset line. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Link: https://lore.kernel.org/r/20220323091932.10648-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-04soc: mediatek: mmsys: add sw0_rst_offset in mmsys driver dataRex-BC Chen
There are different software reset registers for difference MTK SoCs. Therefore, we add a new variable "sw0_rst_offset" to control it. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220217082626.15728-2-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-03-01soc: mediatek: mmsys: add mmsys reset control for MT8186Rex-BC Chen
Add mmsys reset control register 0x160 for MT8186. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Link: https://lore.kernel.org/r/20220217082626.15728-3-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2022-02-28soc: mediatek: mmsys: add mt8186 mmsys routing tableYongqiang Niu
Add new routing table for MT8186. In MT8186, there are two routing pipelines for internal and external display. Internal display: OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0-> DITHER->DSI0 External display: OVL_2L0->RDMA1->DPI0 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-10-08soc: mediatek: mmsys: Add reset controller supportEnric Balletbo i Serra
Among other features the mmsys driver should implement a reset controller to be able to reset different bits from their space. Cc: Jitao Shi <jitao.shi@mediatek.com> Suggested-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210930103105.v4.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-09-13soc: mediatek: mmsys: Add mt8192 mmsys routing tableYongqiang Niu
mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Link: https://lore.kernel.org/r/1627894773-23872-3-git-send-email-yongqiang.niu@mediatek.com [mb: take mask into account] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-08-06soc: mediatek: mmsys: add MT8365 supportFabien Parent
Add DSI mmsys connections for the MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com [mb: take the mask field into account] Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-08-04soc: mmsys: mediatek: add mask to mmsys routesCK Hu
SOUT has many bits and need to be cleared before set new value. Write only could do the clear, but for MOUT, it clears bits that should not be cleared. So use a mask to reset only the needed bits. this fixes HDMI issues on MT7623/BPI-R2 since 5.13 Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210729070549.5514-1-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-04-06soc: mediatek: mmsys: Add support for MT8167 SoCFabien Parent
Add routing table for DSI on MT8167 SoC. The registers are mostly incompatible with the current defines, so new one for MT8167 are added. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20210405200354.2194930-2-fparent@baylibre.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-31soc: mediatek: mmsys: Add mt8183 mmsys routing tableHsin-Yi Wang
mt8183 has different routing registers than mt8173. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210330110423.3542163-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30soc: mediatek: mmsys: Use an array for setting the routing registersCK Hu
Actually, setting the registers for routing, use multiple 'if-else' for different routes, but this code would be more and more complicated while we support more and more SoCs. Change that and use a table per SoC so the code will be more portable and clear. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210317181711.795245-3-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30soc: mediatek: mmsys: Create struct mtk_mmsys to store context dataCK Hu
Apart from the driver data, in order to extend the driver to support more and more SoCs, we will need to store other configuration data. So, create a mtk_mmsys struct to encapsulate all that information. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/20210317181711.795245-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-28soc: mediatek: mmsys: Use devm_platform_ioremap_resource()Enric Balletbo i Serra
For the common platform_get_resource()+devm_platform_ioremap() combination, there is a helper, so use it and make the code a bit more compact. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/20201006193320.405529-3-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-28soc / drm: mediatek: Move DDP component defines into mtk-mmsys.hYongqiang Niu
MMSYS is the driver which controls the routing of these DDP components, so the definition of the mtk_ddp_comp_id enum should be placed in mtk-mmsys.h Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://lore.kernel.org/r/20201006193320.405529-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-20clk/soc: mediatek: mt6779: Bind clock driver from platform deviceMatthias Brugger
The mmsys driver is now the top level entry point for the multimedia system (mmsys), we bind the clock driver by creating a platform device. We also bind the MediaTek DRM driver which is not yet implement and therefor will errror out for now. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200518113156.25009-3-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-20clk/soc: mediatek: mt6797: Bind clock driver from platform deviceMatthias Brugger
The mmsys driver is now the top level entry point for the multimedia system (mmsys), we bind the clock driver by creating a platform device. We also bind the MediaTek DRM driver which is not yet implement and therefor will errror out for now. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200518113156.25009-2-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-20clk/soc: mediatek: mt8183: Bind clock driver from platform deviceMatthias Brugger
The mmsys driver is now the top level entry point for the multimedia system (mmsys), we bind the clock driver by creating a platform device. We also bind the MediaTek DRM driver which is not yet implement and therefor will errror out for now. Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200518113156.25009-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-20clk / soc: mediatek: Bind clock and gpu driver for mt2701Enric Balletbo i Serra
Now that the mmsys driver is the top-level entry point for the multimedia subsystem, we could bind the clock and the gpu driver on those devices that is expected to work, so the drm driver is intantiated by the mmsys driver and display, hopefully, working again. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200401201736.2980433-3-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-20clk / soc: mediatek: Bind clock and gpu driver for mt2712Enric Balletbo i Serra
Now that the mmsys driver is the top-level entry point for the multimedia subsystem, we could bind the clock and the gpu driver on those devices that is expected to work, so the drm driver is intantiated by the mmsys driver and display, hopefully, working again on those devices. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200401201736.2980433-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-15soc: mediatek: Missing platform_device_unregister() on error in ↵Wei Yongjun
mtk_mmsys_probe() Add the missing platform_device_unregister() before return from mtk_mmsys_probe() in the error handling case. Fixes: 667c769246b0 ("soc / drm: mediatek: Fix mediatek-drm device probing") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20200506141317.119537-1-weiyongjun1@huawei.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-05-14soc: mediatek: mmsys: Drop <linux/clk-provider.h>Geert Uytterhoeven
After the split, the mt8173 MMSYS driver is no longer a clock provider, and thus does not need to include <linux/clk-provider.h>. Fixes: 13032709e2328553 ("clk / soc: mediatek: Move mt8173 MMSYS to platform driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200506120204.31422-1-geert+renesas@glider.be Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13soc / drm: mediatek: Fix mediatek-drm device probingEnric Balletbo i Serra
In the actual implementation the same compatible string "mediatek,<chip>-mmsys" is used to bind the clock drivers (drivers/soc/mediatek) as well as to the gpu driver (drivers/gpu/drm/mediatek/mtk_drm_drv.c). This ends with the problem that the only probed driver is the clock driver and there is no display at all. In any case having the same compatible string for two drivers is not correct and should be fixed. To fix this, and maintain backward compatibility, we can consider that the mmsys driver is the top-level entry point for the multimedia subsystem, so is not a pure clock controller but a system controller, and the drm driver is instantiated by that MMSYS driver. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13soc / drm: mediatek: Move routing control to mmsys deviceEnric Balletbo i Serra
Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path(). Those functions will allow DRM driver and others to control the data path routing. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com> Tested-by: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-04-13clk / soc: mediatek: Move mt8173 MMSYS to platform driverMatthias Brugger
There is no strong reason for this to use CLK_OF_DECLARE instead of being a platform driver. Plus, MMSYS provides clocks but also a shared register space for the mediatek-drm and the mediatek-mdp driver. So move the MMSYS clocks to a new platform driver and also create a new MMSYS platform driver in drivers/soc/mediatek that instantiates the clock driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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