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2022-12-31soc: sifive: ccache: fix missing of_node_put() in sifive_ccache_init()Yang Yingliang
[ Upstream commit 8fbf94fea0b4e187ca9100936c5429f96b8a4e44 ] The device_node pointer returned by of_find_matching_node() with refcount incremented, when finish using it, the refcount need be decreased. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31soc: sifive: ccache: fix missing free_irq() in error path in ↵Yang Yingliang
sifive_ccache_init() [ Upstream commit 756344e7cb1afbb87da8705c20384dddd0dea233 ] Add missing free_irq() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-12-31soc: sifive: ccache: fix missing iounmap() in error path in sifive_ccache_init()Yang Yingliang
[ Upstream commit 73e770f085023da327dc9ffeb6cd96b0bb22d97e ] Add missing iounmap() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-10-13soc: sifive: ccache: define the macro for the register shiftsZong Li
Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-7-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-13soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixesBen Dooks
Use the pr_fmt() macro to prefix all the output with "CCACHE:" to avoid having to write it out each time, or make a large diff when the next change comes along. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-6-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-13soc: sifive: ccache: reduce printing on initBen Dooks
The driver prints out 6 lines on startup, which can easily be redcued to two lines without losing any information. Note, to make the types work better, uint64_t has been replaced with ULL to make the unsigned long long match the format in the print statement. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-5-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-13soc: sifive: ccache: determine the cache level from dtsZong Li
Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-4-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-13soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.Greentime Hu
Since composable cache may be L3 cache if there is a L2 cache, we should use its original name composable cache to prevent confusion. There are some new lines were generated due to adding the compatible "sifive,ccache0" into ID table and indent requirement. The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to apply the change as well. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220913061817.22564-3-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2021-01-07RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740Yash Shah
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540. Update the L2 cache controller driver to support this additional interrupt in case of FU740-C000 chip. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-28soc: sifive: l2 cache: Mark l2_get_priv_group as staticPalmer Dabbelt
The kbuild test robot is firing a warning over a missing prototype. The function can just be static. Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-28soc: sifive: l2 cache: Eliminate an unsigned zero compare warningPalmer Dabbelt
GCC warns about this comparison, which is unnecessary. Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-20riscv: Add support to determine no. of L2 cache way enabledYash Shah
In order to determine the number of L2 cache ways enabled at runtime, implement a private attribute ("number_of_ways_enabled"). Reading this attribute returns the number of enabled L2 cache ways at runtime. Using riscv_set_cacheinfo_ops() hook a custom function, that returns this private attribute, to the generic ops structure which is used by cache_get_priv_group() in cacheinfo framework. Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-01-12riscv: move sifive_l2_cache.h to include/socYash Shah
The commit 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") moves the sifive L2 cache driver to driver/soc. It did not move the header file along with the driver. Therefore this patch moves the header file to driver/soc Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: updated to fix the include guard] Fixes: 9209fb51896f ("riscv: move sifive_l2_cache.c to drivers/soc") Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-12-20riscv: move sifive_l2_cache.c to drivers/socChristoph Hellwig
The sifive_l2_cache.c is in no way related to RISC-V architecture memory management. It is a little stub driver working around the fact that the EDAC maintainers prefer their drivers to be structured in a certain way that doesn't fit the SiFive SOCs. Move the file to drivers/soc and add a Kconfig option for it, as well as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE. Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Borislav Petkov <bp@suse.de> [paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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