| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-06-25 | clk: socfpga: stratix10: add additional clocks needed for the NAND IP | Dinh Nguyen | |
| The nand_clk is actually called the nand_x_clk and the parent is the l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the nand_x_clk and has a fixed divider of 4. The same is true for the nand_ecc_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> | |||
| 2018-04-06 | dt-bindings: documentation: add clock bindings information for Stratix10 | Dinh Nguyen | |
| Document that Stratix10 clock bindings, and add the clock header file. The clock header is an enumeration of all the different clocks on the Stratix10 platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> | |||
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